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hw/i2c: Implement NPCM7XX SMBus Module Single Mode
This commit implements the single-byte mode of the SMBus. Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses compliant with SMBus and I2C protocol. This patch implements the single-byte mode of the SMBus. In this mode, the user sends or receives a byte each time. The SMBus device transmits it to the underlying i2c device and sends an interrupt back to the QEMU guest. Reviewed-by: Doug Evans<dje@google.com> Reviewed-by: Tyrong Ting<kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Corey Minyard <cminyard@mvista.com> Message-id: 20210210220426.3577804-2-wuhaotsh@google.com Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu
Peter Maydell
@@ -43,6 +43,7 @@ Supported devices
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* GPIO controller
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* Analog to Digital Converter (ADC)
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* Pulse Width Modulation (PWM)
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* SMBus controller (SMBF)
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Missing devices
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---------------
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@@ -58,7 +59,6 @@ Missing devices
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* Ethernet controllers (GMAC and EMC)
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* USB device (USBD)
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* SMBus controller (SMBF)
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* Peripheral SPI controller (PSPI)
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* SD/MMC host
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* PECI interface
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+52
-16
@@ -102,6 +102,22 @@ enum NPCM7xxInterrupt {
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NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
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NPCM7XX_EHCI_IRQ = 61,
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NPCM7XX_OHCI_IRQ = 62,
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NPCM7XX_SMBUS0_IRQ = 64,
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NPCM7XX_SMBUS1_IRQ,
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NPCM7XX_SMBUS2_IRQ,
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NPCM7XX_SMBUS3_IRQ,
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NPCM7XX_SMBUS4_IRQ,
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NPCM7XX_SMBUS5_IRQ,
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NPCM7XX_SMBUS6_IRQ,
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NPCM7XX_SMBUS7_IRQ,
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NPCM7XX_SMBUS8_IRQ,
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NPCM7XX_SMBUS9_IRQ,
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NPCM7XX_SMBUS10_IRQ,
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NPCM7XX_SMBUS11_IRQ,
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NPCM7XX_SMBUS12_IRQ,
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NPCM7XX_SMBUS13_IRQ,
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NPCM7XX_SMBUS14_IRQ,
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NPCM7XX_SMBUS15_IRQ,
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NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
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NPCM7XX_PWM1_IRQ, /* PWM module 1 */
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NPCM7XX_GPIO0_IRQ = 116,
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@@ -152,6 +168,26 @@ static const hwaddr npcm7xx_pwm_addr[] = {
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0xf0104000,
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};
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/* Direct memory-mapped access to each SMBus Module. */
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static const hwaddr npcm7xx_smbus_addr[] = {
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0xf0080000,
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0xf0081000,
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0xf0082000,
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0xf0083000,
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0xf0084000,
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0xf0085000,
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0xf0086000,
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0xf0087000,
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0xf0088000,
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0xf0089000,
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0xf008a000,
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0xf008b000,
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0xf008c000,
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0xf008d000,
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0xf008e000,
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0xf008f000,
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};
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static const struct {
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hwaddr regs_addr;
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uint32_t unconnected_pins;
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@@ -353,6 +389,11 @@ static void npcm7xx_init(Object *obj)
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object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
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}
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for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
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object_initialize_child(obj, "smbus[*]", &s->smbus[i],
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TYPE_NPCM7XX_SMBUS);
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}
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object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
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object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
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@@ -509,6 +550,17 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
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npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
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}
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/* SMBus modules. Cannot fail. */
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QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus));
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for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
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Object *obj = OBJECT(&s->smbus[i]);
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sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
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npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i));
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}
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/* USB Host */
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object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
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&error_abort);
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@@ -576,22 +628,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
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create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
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create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
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create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB);
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create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB);
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create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB);
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create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
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create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
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@@ -9,6 +9,7 @@ i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c'))
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i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c'))
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i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c'))
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i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c'))
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i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c'))
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i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c'))
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i2c_ss.add(when: 'CONFIG_VERSATILE_I2C', if_true: files('versatile_i2c.c'))
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i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c'))
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File diff suppressed because it is too large
Load Diff
@@ -14,3 +14,14 @@ aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t val
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aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64
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aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s send %d/%d 0x%02x"
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aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) "%s recv %d/%d 0x%02x"
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# npcm7xx_smbus.c
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npcm7xx_smbus_read(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
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npcm7xx_smbus_write(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
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npcm7xx_smbus_start(const char *id, int success) "%s starting, success: %d"
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npcm7xx_smbus_send_address(const char *id, uint8_t addr, int recv, int success) "%s sending address: 0x%02x, recv: %d, success: %d"
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npcm7xx_smbus_send_byte(const char *id, uint8_t value, int success) "%s send byte: 0x%02x, success: %d"
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npcm7xx_smbus_recv_byte(const char *id, uint8_t value) "%s recv byte: 0x%02x"
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npcm7xx_smbus_stop(const char *id) "%s stopping"
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npcm7xx_smbus_nack(const char *id) "%s nacking"
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@@ -20,6 +20,7 @@
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#include "hw/adc/npcm7xx_adc.h"
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#include "hw/cpu/a9mpcore.h"
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#include "hw/gpio/npcm7xx_gpio.h"
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#include "hw/i2c/npcm7xx_smbus.h"
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#include "hw/mem/npcm7xx_mc.h"
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#include "hw/misc/npcm7xx_clk.h"
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#include "hw/misc/npcm7xx_gcr.h"
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@@ -85,6 +86,7 @@ typedef struct NPCM7xxState {
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NPCM7xxMCState mc;
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NPCM7xxRNGState rng;
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NPCM7xxGPIOState gpio[8];
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NPCM7xxSMBusState smbus[16];
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EHCISysBusState ehci;
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OHCISysBusState ohci;
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NPCM7xxFIUState fiu[2];
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@@ -0,0 +1,88 @@
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/*
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* Nuvoton NPCM7xx SMBus Module.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_SMBUS_H
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#define NPCM7XX_SMBUS_H
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#include "exec/memory.h"
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#include "hw/i2c/i2c.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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/*
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* Number of addresses this module contains. Do not change this without
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* incrementing the version_id in the vmstate.
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*/
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#define NPCM7XX_SMBUS_NR_ADDRS 10
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typedef enum NPCM7xxSMBusStatus {
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NPCM7XX_SMBUS_STATUS_IDLE,
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NPCM7XX_SMBUS_STATUS_SENDING,
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NPCM7XX_SMBUS_STATUS_RECEIVING,
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NPCM7XX_SMBUS_STATUS_NEGACK,
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NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE,
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NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK,
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} NPCM7xxSMBusStatus;
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/*
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* struct NPCM7xxSMBusState - System Management Bus device state.
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* @bus: The underlying I2C Bus.
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* @irq: GIC interrupt line to fire on events (if enabled).
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* @sda: The serial data register.
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* @st: The status register.
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* @cst: The control status register.
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* @cst2: The control status register 2.
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* @cst3: The control status register 3.
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* @ctl1: The control register 1.
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* @ctl2: The control register 2.
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* @ctl3: The control register 3.
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* @ctl4: The control register 4.
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* @ctl5: The control register 5.
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* @addr: The SMBus module's own addresses on the I2C bus.
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* @scllt: The SCL low time register.
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* @sclht: The SCL high time register.
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* @status: The current status of the SMBus.
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*/
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typedef struct NPCM7xxSMBusState {
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SysBusDevice parent;
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MemoryRegion iomem;
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I2CBus *bus;
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qemu_irq irq;
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uint8_t sda;
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uint8_t st;
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uint8_t cst;
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uint8_t cst2;
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uint8_t cst3;
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uint8_t ctl1;
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uint8_t ctl2;
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uint8_t ctl3;
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uint8_t ctl4;
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uint8_t ctl5;
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uint8_t addr[NPCM7XX_SMBUS_NR_ADDRS];
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uint8_t scllt;
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uint8_t sclht;
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NPCM7xxSMBusStatus status;
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} NPCM7xxSMBusState;
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#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
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#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \
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TYPE_NPCM7XX_SMBUS)
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#endif /* NPCM7XX_SMBUS_H */
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