linux-user: Move get_elf_hwcap to sh4/elfload.c

Change the return type to abi_ulong, and pass in the cpu.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2025-08-28 06:39:25 +10:00
parent 48004ab058
commit 92c9983c06
4 changed files with 32 additions and 29 deletions
+1 -28
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@@ -963,34 +963,7 @@ static inline void elf_core_copy_regs(target_elf_gregset_t *regs,
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
enum {
SH_CPU_HAS_FPU = 0x0001, /* Hardware FPU support */
SH_CPU_HAS_P2_FLUSH_BUG = 0x0002, /* Need to flush the cache in P2 area */
SH_CPU_HAS_MMU_PAGE_ASSOC = 0x0004, /* SH3: TLB way selection bit support */
SH_CPU_HAS_DSP = 0x0008, /* SH-DSP: DSP support */
SH_CPU_HAS_PERF_COUNTER = 0x0010, /* Hardware performance counters */
SH_CPU_HAS_PTEA = 0x0020, /* PTEA register */
SH_CPU_HAS_LLSC = 0x0040, /* movli.l/movco.l */
SH_CPU_HAS_L2_CACHE = 0x0080, /* Secondary cache / URAM */
SH_CPU_HAS_OP32 = 0x0100, /* 32-bit instruction support */
SH_CPU_HAS_PTEAEX = 0x0200, /* PTE ASID Extension support */
};
#define ELF_HWCAP get_elf_hwcap()
static uint32_t get_elf_hwcap(void)
{
SuperHCPU *cpu = SUPERH_CPU(thread_cpu);
uint32_t hwcap = 0;
hwcap |= SH_CPU_HAS_FPU;
if (cpu->env.features & SH_FEATURE_SH4A) {
hwcap |= SH_CPU_HAS_LLSC;
}
return hwcap;
}
#define ELF_HWCAP get_elf_hwcap(thread_cpu)
#endif
+2 -1
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@@ -103,7 +103,8 @@ const char *get_elf_cpu_model(uint32_t eflags);
#if defined(TARGET_I386) || defined(TARGET_X86_64) || defined(TARGET_ARM) \
|| defined(TARGET_SPARC) || defined(TARGET_PPC) \
|| defined(TARGET_LOONGARCH64) || defined(TARGET_MIPS)
|| defined(TARGET_LOONGARCH64) || defined(TARGET_MIPS) \
|| defined(TARGET_SH4)
abi_ulong get_elf_hwcap(CPUState *cs);
abi_ulong get_elf_hwcap2(CPUState *cs);
#endif
+27
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@@ -9,3 +9,30 @@ const char *get_elf_cpu_model(uint32_t eflags)
{
return "sh7785";
}
enum {
SH_CPU_HAS_FPU = 0x0001, /* Hardware FPU support */
SH_CPU_HAS_P2_FLUSH_BUG = 0x0002, /* Need to flush the cache in P2 area */
SH_CPU_HAS_MMU_PAGE_ASSOC = 0x0004, /* SH3: TLB way selection bit support */
SH_CPU_HAS_DSP = 0x0008, /* SH-DSP: DSP support */
SH_CPU_HAS_PERF_COUNTER = 0x0010, /* Hardware performance counters */
SH_CPU_HAS_PTEA = 0x0020, /* PTEA register */
SH_CPU_HAS_LLSC = 0x0040, /* movli.l/movco.l */
SH_CPU_HAS_L2_CACHE = 0x0080, /* Secondary cache / URAM */
SH_CPU_HAS_OP32 = 0x0100, /* 32-bit instruction support */
SH_CPU_HAS_PTEAEX = 0x0200, /* PTE ASID Extension support */
};
abi_ulong get_elf_hwcap(CPUState *cs)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
abi_ulong hwcap = 0;
hwcap |= SH_CPU_HAS_FPU;
if (cpu->env.features & SH_FEATURE_SH4A) {
hwcap |= SH_CPU_HAS_LLSC;
}
return hwcap;
}
+2
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@@ -8,4 +8,6 @@
#ifndef SH4_TARGET_ELF_H
#define SH4_TARGET_ELF_H
#define HAVE_ELF_HWCAP 1
#endif