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Merge remote-tracking branch 'remotes/hdeller/tags/hppa-updates-pull-request' into staging

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Fixes and updates for hppa target

This patchset fixes some important bugs in the hppa artist graphics driver:
- Fix artist graphics for HP-UX and Linux
- Mouse cursor fixes for HP-UX
- Fix draw_line() function on artist graphic

and it adds new qemu features for hppa:
- Allow up to 16 emulated CPUs (instead of 8)
- Add support for an emulated TOC/NMI button

A new Seabios-hppa firmware is included as well:
- Update SeaBIOS-hppa to VERSION 3
- New opt/hostid fw_cfg option to change hostid
- Add opt/console fw_cfg option to select default console
- Added 16x32 font to STI firmware

Signed-off-by: Helge Deller <deller@gmx.de>

# gpg: Signature made Wed 02 Feb 2022 18:08:34 GMT
# gpg:                using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg:                 aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D  25F8 3E5F 3D04 A7A2 4603
#      Subkey fingerprint: BCE9 123E 1AD2 9F07 C049  BBDE F712 B510 A23A 0F5F

* remotes/hdeller/tags/hppa-updates-pull-request:
  hw/display/artist: Fix draw_line() artefacts
  hw/display/artist: Mouse cursor fixes for HP-UX
  hw/display/artist: rewrite vram access mode handling
  hppa: Add support for an emulated TOC/NMI button.
  hw/hppa: Allow up to 16 emulated CPUs
  seabios-hppa: Update SeaBIOS-hppa to VERSION 3

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2022-02-02 19:54:30 +00:00
parent f7c0e223ac d449eee3af
commit 8f3e5ce773
13 changed files with 283 additions and 275 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/display/artist.c
+199 -264
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File diff suppressed because it is too large Load Diff
hw/display/trace-events
+4 -4
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@@ -140,10 +140,10 @@ ati_mm_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%
ati_mm_write(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 " %s <- 0x%"PRIx64
# artist.c
artist_reg_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 "%s -> 0x%"PRIx64
artist_reg_write(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 "%s <- 0x%"PRIx64
artist_vram_read(unsigned int size, uint64_t addr, int posx, int posy, uint64_t val) "%u 0x%"PRIx64 " %ux%u-> 0x%"PRIx64
artist_vram_write(unsigned int size, uint64_t addr, uint64_t val) "%u 0x%"PRIx64 " <- 0x%"PRIx64
artist_reg_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 "%s -> 0x%08"PRIx64
artist_reg_write(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 "%s <- 0x%08"PRIx64
artist_vram_read(unsigned int size, uint64_t addr, uint64_t val) "%u 0x%08"PRIx64 " -> 0x%08"PRIx64
artist_vram_write(unsigned int size, uint64_t addr, uint64_t val) "%u 0x%08"PRIx64 " <- 0x%08"PRIx64
artist_fill_window(unsigned int start_x, unsigned int start_y, unsigned int width, unsigned int height, uint32_t op, uint32_t ctlpln) "start=%ux%u length=%ux%u op=0x%08x ctlpln=0x%08x"
artist_block_move(unsigned int start_x, unsigned int start_y, unsigned int dest_x, unsigned int dest_y, unsigned int width, unsigned int height) "source %ux%u -> dest %ux%u size %ux%u"
artist_draw_line(unsigned int start_x, unsigned int start_y, unsigned int end_x, unsigned int end_y) "%ux%u %ux%u"
hw/hppa/hppa_hardware.h
+3 -2
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@@ -25,7 +25,7 @@
#define LASI_GFX_HPA 0xf8000000
#define ARTIST_FB_ADDR 0xf9000000
#define CPU_HPA 0xfffb0000
#define MEMORY_HPA 0xfffbf000
#define MEMORY_HPA 0xfffff000
#define PCI_HPA DINO_HPA /* PCI bus */
#define IDE_HPA 0xf9000000 /* Boot disc controller */
@@ -43,9 +43,10 @@
#define PORT_SERIAL1 (DINO_UART_HPA + 0x800)
#define PORT_SERIAL2 (LASI_UART_HPA + 0x800)
#define HPPA_MAX_CPUS 8 /* max. number of SMP CPUs */
#define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */
#define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */
#define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */
#define PIM_STORAGE_SIZE 600 /* storage size of pdc_pim_toc_struct (64bit) */
#endif
hw/hppa/machine.c
+34 -1
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@@ -17,6 +17,7 @@
#include "hw/timer/i8254.h"
#include "hw/char/serial.h"
#include "hw/net/lasi_82596.h"
#include "hw/nmi.h"
#include "hppa_sys.h"
#include "qemu/units.h"
#include "qapi/error.h"
@@ -355,6 +356,14 @@ static void hppa_machine_reset(MachineState *ms)
cpu[0]->env.gr[19] = FW_CFG_IO_BASE;
}
static void hppa_nmi(NMIState *n, int cpu_index, Error **errp)
{
CPUState *cs;
CPU_FOREACH(cs) {
cpu_interrupt(cs, CPU_INTERRUPT_NMI);
}
}
static void machine_hppa_machine_init(MachineClass *mc)
{
@@ -371,4 +380,28 @@ static void machine_hppa_machine_init(MachineClass *mc)
mc->default_ram_id = "ram";
}
DEFINE_MACHINE("hppa", machine_hppa_machine_init)
static void machine_hppa_machine_init_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
machine_hppa_machine_init(mc);
NMIClass *nc = NMI_CLASS(oc);
nc->nmi_monitor_handler = hppa_nmi;
}
static const TypeInfo machine_hppa_machine_init_typeinfo = {
.name = ("hppa" "-machine"),
.parent = "machine",
.class_init = machine_hppa_machine_init_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_NMI },
{ }
},
};
static void machine_hppa_machine_init_register_types(void)
{
type_register_static(&machine_hppa_machine_init_typeinfo);
}
type_init(machine_hppa_machine_init_register_types)
pc-bios/hppa-firmware.img
BIN
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Binary file not shown.
roms/seabios-hppa
+1 -1
Submodule roms/seabios-hppa updated: b12acac4be...bf3404006f
target/hppa/cpu.c
+1 -1
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@@ -62,7 +62,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
static bool hppa_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & CPU_INTERRUPT_HARD;
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
target/hppa/cpu.h
+5
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@@ -69,6 +69,11 @@
#define EXCP_SYSCALL 30
#define EXCP_SYSCALL_LWS 31
/* Emulated hardware TOC button */
#define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */
/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
#define PSW_I 0x00000001
#define PSW_D 0x00000002
target/hppa/helper.h
+1
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@@ -80,6 +80,7 @@ DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(halt, noreturn, env)
DEF_HELPER_1(reset, noreturn, env)
DEF_HELPER_1(getshadowregs, void, env)
DEF_HELPER_1(rfi, void, env)
DEF_HELPER_1(rfi_r, void, env)
DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr)
target/hppa/insns.decode
+1
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@@ -111,6 +111,7 @@ rfi_r 000000 ----- ----- --- 01100101 00000
# They are allocated from the unassigned instruction space.
halt 1111 1111 1111 1101 1110 1010 1101 0000
reset 1111 1111 1111 1101 1110 1010 1101 0001
getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010
####
# Memory Management
target/hppa/int_helper.c
+18 -1
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@@ -23,6 +23,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "hw/core/cpu.h"
#include "hw/hppa/hppa_hardware.h"
#ifndef CONFIG_USER_ONLY
static void eval_interrupt(HPPACPU *cpu)
@@ -181,7 +182,14 @@ void hppa_cpu_do_interrupt(CPUState *cs)
}
/* step 7 */
env->iaoq_f = env->cr[CR_IVA] + 32 * i;
if (i == EXCP_TOC) {
env->iaoq_f = FIRMWARE_START;
/* help SeaBIOS and provide iaoq_b and iasq_back in shadow regs */
env->gr[24] = env->cr_back[0];
env->gr[25] = env->cr_back[1];
} else {
env->iaoq_f = env->cr[CR_IVA] + 32 * i;
}
env->iaoq_b = env->iaoq_f + 4;
env->iasq_f = 0;
env->iasq_b = 0;
@@ -219,6 +227,7 @@ void hppa_cpu_do_interrupt(CPUState *cs)
[EXCP_PER_INTERRUPT] = "performance monitor interrupt",
[EXCP_SYSCALL] = "syscall",
[EXCP_SYSCALL_LWS] = "syscall-lws",
[EXCP_TOC] = "TOC (transfer of control)",
};
static int count;
const char *name = NULL;
@@ -248,6 +257,14 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
if (interrupt_request & CPU_INTERRUPT_NMI) {
/* Raise TOC (NMI) interrupt */
cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI);
cs->exception_index = EXCP_TOC;
hppa_cpu_do_interrupt(cs);
return true;
}
/* If interrupts are requested and enabled, raise them. */
if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) {
cs->exception_index = EXCP_EXT_INTERRUPT;
target/hppa/op_helper.c
+6 -1
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@@ -694,7 +694,7 @@ void HELPER(rfi)(CPUHPPAState *env)
cpu_hppa_put_psw(env, env->cr[CR_IPSW]);
}
void HELPER(rfi_r)(CPUHPPAState *env)
void HELPER(getshadowregs)(CPUHPPAState *env)
{
env->gr[1] = env->shadow[0];
env->gr[8] = env->shadow[1];
@@ -703,6 +703,11 @@ void HELPER(rfi_r)(CPUHPPAState *env)
env->gr[17] = env->shadow[4];
env->gr[24] = env->shadow[5];
env->gr[25] = env->shadow[6];
}
void HELPER(rfi_r)(CPUHPPAState *env)
{
helper_getshadowregs(env);
helper_rfi(env);
}
#endif
target/hppa/translate.c
+10
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@@ -2393,6 +2393,16 @@ static bool trans_reset(DisasContext *ctx, arg_reset *a)
#endif
}
static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
nullify_over(ctx);
gen_helper_getshadowregs(cpu_env);
return nullify_end(ctx);
#endif
}
static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a)
{
if (a->m) {