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Merge remote-tracking branch 'qemu-kvm/memory/batch' into staging

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This commit is contained in:
Anthony Liguori
2011-08-25 07:48:24 -05:00
parent 444dc48298 2b90ca040c
commit 8ef9ea85a2
49 changed files with 637 additions and 657 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Makefile.hw
+1
View File
@@ -10,6 +10,7 @@ include $(SRC_PATH)/rules.mak
$(call set-vpath, $(SRC_PATH):$(SRC_PATH)/hw)
QEMU_CFLAGS+=-I..
QEMU_CFLAGS += $(GLIB_CFLAGS)
include $(SRC_PATH)/Makefile.objs
Makefile.target
-1
View File
@@ -195,7 +195,6 @@ obj-$(CONFIG_VIRTIO) += virtio.o virtio-blk.o virtio-balloon.o virtio-net.o virt
obj-y += vhost_net.o
obj-$(CONFIG_VHOST_NET) += vhost.o
obj-$(CONFIG_REALLY_VIRTFS) += 9pfs/virtio-9p-device.o
obj-y += rwhandler.o
obj-$(CONFIG_KVM) += kvm.o kvm-all.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-y += memory.o
hw/an5206.c
+8 -4
View File
@@ -12,6 +12,7 @@
#include "boards.h"
#include "loader.h"
#include "elf.h"
#include "exec-memory.h"
#define KERNEL_LOAD_ADDR 0x10000
#define AN5206_MBAR_ADDR 0x10000000
@@ -37,6 +38,9 @@ static void an5206_init(ram_addr_t ram_size,
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "m5206";
@@ -52,12 +56,12 @@ static void an5206_init(ram_addr_t ram_size,
env->rambar0 = AN5206_RAMBAR_ADDR | 1;
/* DRAM at address zero */
cpu_register_physical_memory(0, ram_size,
qemu_ram_alloc(NULL, "an5206.ram", ram_size) | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "an5206.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0, ram);
/* Internal SRAM. */
cpu_register_physical_memory(AN5206_RAMBAR_ADDR, 512,
qemu_ram_alloc(NULL, "an5206.sram", 512) | IO_MEM_RAM);
memory_region_init_ram(sram, NULL, "an5206.sram", 512);
memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram);
mcf5206_init(AN5206_MBAR_ADDR, env);
hw/arm-misc.h
+4 -1
View File
@@ -11,13 +11,16 @@
#ifndef ARM_MISC_H
#define ARM_MISC_H 1
#include "memory.h"
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(CPUState *env);
/* armv7m.c */
qemu_irq *armv7m_init(int flash_size, int sram_size,
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model);
/* arm_boot.c */
hw/armv7m.c
+12 -10
View File
@@ -156,7 +156,8 @@ static void armv7m_reset(void *opaque)
flash_size and sram_size are in kb.
Returns the NVIC array. */
qemu_irq *armv7m_init(int flash_size, int sram_size,
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model)
{
CPUState *env;
@@ -169,6 +170,9 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
uint64_t lowaddr;
int i;
int big_endian;
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *hack = g_new(MemoryRegion, 1);
flash_size *= 1024;
sram_size *= 1024;
@@ -194,12 +198,11 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
#endif
/* Flash programming is done via the SCU, so pretend it is ROM. */
cpu_register_physical_memory(0, flash_size,
qemu_ram_alloc(NULL, "armv7m.flash",
flash_size) | IO_MEM_ROM);
cpu_register_physical_memory(0x20000000, sram_size,
qemu_ram_alloc(NULL, "armv7m.sram",
sram_size) | IO_MEM_RAM);
memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size);
memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space_mem, 0, flash);
memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size);
memory_region_add_subregion(address_space_mem, 0x20000000, sram);
armv7m_bitband_init();
nvic = qdev_create(NULL, "armv7m_nvic");
@@ -232,9 +235,8 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
/* Hack to map an additional page of ram at the top of the address
space. This stops qemu complaining about executing code outside RAM
when returning from an exception. */
cpu_register_physical_memory(0xfffff000, 0x1000,
qemu_ram_alloc(NULL, "armv7m.hack",
0x1000) | IO_MEM_RAM);
memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000);
memory_region_add_subregion(address_space_mem, 0xfffff000, hack);
qemu_register_reset(armv7m_reset, env);
return pic;
hw/axis_dev88.c
+8 -8
View File
@@ -31,6 +31,7 @@
#include "elf.h"
#include "cris-boot.h"
#include "blockdev.h"
#include "exec-memory.h"
#define D(x)
#define DNAND(x)
@@ -259,8 +260,9 @@ void axisdev88_init (ram_addr_t ram_size,
int i;
int nand_regs;
int gpio_regs;
ram_addr_t phys_ram;
ram_addr_t phys_intmem;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
/* init CPUs */
if (cpu_model == NULL) {
@@ -269,15 +271,13 @@ void axisdev88_init (ram_addr_t ram_size,
env = cpu_init(cpu_model);
/* allocate RAM */
phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size);
cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
internal memory. */
phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE);
cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
phys_intmem | IO_MEM_RAM);
memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
/* Attach a NAND flash to CS1. */
nand = drive_get(IF_MTD, 0, 0);
hw/cirrus_vga.c
+2
View File
@@ -2424,6 +2424,7 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
{
unsigned mode;
memory_region_transaction_begin();
if ((s->vga.sr[0x17] & 0x44) == 0x44) {
goto generic_io;
} else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
@@ -2443,6 +2444,7 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
unmap_linear_vram(s);
}
}
memory_region_transaction_commit();
}
hw/collie.c
+9 -7
View File
@@ -26,7 +26,7 @@ static void collie_init(ram_addr_t ram_size,
{
StrongARMState *s;
DriveInfo *dinfo;
ram_addr_t phys_flash;
MemoryRegion *phys_flash = g_new(MemoryRegion, 2);
if (!cpu_model) {
cpu_model = "sa1110";
@@ -34,17 +34,19 @@ static void collie_init(ram_addr_t ram_size,
s = sa1110_init(collie_binfo.ram_size, cpu_model);
phys_flash = qemu_ram_alloc(NULL, "collie.fl1", 0x02000000);
memory_region_init_rom_device(&phys_flash[0], &pflash_cfi01_ops_le,
NULL, "collie.fl1", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(SA_CS0, phys_flash,
pflash_cfi01_register(SA_CS0, &phys_flash[0],
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
512, 4, 0x00, 0x00, 0x00, 0x00, 0);
512, 4, 0x00, 0x00, 0x00, 0x00);
phys_flash = qemu_ram_alloc(NULL, "collie.fl2", 0x02000000);
memory_region_init_rom_device(&phys_flash[1], &pflash_cfi01_ops_le,
NULL, "collie.fl2", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 1);
pflash_cfi01_register(SA_CS1, phys_flash,
pflash_cfi01_register(SA_CS1, &phys_flash[1],
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
512, 4, 0x00, 0x00, 0x00, 0x00, 0);
512, 4, 0x00, 0x00, 0x00, 0x00);
sysbus_create_simple("scoop", 0x40800000, NULL);
hw/dec_pci.c
+6 -7
View File
@@ -80,16 +80,15 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
static int pci_dec_21154_init_device(SysBusDevice *dev)
{
DECState *s;
int pci_mem_config, pci_mem_data;
s = FROM_SYSBUS(DECState, dev);
pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
pci_mem_data = pci_host_data_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
&s->host_state, "pci-data-idx", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
return 0;
}
hw/dummy_m68k.c
+5 -2
View File
@@ -10,6 +10,7 @@
#include "boards.h"
#include "loader.h"
#include "elf.h"
#include "exec-memory.h"
#define KERNEL_LOAD_ADDR 0x10000
@@ -21,6 +22,8 @@ static void dummy_m68k_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
@@ -37,8 +40,8 @@ static void dummy_m68k_init(ram_addr_t ram_size,
env->vbr = 0;
/* RAM at address zero */
cpu_register_physical_memory(0, ram_size,
qemu_ram_alloc(NULL, "dummy_m68k.ram", ram_size) | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "dummy_m68k.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0, ram);
/* Load kernel. */
if (kernel_filename) {
hw/flash.h
+11 -5
View File
@@ -1,21 +1,27 @@
#include "memory.h"
/* NOR flash devices */
typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
extern const MemoryRegionOps pflash_cfi01_ops_be;
extern const MemoryRegionOps pflash_cfi01_ops_le;
extern const MemoryRegionOps pflash_cfi02_ops_be;
extern const MemoryRegionOps pflash_cfi02_ops_le;
pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be);
uint16_t id2, uint16_t id3);
/* pflash_cfi02.c */
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3,
uint16_t unlock_addr0, uint16_t unlock_addr1,
int be);
uint16_t unlock_addr0, uint16_t unlock_addr1);
/* nand.c */
DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id);
hw/g364fb.c
+33 -27
View File
@@ -36,7 +36,7 @@ do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0)
typedef struct G364State {
/* hardware */
uint8_t *vram;
ram_addr_t vram_offset;
MemoryRegion vram_region;
int vram_size;
qemu_irq irq;
/* registers */
@@ -68,16 +68,17 @@ typedef struct G364State {
#define CTLA_FORCE_BLANK 0x00000400
#define CTLA_NO_CURSOR 0x00800000
static inline int check_dirty(ram_addr_t page)
static inline int check_dirty(G364State *s, ram_addr_t page)
{
return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
return memory_region_get_dirty(&s->vram_region, page, DIRTY_MEMORY_VGA);
}
static inline void reset_dirty(G364State *s,
ram_addr_t page_min, ram_addr_t page_max)
{
cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1,
VGA_DIRTY_FLAG);
memory_region_reset_dirty(&s->vram_region, page_min,
page_max + TARGET_PAGE_SIZE - 1,
DIRTY_MEMORY_VGA);
}
static void g364fb_draw_graphic8(G364State *s)
@@ -114,7 +115,7 @@ static void g364fb_draw_graphic8(G364State *s)
return;
}
page = s->vram_offset;
page = 0;
page_min = (ram_addr_t)-1;
page_max = 0;
@@ -135,7 +136,7 @@ static void g364fb_draw_graphic8(G364State *s)
/* XXX: out of range in vram? */
data_display = dd = ds_get_data(s->ds);
while (y < s->height) {
if (check_dirty(page)) {
if (check_dirty(s, page)) {
if (y < ymin)
ymin = ymax = y;
if (page_min == (ram_addr_t)-1)
@@ -275,7 +276,7 @@ static inline void g364fb_invalidate_display(void *opaque)
s->blanked = 0;
for (i = 0; i < s->vram_size; i += TARGET_PAGE_SIZE) {
cpu_physical_memory_set_dirty(s->vram_offset + i);
memory_region_set_dirty(&s->vram_region, i);
}
}
@@ -411,7 +412,7 @@ static void g364_invalidate_cursor_position(G364State *s)
end = (ymax + 1) * ds_get_linesize(s->ds);
for (i = start; i < end; i += TARGET_PAGE_SIZE) {
cpu_physical_memory_set_dirty(s->vram_offset + i);
memory_region_set_dirty(&s->vram_region, i);
}
}
@@ -522,16 +523,20 @@ static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t v
g364fb_ctrl_writel(opaque, addr & ~0x3, val);
}
static CPUReadMemoryFunc * const g364fb_ctrl_read[3] = {
g364fb_ctrl_readb,
g364fb_ctrl_readw,
g364fb_ctrl_readl,
};
static CPUWriteMemoryFunc * const g364fb_ctrl_write[3] = {
g364fb_ctrl_writeb,
g364fb_ctrl_writew,
g364fb_ctrl_writel,
static const MemoryRegionOps g364fb_ctrl_ops = {
.old_mmio = {
.read = {
g364fb_ctrl_readb,
g364fb_ctrl_readw,
g364fb_ctrl_readl,
},
.write = {
g364fb_ctrl_writeb,
g364fb_ctrl_writew,
g364fb_ctrl_writel,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
@@ -583,18 +588,19 @@ static void g364fb_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->height);
}
int g364fb_mm_init(target_phys_addr_t vram_base,
int g364fb_mm_init(MemoryRegion *system_memory,
target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq)
{
G364State *s;
int io_ctrl;
MemoryRegion *io_ctrl = g_new(MemoryRegion, 1);
s = g_malloc0(sizeof(G364State));
s->vram_size = 8 * 1024 * 1024;
s->vram_offset = qemu_ram_alloc(NULL, "g364fb.vram", s->vram_size);
s->vram = qemu_get_ram_ptr(s->vram_offset);
memory_region_init_ram(&s->vram_region, NULL, "g364fb.vram", s->vram_size);
s->vram = memory_region_get_ram_ptr(&s->vram_region);
s->irq = irq;
qemu_register_reset(g364fb_reset, s);
@@ -605,11 +611,11 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
memory_region_add_subregion(system_memory, vram_base, &s->vram_region);
io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
memory_region_init_io(io_ctrl, &g364fb_ctrl_ops, s,
"g364fb-ctrl", 0x200000);
memory_region_add_subregion(system_memory, ctrl_base, io_ctrl);
return 0;
}
hw/grackle_pci.c
+6 -7
View File
@@ -92,16 +92,15 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
static int pci_grackle_init_device(SysBusDevice *dev)
{
GrackleState *s;
int pci_mem_config, pci_mem_data;
s = FROM_SYSBUS(GrackleState, dev);
pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
pci_mem_data = pci_host_data_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
&s->host_state, "pci-data-idx", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
qemu_register_reset(pci_grackle_reset, &s->host_state);
return 0;
hw/gumstix.c
+16 -12
View File
@@ -48,7 +48,8 @@ static void connex_init(ram_addr_t ram_size,
{
PXA2xxState *cpu;
DriveInfo *dinfo;
int be;
const MemoryRegionOps *flash_ops;
MemoryRegion *flash = g_new(MemoryRegion, 1);
uint32_t connex_rom = 0x01000000;
uint32_t connex_ram = 0x04000000;
@@ -63,14 +64,15 @@ static void connex_init(ram_addr_t ram_size,
}
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
flash_ops = &pflash_cfi01_ops_be;
#else
be = 0;
flash_ops = &pflash_cfi01_ops_le;
#endif
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "connext.rom",
connex_rom),
memory_region_init_rom_device(flash, flash_ops,
NULL, "connext.rom", connex_rom);
if (!pflash_cfi01_register(0x00000000, flash,
dinfo->bdrv, sector_len, connex_rom / sector_len,
2, 0, 0, 0, 0, be)) {
2, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
@@ -87,7 +89,8 @@ static void verdex_init(ram_addr_t ram_size,
{
PXA2xxState *cpu;
DriveInfo *dinfo;
int be;
MemoryRegion *flash = g_new(MemoryRegion, 1);
const MemoryRegionOps *flash_ops;
uint32_t verdex_rom = 0x02000000;
uint32_t verdex_ram = 0x10000000;
@@ -102,14 +105,15 @@ static void verdex_init(ram_addr_t ram_size,
}
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
flash_ops = &pflash_cfi01_ops_be;
#else
be = 0;
flash_ops = &pflash_cfi01_ops_le;
#endif
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "verdex.rom",
verdex_rom),
memory_region_init_rom_device(flash, flash_ops,
NULL, "verdex.rom", verdex_rom);
if (!pflash_cfi01_register(0x00000000, flash,
dinfo->bdrv, sector_len, verdex_rom / sector_len,
2, 0, 0, 0, 0, be)) {
2, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
hw/integratorcp.c
+20 -8
View File
@@ -13,11 +13,13 @@
#include "boards.h"
#include "arm-misc.h"
#include "net.h"
#include "exec-memory.h"
typedef struct {
SysBusDevice busdev;
uint32_t memsz;
uint32_t flash_offset;
MemoryRegion flash;
bool flash_mapped;
uint32_t cm_osc;
uint32_t cm_ctrl;
uint32_t cm_lock;
@@ -108,9 +110,15 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
static void integratorcm_do_remap(integratorcm_state *s, int flash)
{
if (flash) {
cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
if (s->flash_mapped) {
sysbus_del_memory(&s->busdev, &s->flash);
s->flash_mapped = false;
}
} else {
cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
if (!s->flash_mapped) {
sysbus_add_memory_overlap(&s->busdev, 0, &s->flash, 1);
s->flash_mapped = true;
}
}
//??? tlb_flush (cpu_single_env, 1);
}
@@ -252,7 +260,8 @@ static int integratorcm_init(SysBusDevice *dev)
}
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
s->cm_init = 0x00000112;
s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000);
s->flash_mapped = false;
iomemtype = cpu_register_io_memory(integratorcm_readfn,
integratorcm_writefn, s,
@@ -456,7 +465,9 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
ram_addr_t ram_offset;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32];
qemu_irq *cpu_pic;
DeviceState *dev;
@@ -469,13 +480,14 @@ static void integratorcp_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
ram_offset = qemu_ram_alloc(NULL, "integrator.ram", ram_size);
memory_region_init_ram(ram, NULL, "integrator.ram", ram_size);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
memory_region_add_subregion(address_space_mem, 0, ram);
/* And again at address 0x80000000 */
cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, "integrator_core");
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
hw/leon3.c
+9 -6
View File
@@ -29,6 +29,7 @@
#include "loader.h"
#include "elf.h"
#include "trace.h"
#include "exec-memory.h"
#include "grlib.h"
@@ -100,7 +101,9 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
const char *cpu_model)
{
CPUState *env;
ram_addr_t ram_offset, prom_offset;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *prom = g_new(MemoryRegion, 1);
int ret;
char *filename;
qemu_irq *cpu_irqs = NULL;
@@ -139,14 +142,14 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
exit(1);
}
ram_offset = qemu_ram_alloc(NULL, "leon3.ram", ram_size);
cpu_register_physical_memory(0x40000000, ram_size, ram_offset | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "leon3.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Allocate BIOS */
prom_size = 8 * 1024 * 1024; /* 8Mb */
prom_offset = qemu_ram_alloc(NULL, "Leon3.bios", prom_size);
cpu_register_physical_memory(0x00000000, prom_size,
prom_offset | IO_MEM_ROM);
memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size);
memory_region_set_readonly(prom, true);
memory_region_add_subregion(address_space_mem, 0x00000000, prom);
/* Load boot prom */
if (bios_name == NULL) {
hw/lm32_boards.c
+17 -12
View File
@@ -28,6 +28,7 @@
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
#include "exec-memory.h"
typedef struct {
CPUState *env;
@@ -76,8 +77,9 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
{
CPUState *env;
DriveInfo *dinfo;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
ResetInfo *reset_info;
int i;
@@ -105,16 +107,17 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
reset_info->flash_base = flash_base;
phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_ram(phys_ram, NULL, "lm32_evr.sdram", ram_size);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size);
memory_region_init_rom_device(phys_flash, &pflash_cfi02_ops_be,
NULL, "lm32_evr.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2,
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa);
/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
@@ -164,8 +167,9 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
{
CPUState *env;
DriveInfo *dinfo;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
HWSetup *hw;
ResetInfo *reset_info;
@@ -200,16 +204,17 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
reset_info->flash_base = flash_base;
phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_ram(phys_ram, NULL, "lm32_uclinux.sdram", ram_size);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size);
memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
NULL, "lm32_uclinux.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2,
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa);
/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
hw/mainstone.c
+19 -14
View File
@@ -17,6 +17,7 @@
#include "flash.h"
#include "blockdev.h"
#include "sysbus.h"
#include "exec-memory.h"
/* Device addresses */
#define MST_FPGA_PHYS 0x08000000
@@ -90,7 +91,8 @@ static struct arm_boot_info mainstone_binfo = {
.ram_size = 0x04000000,
};
static void mainstone_common_init(ram_addr_t ram_size,
static void mainstone_common_init(MemoryRegion *address_space_mem,
ram_addr_t ram_size,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
@@ -101,21 +103,23 @@ static void mainstone_common_init(ram_addr_t ram_size,
DeviceState *mst_irq;
DriveInfo *dinfo;
int i;
int be;
MemoryRegion *rom = g_new(MemoryRegion, 1);
MemoryRegion *flashes = g_new(MemoryRegion, 2);
const MemoryRegionOps *flash_ops;
if (!cpu_model)
cpu_model = "pxa270-c5";
/* Setup CPU & memory */
cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
cpu_register_physical_memory(0, MAINSTONE_ROM,
qemu_ram_alloc(NULL, "mainstone.rom",
MAINSTONE_ROM) | IO_MEM_ROM);
memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
flash_ops = &pflash_cfi01_ops_be;
#else
be = 0;
flash_ops = &pflash_cfi01_ops_le;
#endif
/* There are two 32MiB flash devices on the board */
for (i = 0; i < 2; i ++) {
@@ -126,13 +130,14 @@ static void mainstone_common_init(ram_addr_t ram_size,
exit(1);
}
memory_region_init_rom_device(&flashes[i], flash_ops,
NULL, (i ? "mainstone.flash1"
: "mainstone.flash0"),
MAINSTONE_FLASH);
if (!pflash_cfi01_register(mainstone_flash_base[i],
qemu_ram_alloc(NULL, i ? "mainstone.flash1" :
"mainstone.flash0",
MAINSTONE_FLASH),
dinfo->bdrv, sector_len,
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
be)) {
&flashes[i], dinfo->bdrv, sector_len,
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0,
0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
@@ -170,7 +175,7 @@ static void mainstone_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
mainstone_common_init(ram_size, kernel_filename,
mainstone_common_init(get_system_memory(), ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
}
hw/mcf5208.c
+32 -40
View File
@@ -13,6 +13,7 @@
#include "boards.h"
#include "loader.h"
#include "elf.h"
#include "exec-memory.h"
#define SYS_FREQ 66000000
@@ -27,6 +28,7 @@
#define PCSR_PRE_MASK 0x0f00
typedef struct {
MemoryRegion iomem;
qemu_irq irq;
ptimer_state *timer;
uint16_t pcsr;
@@ -43,7 +45,7 @@ static void m5208_timer_update(m5208_timer_state *s)
}
static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
int prescale;
@@ -104,7 +106,8 @@ static void m5208_timer_trigger(void *opaque)
m5208_timer_update(s);
}
static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
switch (addr) {
@@ -120,19 +123,14 @@ static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
}
}
static CPUReadMemoryFunc * const m5208_timer_readfn[] = {
m5208_timer_read,
m5208_timer_read,
m5208_timer_read
static const MemoryRegionOps m5208_timer_ops = {
.read = m5208_timer_read,
.write = m5208_timer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
m5208_timer_write,
m5208_timer_write,
m5208_timer_write
};
static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
switch (addr) {
case 0x110: /* SDCS0 */
@@ -154,45 +152,36 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
}
static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
}
static CPUReadMemoryFunc * const m5208_sys_readfn[] = {
m5208_sys_read,
m5208_sys_read,
m5208_sys_read
static const MemoryRegionOps m5208_sys_ops = {
.read = m5208_sys_read,
.write = m5208_sys_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const m5208_sys_writefn[] = {
m5208_sys_write,
m5208_sys_write,
m5208_sys_write
};
static void mcf5208_sys_init(qemu_irq *pic)
static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
{
int iomemtype;
MemoryRegion *iomem = g_new(MemoryRegion, 1);
m5208_timer_state *s;
QEMUBH *bh;
int i;
iomemtype = cpu_register_io_memory(m5208_sys_readfn,
m5208_sys_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
/* SDRAMC. */
cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
memory_region_init_io(iomem, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
/* Timers. */
for (i = 0; i < 2; i++) {
s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
bh = qemu_bh_new(m5208_timer_trigger, s);
s->timer = ptimer_init(bh);
iomemtype = cpu_register_io_memory(m5208_timer_readfn,
m5208_timer_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
iomemtype);
memory_region_init_io(&s->iomem, &m5208_timer_ops, s,
"m5208-timer", 0x00004000);
memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
&s->iomem);
s->irq = pic[4 + i];
}
}
@@ -207,6 +196,9 @@ static void mcf5208evb_init(ram_addr_t ram_size,
uint64_t elf_entry;
target_phys_addr_t entry;
qemu_irq *pic;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "m5208";
@@ -221,12 +213,12 @@ static void mcf5208evb_init(ram_addr_t ram_size,
/* TODO: Configure BARs. */
/* DRAM at 0x40000000 */
cpu_register_physical_memory(0x40000000, ram_size,
qemu_ram_alloc(NULL, "mcf5208.ram", ram_size) | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "mcf5208.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Internal SRAM. */
cpu_register_physical_memory(0x80000000, 16384,
qemu_ram_alloc(NULL, "mcf5208.sram", 16384) | IO_MEM_RAM);
memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384);
memory_region_add_subregion(address_space_mem, 0x80000000, sram);
/* Internal peripherals. */
pic = mcf_intc_init(0xfc048000, env);
@@ -235,7 +227,7 @@ static void mcf5208evb_init(ram_addr_t ram_size,
mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
mcf5208_sys_init(pic);
mcf5208_sys_init(address_space_mem, pic);
if (nb_nics > 1) {
fprintf(stderr, "Too many NICs\n");
hw/milkymist-minimac2.c
+21 -22
View File
@@ -97,6 +97,8 @@ struct MilkymistMinimac2State {
NICConf conf;
char *phy_model;
target_phys_addr_t buffers_base;
MemoryRegion buffers;
MemoryRegion regs_region;
qemu_irq rx_irq;
qemu_irq tx_irq;
@@ -320,8 +322,8 @@ static ssize_t minimac2_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
return size;
}
static uint32_t
minimac2_read(void *opaque, target_phys_addr_t addr)
static uint64_t
minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
MilkymistMinimac2State *s = opaque;
uint32_t r = 0;
@@ -350,7 +352,8 @@ minimac2_read(void *opaque, target_phys_addr_t addr)
}
static void
minimac2_write(void *opaque, target_phys_addr_t addr, uint32_t value)
minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{
MilkymistMinimac2State *s = opaque;
@@ -395,16 +398,14 @@ minimac2_write(void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
static CPUReadMemoryFunc * const minimac2_read_fn[] = {
NULL,
NULL,
&minimac2_read,
};
static CPUWriteMemoryFunc * const minimac2_write_fn[] = {
NULL,
NULL,
&minimac2_write,
static const MemoryRegionOps minimac2_ops = {
.read = minimac2_read,
.write = minimac2_write,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int minimac2_can_rx(VLANClientState *nc)
@@ -457,25 +458,23 @@ static NetClientInfo net_milkymist_minimac2_info = {
static int milkymist_minimac2_init(SysBusDevice *dev)
{
MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev);
int regs;
ram_addr_t buffers;
size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
sysbus_init_irq(dev, &s->rx_irq);
sysbus_init_irq(dev, &s->tx_irq);
regs = cpu_register_io_memory(minimac2_read_fn, minimac2_write_fn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, regs);
memory_region_init_io(&s->regs_region, &minimac2_ops, s,
"minimac2-mmio", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
/* register buffers memory */
buffers = qemu_ram_alloc(NULL, "milkymist_minimac2.buffers", buffers_size);
s->rx0_buf = qemu_get_ram_ptr(buffers);
memory_region_init_ram(&s->buffers, NULL, "milkymist_minimac2.buffers",
buffers_size);
s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
cpu_register_physical_memory(s->buffers_base, buffers_size,
buffers | IO_MEM_RAM);
sysbus_add_memory(dev, s->buffers_base, &s->buffers);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,

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