izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity

Change MMIO callbacks to use offsets, not absolute addresses.

Browse Source 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5849 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook
2008-12-01 18:59:50 +00:00
parent 6ad1d22b15
commit 8da3ff1809
82 changed files with 453 additions and 869 deletions
Download Patch File Download Diff File Expand all files Collapse all files
cpu-all.h
+11 -3
View File
@@ -877,9 +877,17 @@ extern ram_addr_t ram_size;
typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
void cpu_register_physical_memory(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset);
void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset,
ram_addr_t region_offset);
static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset)
{
cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
}
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(ram_addr_t);
void qemu_ram_free(ram_addr_t addr);
exec.c
+62 -20
View File
@@ -146,6 +146,7 @@ typedef struct PageDesc {
typedef struct PhysPageDesc {
/* offset in host memory of the page + io_index in the low bits */
ram_addr_t phys_offset;
ram_addr_t region_offset;
} PhysPageDesc;
#define L2_BITS 10
@@ -199,6 +200,7 @@ typedef struct subpage_t {
CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
void *opaque[TARGET_PAGE_SIZE][2][4];
ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4];
} subpage_t;
#ifdef _WIN32
@@ -1969,7 +1971,13 @@ int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
and avoid full address decoding in every device.
We can't use the high bits of pd for this because
IO_MEM_ROMD uses these as a ram address. */
iotlb = (pd & ~TARGET_PAGE_MASK) + paddr;
iotlb = (pd & ~TARGET_PAGE_MASK);
if (p) {
/* FIXME: What if this isn't page aligned? */
iotlb += p->region_offset;
} else {
iotlb += paddr;
}
}
code_address = address;
@@ -2209,10 +2217,11 @@ static inline void tlb_set_dirty(CPUState *env,
#endif /* defined(CONFIG_USER_ONLY) */
#if !defined(CONFIG_USER_ONLY)
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
ram_addr_t memory);
ram_addr_t memory, ram_addr_t region_offset);
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
ram_addr_t orig_memory);
ram_addr_t orig_memory, ram_addr_t region_offset);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
need_subpage) \
do { \
@@ -2235,10 +2244,15 @@ static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
/* register physical memory. 'size' must be a multiple of the target
page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
io memory page */
void cpu_register_physical_memory(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset)
io memory page. The address used when calling the IO function is
the offset from the start of the region, plus region_offset. Both
start_region and regon_offset are rounded down to a page boundary
before calculating this offset. This should not be a problem unless
the low bits of start_addr and region_offset differ. */
void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset,
ram_addr_t region_offset)
{
target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
@@ -2256,6 +2270,7 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
if (kvm_enabled())
kvm_set_phys_mem(start_addr, size, phys_offset);
region_offset &= TARGET_PAGE_MASK;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
end_addr = start_addr + (target_phys_addr_t)size;
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
@@ -2270,12 +2285,15 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
if (!(orig_memory & IO_MEM_SUBPAGE)) {
subpage = subpage_init((addr & TARGET_PAGE_MASK),
&p->phys_offset, orig_memory);
&p->phys_offset, orig_memory,
p->region_offset);
} else {
subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
>> IO_MEM_SHIFT];
}
subpage_register(subpage, start_addr2, end_addr2, phys_offset);
subpage_register(subpage, start_addr2, end_addr2, phys_offset,
region_offset);
p->region_offset = 0;
} else {
p->phys_offset = phys_offset;
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
@@ -2285,10 +2303,11 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
} else {
p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
p->phys_offset = phys_offset;
p->region_offset = region_offset;
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
(phys_offset & IO_MEM_ROMD))
(phys_offset & IO_MEM_ROMD)) {
phys_offset += TARGET_PAGE_SIZE;
else {
}else {
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
@@ -2297,12 +2316,15 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
subpage = subpage_init((addr & TARGET_PAGE_MASK),
&p->phys_offset, IO_MEM_UNASSIGNED);
&p->phys_offset, IO_MEM_UNASSIGNED,
0);
subpage_register(subpage, start_addr2, end_addr2,
phys_offset);
phys_offset, region_offset);
p->region_offset = 0;
}
}
}
region_offset += TARGET_PAGE_SIZE;
}
/* since each CPU stores ram addresses in its TLB cache, we must
@@ -2609,12 +2631,13 @@ static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr
uint32_t ret;
unsigned int idx;
idx = SUBPAGE_IDX(addr - mmio->base);
idx = SUBPAGE_IDX(addr);
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
mmio, len, addr, idx);
#endif
ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr);
ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len],
addr + mmio->region_offset[idx][0][len]);
return ret;
}
@@ -2624,12 +2647,14 @@ static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
{
unsigned int idx;
idx = SUBPAGE_IDX(addr - mmio->base);
idx = SUBPAGE_IDX(addr);
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
mmio, len, addr, idx, value);
#endif
(**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value);
(**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len],
addr + mmio->region_offset[idx][1][len],
value);
}
static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
@@ -2699,7 +2724,7 @@ static CPUWriteMemoryFunc *subpage_write[] = {
};
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
ram_addr_t memory)
ram_addr_t memory, ram_addr_t region_offset)
{
int idx, eidx;
unsigned int i;
@@ -2718,10 +2743,12 @@ static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
if (io_mem_read[memory][i]) {
mmio->mem_read[idx][i] = &io_mem_read[memory][i];
mmio->opaque[idx][0][i] = io_mem_opaque[memory];
mmio->region_offset[idx][0][i] = region_offset;
}
if (io_mem_write[memory][i]) {
mmio->mem_write[idx][i] = &io_mem_write[memory][i];
mmio->opaque[idx][1][i] = io_mem_opaque[memory];
mmio->region_offset[idx][1][i] = region_offset;
}
}
}
@@ -2730,7 +2757,7 @@ static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
}
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
ram_addr_t orig_memory)
ram_addr_t orig_memory, ram_addr_t region_offset)
{
subpage_t *mmio;
int subpage_memory;
@@ -2744,7 +2771,8 @@ static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
#endif
*phys = subpage_memory | IO_MEM_SUBPAGE;
subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory);
subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory,
region_offset);
}
return mmio;
@@ -2878,6 +2906,8 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
if (is_write) {
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
/* XXX: could force cpu_single_env to NULL to avoid
potential bugs */
if (l >= 4 && ((addr & 3) == 0)) {
@@ -2915,6 +2945,8 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
!(pd & IO_MEM_ROMD)) {
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
if (l >= 4 && ((addr & 3) == 0)) {
/* 32 bit read access */
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
@@ -3004,6 +3036,8 @@ uint32_t ldl_phys(target_phys_addr_t addr)
!(pd & IO_MEM_ROMD)) {
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
} else {
/* RAM case */
@@ -3034,6 +3068,8 @@ uint64_t ldq_phys(target_phys_addr_t addr)
!(pd & IO_MEM_ROMD)) {
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
#ifdef TARGET_WORDS_BIGENDIAN
val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
@@ -3085,6 +3121,8 @@ void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
} else {
unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
@@ -3119,6 +3157,8 @@ void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
#ifdef TARGET_WORDS_BIGENDIAN
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
@@ -3150,6 +3190,8 @@ void stl_phys(target_phys_addr_t addr, uint32_t val)
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
} else {
unsigned long addr1;
hw/arm_gic.c
+5 -11
View File
@@ -23,14 +23,12 @@ do { printf("arm_gic: " fmt , ##args); } while (0)
#ifdef NVIC
static const uint8_t gic_id[] =
{ 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
#define GIC_DIST_OFFSET 0
/* The NVIC has 16 internal vectors. However these are not exposed
through the normal GIC interface. */
#define GIC_BASE_IRQ 32
#else
static const uint8_t gic_id[] =
{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
#define GIC_DIST_OFFSET 0x1000
#define GIC_BASE_IRQ 0
#endif
@@ -76,7 +74,6 @@ typedef struct gic_irq_state
typedef struct gic_state
{
uint32_t base;
qemu_irq parent_irq[NCPU];
int enabled;
int cpu_enabled[NCPU];
@@ -252,7 +249,6 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
cpu = gic_get_current_cpu();
cm = 1 << cpu;
offset -= s->base + GIC_DIST_OFFSET;
if (offset < 0x100) {
#ifndef NVIC
if (offset == 0)
@@ -365,7 +361,7 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
#ifdef NVIC
gic_state *s = (gic_state *)opaque;
uint32_t addr;
addr = offset - s->base;
addr = offset;
if (addr < 0x100 || addr > 0xd00)
return nvic_readl(s->nvic, addr);
#endif
@@ -383,7 +379,6 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
int cpu;
cpu = gic_get_current_cpu();
offset -= s->base + GIC_DIST_OFFSET;
if (offset < 0x100) {
#ifdef NVIC
goto bad_reg;
@@ -526,13 +521,13 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
gic_state *s = (gic_state *)opaque;
#ifdef NVIC
uint32_t addr;
addr = offset - s->base;
addr = offset;
if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
nvic_writel(s->nvic, addr, value);
return;
}
#endif
if (offset - s->base == GIC_DIST_OFFSET + 0xf00) {
if (offset == 0xf00) {
int cpu;
int irq;
int mask;
@@ -723,7 +718,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
static gic_state *gic_init(uint32_t base, qemu_irq *parent_irq)
static gic_state *gic_init(uint32_t dist_base, qemu_irq *parent_irq)
{
gic_state *s;
int iomemtype;
@@ -738,9 +733,8 @@ static gic_state *gic_init(uint32_t base, qemu_irq *parent_irq)
}
iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
gic_dist_writefn, s);
cpu_register_physical_memory(base + GIC_DIST_OFFSET, 0x00001000,
cpu_register_physical_memory(dist_base, 0x00001000,
iomemtype);
s->base = base;
gic_reset(s);
register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);
return s;
hw/arm_sysctl.c
-4
View File
@@ -14,7 +14,6 @@
#define LOCK_VALUE 0xa05f
typedef struct {
uint32_t base;
uint32_t sys_id;
uint32_t leds;
uint16_t lockval;
@@ -29,7 +28,6 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
offset -= s->base;
switch (offset) {
case 0x00: /* ID */
return s->sys_id;
@@ -108,7 +106,6 @@ static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
uint32_t val)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
offset -= s->base;
switch (offset) {
case 0x08: /* LED */
@@ -199,7 +196,6 @@ void arm_sysctl_init(uint32_t base, uint32_t sys_id)
s = (arm_sysctl_state *)qemu_mallocz(sizeof(arm_sysctl_state));
if (!s)
return;
s->base = base;
s->sys_id = sys_id;
/* The MPcore bootloader uses these flags to start secondary CPUs.
We don't use a bootloader, so do this here. */
hw/arm_timer.c
-8
View File
@@ -190,7 +190,6 @@ static void *arm_timer_init(uint32_t freq, qemu_irq irq)
typedef struct {
void *timer[2];
int level[2];
uint32_t base;
qemu_irq irq;
} sp804_state;
@@ -208,7 +207,6 @@ static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
sp804_state *s = (sp804_state *)opaque;
/* ??? Don't know the PrimeCell ID for this device. */
offset -= s->base;
if (offset < 0x20) {
return arm_timer_read(s->timer[0], offset);
} else {
@@ -221,7 +219,6 @@ static void sp804_write(void *opaque, target_phys_addr_t offset,
{
sp804_state *s = (sp804_state *)opaque;
offset -= s->base;
if (offset < 0x20) {
arm_timer_write(s->timer[0], offset, value);
} else {
@@ -268,7 +265,6 @@ void sp804_init(uint32_t base, qemu_irq irq)
s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
s->base = base;
s->irq = irq;
/* ??? The timers are actually configurable between 32kHz and 1MHz, but
we don't implement that. */
@@ -285,7 +281,6 @@ void sp804_init(uint32_t base, qemu_irq irq)
typedef struct {
void *timer[3];
uint32_t base;
} icp_pit_state;
static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
@@ -294,7 +289,6 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
int n;
/* ??? Don't know the PrimeCell ID for this device. */
offset -= s->base;
n = offset >> 8;
if (n > 3)
cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
@@ -308,7 +302,6 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset,
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
offset -= s->base;
n = offset >> 8;
if (n > 3)
cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
@@ -335,7 +328,6 @@ void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
icp_pit_state *s;
s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
s->base = base;
/* Timer 0 runs at the system clock speed (40MHz). */
s->timer[0] = arm_timer_init(40000000, pic[irq]);
/* The other two timers run at 1MHz. */
hw/armv7m.c
+13 -9
View File
@@ -14,11 +14,11 @@
/* Bitbanded IO. Each word corresponds to a single bit. */
/* Get the byte address of the real memory for a bitband acess. */
static inline uint32_t bitband_addr(uint32_t addr)
static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
{
uint32_t res;
res = addr & 0xe0000000;
res = *(uint32_t *)opaque;
res |= (addr & 0x1ffffff) >> 5;
return res;
@@ -27,7 +27,7 @@ static inline uint32_t bitband_addr(uint32_t addr)
static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(offset), &v, 1);
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
@@ -37,7 +37,7 @@ static void bitband_writeb(void *opaque, target_phys_addr_t offset,
uint32_t addr;
uint8_t mask;
uint8_t v;
addr = bitband_addr(offset);
addr = bitband_addr(opaque, offset);
mask = (1 << ((offset >> 2) & 7));
cpu_physical_memory_read(addr, &v, 1);
if (value & 1)
@@ -52,7 +52,7 @@ static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
uint32_t addr;
uint16_t mask;
uint16_t v;
addr = bitband_addr(offset) & ~1;
addr = bitband_addr(opaque, offset) & ~1;
mask = (1 << ((offset >> 2) & 15));
mask = tswap16(mask);
cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
@@ -65,7 +65,7 @@ static void bitband_writew(void *opaque, target_phys_addr_t offset,
uint32_t addr;
uint16_t mask;
uint16_t v;
addr = bitband_addr(offset) & ~1;
addr = bitband_addr(opaque, offset) & ~1;
mask = (1 << ((offset >> 2) & 15));
mask = tswap16(mask);
cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
@@ -81,7 +81,7 @@ static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
uint32_t addr;
uint32_t mask;
uint32_t v;
addr = bitband_addr(offset) & ~3;
addr = bitband_addr(opaque, offset) & ~3;
mask = (1 << ((offset >> 2) & 31));
mask = tswap32(mask);
cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
@@ -94,7 +94,7 @@ static void bitband_writel(void *opaque, target_phys_addr_t offset,
uint32_t addr;
uint32_t mask;
uint32_t v;
addr = bitband_addr(offset) & ~3;
addr = bitband_addr(opaque, offset) & ~3;
mask = (1 << ((offset >> 2) & 31));
mask = tswap32(mask);
cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
@@ -120,10 +120,14 @@ static CPUWriteMemoryFunc *bitband_writefn[] = {
static void armv7m_bitband_init(void)
{
int iomemtype;
static uint32_t bitband1_offset = 0x20000000;
static uint32_t bitband2_offset = 0x40000000;
iomemtype = cpu_register_io_memory(0, bitband_readfn, bitband_writefn,
NULL);
&bitband1_offset);
cpu_register_physical_memory(0x22000000, 0x02000000, iomemtype);
iomemtype = cpu_register_io_memory(0, bitband_readfn, bitband_writefn,
&bitband2_offset);
cpu_register_physical_memory(0x42000000, 0x02000000, iomemtype);
}
hw/ds1225y.c
+4 -13
View File
@@ -30,7 +30,6 @@
typedef struct ds1225y_t
{
target_phys_addr_t mem_base;
uint32_t chip_size;
QEMUFile *file;
uint8_t *contents;
@@ -41,14 +40,9 @@ typedef struct ds1225y_t
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
ds1225y_t *s = opaque;
int64_t pos;
uint32_t val;
pos = addr - s->mem_base;
if (pos >= s->chip_size)
pos -= s->chip_size;
val = s->contents[pos];
val = s->contents[addr];
#ifdef DEBUG_NVRAM
printf("nvram: read 0x%x at " TARGET_FMT_lx "\n", val, addr);
@@ -77,16 +71,14 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
{
ds1225y_t *s = opaque;
int64_t pos;
#ifdef DEBUG_NVRAM
printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr);
#endif
pos = addr - s->mem_base;
s->contents[pos] = val & 0xff;
s->contents[addr] = val & 0xff;
if (s->file) {
qemu_fseek(s->file, pos, SEEK_SET);
qemu_fseek(s->file, addr, SEEK_SET);
qemu_put_byte(s->file, (int)val);
qemu_fflush(s->file);
}
@@ -117,7 +109,7 @@ static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint3
return;
}
nvram_writeb(opaque, addr - s->chip_size, val);
nvram_writeb(opaque, addr, val);
}
static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
@@ -167,7 +159,6 @@ void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
if (!s->contents) {
return NULL;
}
s->mem_base = mem_base;
s->protection = 7;
/* Read current file */
hw/e1000.c
+4 -6
View File
@@ -76,7 +76,6 @@ typedef struct E1000State_st {
PCIDevice dev;
VLANClientState *vc;
NICInfo *nd;
uint32_t mmio_base;
int mmio_index;
uint32_t mac_reg[0x8000];
@@ -786,7 +785,7 @@ static void
e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
E1000State *s = opaque;
unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
unsigned int index = (addr & 0x1ffff) >> 2;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
@@ -820,7 +819,7 @@ static uint32_t
e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
{
E1000State *s = opaque;
unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
unsigned int index = (addr & 0x1ffff) >> 2;
if (index < NREADOPS && macreg_readops[index])
{
@@ -870,7 +869,7 @@ nic_save(QEMUFile *f, void *opaque)
int i, j;
pci_device_save(&s->dev, f);
qemu_put_be32s(f, &s->mmio_base);
qemu_put_be32(f, 0);
qemu_put_be32s(f, &s->rxbuf_size);
qemu_put_be32s(f, &s->rxbuf_min_shift);
qemu_put_be32s(f, &s->eecd_state.val_in);
@@ -916,7 +915,7 @@ nic_load(QEMUFile *f, void *opaque, int version_id)
return ret;
if (version_id == 1)
qemu_get_sbe32s(f, &i); /* once some unused instance id */
qemu_get_be32s(f, &s->mmio_base);
qemu_get_be32(f); /* Ignored. Was mmio_base. */
qemu_get_be32s(f, &s->rxbuf_size);
qemu_get_be32s(f, &s->rxbuf_min_shift);
qemu_get_be32s(f, &s->eecd_state.val_in);
@@ -1005,7 +1004,6 @@ e1000_mmio_map(PCIDevice *pci_dev, int region_num,
DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
d->mmio_base = addr;
cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
}
hw/eepro100.c
-6
View File
@@ -1392,7 +1392,6 @@ static void pci_map(PCIDevice * pci_dev, int region_num,
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
addr -= s->region[0];
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write1(s, addr, val);
}
@@ -1400,7 +1399,6 @@ static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
addr -= s->region[0];
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write2(s, addr, val);
}
@@ -1408,7 +1406,6 @@ static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
addr -= s->region[0];
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write4(s, addr, val);
}
@@ -1416,7 +1413,6 @@ static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
addr -= s->region[0];
//~ logout("addr=%s\n", regname(addr));
return eepro100_read1(s, addr);
}
@@ -1424,7 +1420,6 @@ static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
addr -= s->region[0];
//~ logout("addr=%s\n", regname(addr));
return eepro100_read2(s, addr);
}
@@ -1432,7 +1427,6 @@ static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
addr -= s->region[0];
//~ logout("addr=%s\n", regname(addr));
return eepro100_read4(s, addr);
}
hw/etraxfs_dma.c
+7 -9
View File
@@ -188,7 +188,6 @@ struct fs_dma_channel
struct fs_dma_ctrl
{
CPUState *env;
target_phys_addr_t base;
int nr_channels;
struct fs_dma_channel *channels;
@@ -212,10 +211,10 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
&& ctrl->channels[c].client;
}
static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
static inline int fs_channel(target_phys_addr_t addr)
{
/* Every channel has a 0x2000 ctrl register map. */
return (addr - base) >> 13;
return addr >> 13;
}
#ifdef USE_THIS_DEAD_CODE
@@ -572,7 +571,7 @@ dma_readl (void *opaque, target_phys_addr_t addr)
uint32_t r = 0;
/* Make addr relative to this instances base. */
c = fs_channel(ctrl->base, addr);
c = fs_channel(addr);
addr &= 0x1fff;
switch (addr)
{
@@ -618,7 +617,7 @@ dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
int c;
/* Make addr relative to this instances base. */
c = fs_channel(ctrl->base, addr);
c = fs_channel(addr);
addr &= 0x1fff;
switch (addr)
{
@@ -753,7 +752,6 @@ void *etraxfs_dmac_init(CPUState *env,
ctrl->bh = qemu_bh_new(DMA_run, ctrl);
ctrl->base = base;
ctrl->env = env;
ctrl->nr_channels = nr_channels;
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
@@ -766,9 +764,9 @@ void *etraxfs_dmac_init(CPUState *env,
dma_read,
dma_write,
ctrl);
cpu_register_physical_memory (base + i * 0x2000,
sizeof ctrl->channels[i].regs,
ctrl->channels[i].regmap);
cpu_register_physical_memory_offset (base + i * 0x2000,
sizeof ctrl->channels[i].regs, ctrl->channels[i].regmap,
i * 0x2000);
}
return ctrl;
hw/etraxfs_eth.c
-6
View File
@@ -314,7 +314,6 @@ struct fs_eth
{
CPUState *env;
qemu_irq *irq;
target_phys_addr_t base;
VLANClientState *vc;
int ethregs;
@@ -375,8 +374,6 @@ static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
struct fs_eth *eth = opaque;
uint32_t r = 0;
/* Make addr relative to this instances base. */
addr -= eth->base;
switch (addr) {
case R_STAT:
/* Attach an MDIO/PHY abstraction. */
@@ -428,8 +425,6 @@ eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_eth *eth = opaque;
/* Make addr relative to this instances base. */
addr -= eth->base;
switch (addr)
{
case RW_MA0_LO:
@@ -589,7 +584,6 @@ void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
dma[1].client.pull = NULL;
eth->env = env;
eth->base = base;
eth->irq = irq;
eth->dma_out = dma;
eth->dma_in = dma + 1;
hw/etraxfs_pic.c
-6
View File
@@ -31,7 +31,6 @@
struct fs_pic_state_t
{
CPUState *env;
target_phys_addr_t base;
uint32_t rw_mask;
/* Active interrupt lines. */
@@ -56,8 +55,6 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
struct fs_pic_state_t *fs = opaque;
uint32_t rval;
/* Transform this to a relative addr. */
addr -= fs->base;
switch (addr)
{
case 0x0:
@@ -99,8 +96,6 @@ pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_pic_state_t *fs = opaque;
D(printf("%s addr=%x val=%x\n", __func__, addr, value));
/* Transform this to a relative addr. */
addr -= fs->base;
switch (addr)
{
case 0x0:
@@ -233,7 +228,6 @@ struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
cpu_register_physical_memory(base, 0x14, intr_vect_regs);
fs->base = base;
return pic;
err:
hw/etraxfs_ser.c
-4
View File
@@ -50,8 +50,6 @@ struct etrax_serial_t
CharDriverState *chr;
qemu_irq *irq;
target_phys_addr_t base;
int pending_tx;
/* Control registers. */
@@ -240,8 +238,6 @@ void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
s->env = env;
s->irq = irq;
s->base = base;
s->chr = chr;
/* transmitter begins ready and idle. */
hw/etraxfs_timer.c
-6
View File
@@ -47,7 +47,6 @@ struct fs_timer_t {
CPUState *env;
qemu_irq *irq;
qemu_irq *nmi;
target_phys_addr_t base;
QEMUBH *bh_t0;
QEMUBH *bh_t1;
@@ -90,8 +89,6 @@ static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
struct fs_timer_t *t = opaque;
uint32_t r = 0;
/* Make addr relative to this instances base. */
addr -= t->base;
switch (addr) {
case R_TMR0_DATA:
break;
@@ -273,8 +270,6 @@ timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_timer_t *t = opaque;
/* Make addr relative to this instances base. */
addr -= t->base;
switch (addr)
{
case RW_TMR0_DIV:
@@ -357,7 +352,6 @@ void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
t->irq = irqs;
t->nmi = nmi;
t->env = env;
t->base = base;
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
cpu_register_physical_memory (base, 0x5c, timer_regs);
hw/g364fb.c
+3 -7
View File
@@ -26,7 +26,6 @@
//#define DEBUG_G364
typedef struct G364State {
target_phys_addr_t vram_base;
unsigned int vram_size;
uint8_t *vram_buffer;
uint32_t ctla;
@@ -300,9 +299,8 @@ static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = {
static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr)
{
G364State *s = opaque;
target_phys_addr_t relative_addr = addr - s->vram_base;
return s->vram_buffer[relative_addr];
return s->vram_buffer[addr];
}
static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr)
@@ -326,9 +324,8 @@ static uint32_t g364fb_mem_readl(void *opaque, target_phys_addr_t addr)
static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
G364State *s = opaque;
target_phys_addr_t relative_addr = addr - s->vram_base;
s->vram_buffer[relative_addr] = val;
s->vram_buffer[addr] = val;
}
static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
@@ -375,14 +372,13 @@ int g364fb_mm_init(DisplayState *ds,
g364fb_reset(s);
s->ds = ds;
s->vram_base = vram_base;
s->console = graphic_console_init(ds, g364fb_update_display,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
cpu_register_physical_memory(s->vram_base, vram_size, io_vram);
cpu_register_physical_memory(vram_base, vram_size, io_vram);
io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);
hw/integratorcp.c
+1 -18
View File
@@ -38,7 +38,6 @@ static uint8_t integrator_spd[128] = {
static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
{
integratorcm_state *s = (integratorcm_state *)opaque;
offset -= 0x10000000;
if (offset >= 0x100 && offset < 0x200) {
/* CM_SPD */
if (offset >= 0x180)
@@ -141,7 +140,6 @@ static void integratorcm_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
integratorcm_state *s = (integratorcm_state *)opaque;
offset -= 0x10000000;
switch (offset >> 2) {
case 2: /* CM_OSC */
if (s->cm_lock == 0xa05f)
@@ -268,7 +266,6 @@ static void integratorcm_init(int memsz)
typedef struct icp_pic_state
{
uint32_t base;
uint32_t level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
@@ -300,7 +297,6 @@ static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
{
icp_pic_state *s = (icp_pic_state *)opaque;
offset -= s->base;
switch (offset >> 2) {
case 0: /* IRQ_STATUS */
return s->level & s->irq_enabled;
@@ -329,7 +325,6 @@ static void icp_pic_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
icp_pic_state *s = (icp_pic_state *)opaque;
offset -= s->base;
switch (offset >> 2) {
case 2: /* IRQ_ENABLESET */
@@ -386,7 +381,6 @@ static qemu_irq *icp_pic_init(uint32_t base,
if (!s)
return NULL;
qi = qemu_allocate_irqs(icp_pic_set_irq, s, 32);
s->base = base;
s->parent_irq = parent_irq;
s->parent_fiq = parent_fiq;
iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
@@ -397,14 +391,8 @@ static qemu_irq *icp_pic_init(uint32_t base,
}
/* CP control registers. */
typedef struct {
uint32_t base;
} icp_control_state;
static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
{
icp_control_state *s = (icp_control_state *)opaque;
offset -= s->base;
switch (offset >> 2) {
case 0: /* CP_IDFIELD */
return 0x41034003;
@@ -424,8 +412,6 @@ static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
static void icp_control_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
icp_control_state *s = (icp_control_state *)opaque;
offset -= s->base;
switch (offset >> 2) {
case 1: /* CP_FLASHPROG */
case 2: /* CP_INTREG */
@@ -452,13 +438,10 @@ static CPUWriteMemoryFunc *icp_control_writefn[] = {
static void icp_control_init(uint32_t base)
{
int iomemtype;
icp_control_state *s;
s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state));
iomemtype = cpu_register_io_memory(0, icp_control_readfn,
icp_control_writefn, s);
icp_control_writefn, NULL);
cpu_register_physical_memory(base, 0x00800000, iomemtype);
s->base = base;
/* ??? Save/restore. */
}
hw/iommu.c
+2 -4
View File
@@ -114,7 +114,6 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
#define PAGE_MASK (PAGE_SIZE - 1)
typedef struct IOMMUState {
target_phys_addr_t addr;
uint32_t regs[IOMMU_NREGS];
target_phys_addr_t iostart;
uint32_t version;
@@ -127,7 +126,7 @@ static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
target_phys_addr_t saddr;
uint32_t ret;
saddr = (addr - s->addr) >> 2;
saddr = addr >> 2;
switch (saddr) {
default:
ret = s->regs[saddr];
@@ -148,7 +147,7 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
IOMMUState *s = opaque;
target_phys_addr_t saddr;
saddr = (addr - s->addr) >> 2;
saddr = addr >> 2;
DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
switch (saddr) {
case IOMMU_CTRL:
@@ -358,7 +357,6 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
if (!s)
return NULL;
s->addr = addr;
s->version = version;
s->irq = irq;
hw/jazz_led.c
+3 -7
View File
@@ -34,7 +34,6 @@ typedef enum {
} screen_state_t;
typedef struct LedState {
target_phys_addr_t base;
uint8_t segments;
DisplayState *ds;
QEMUConsole *console;
@@ -44,10 +43,9 @@ typedef struct LedState {
static uint32_t led_readb(void *opaque, target_phys_addr_t addr)
{
LedState *s = opaque;
int relative_addr = addr - s->base;
uint32_t val;
switch (relative_addr) {
switch (addr) {
case 0:
val = s->segments;
break;
@@ -94,9 +92,8 @@ static uint32_t led_readl(void *opaque, target_phys_addr_t addr)
static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LedState *s = opaque;
int relative_addr = addr - s->base;
switch (relative_addr) {
switch (addr) {
case 0:
s->segments = val;
s->state |= REDRAW_SEGMENTS;
@@ -311,12 +308,11 @@ void jazz_led_init(DisplayState *ds, target_phys_addr_t base)
if (!s)
return;
s->base = base;
s->ds = ds;
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
io = cpu_register_io_memory(0, led_read, led_write, s);
cpu_register_physical_memory(s->base, 1, io);
cpu_register_physical_memory(base, 1, io);
s->console = graphic_console_init(ds, jazz_led_update_display,
jazz_led_invalidate_display,
hw/m48t59.c
-8
View File
@@ -46,7 +46,6 @@ struct m48t59_t {
/* Hardware parameters */
qemu_irq IRQ;
int mem_index;
target_phys_addr_t mem_base;
uint32_t io_base;
uint16_t size;
/* RTC management */
@@ -514,7 +513,6 @@ static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
m48t59_t *NVRAM = opaque;
addr -= NVRAM->mem_base;
m48t59_write(NVRAM, addr, value & 0xff);
}
@@ -522,7 +520,6 @@ static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
m48t59_t *NVRAM = opaque;
addr -= NVRAM->mem_base;
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
m48t59_write(NVRAM, addr + 1, value & 0xff);
}
@@ -531,7 +528,6 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
m48t59_t *NVRAM = opaque;
addr -= NVRAM->mem_base;
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
@@ -543,7 +539,6 @@ static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
m48t59_t *NVRAM = opaque;
uint32_t retval;
addr -= NVRAM->mem_base;
retval = m48t59_read(NVRAM, addr);
return retval;
}
@@ -553,7 +548,6 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
m48t59_t *NVRAM = opaque;
uint32_t retval;
addr -= NVRAM->mem_base;
retval = m48t59_read(NVRAM, addr) << 8;
retval |= m48t59_read(NVRAM, addr + 1);
return retval;
@@ -564,7 +558,6 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
m48t59_t *NVRAM = opaque;
uint32_t retval;
addr -= NVRAM->mem_base;
retval = m48t59_read(NVRAM, addr) << 24;
retval |= m48t59_read(NVRAM, addr + 1) << 16;
retval |= m48t59_read(NVRAM, addr + 2) << 8;
@@ -636,7 +629,6 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
}
s->IRQ = IRQ;
s->size = size;
s->mem_base = mem_base;
s->io_base = io_base;
s->addr = 0;
s->type = type;
hw/mac_nvram.c
-4
View File
@@ -26,7 +26,6 @@
#include "ppc_mac.h"
struct MacIONVRAMState {
target_phys_addr_t mem_base;
target_phys_addr_t size;
int mem_index;
uint8_t data[0x2000];
@@ -62,7 +61,6 @@ static void macio_nvram_writeb (void *opaque,
{
MacIONVRAMState *s = opaque;
addr -= s->mem_base;
addr = (addr >> 4) & 0x1fff;
s->data[addr] = value;
// printf("macio_nvram_writeb %04x = %02x\n", addr, value);
@@ -73,7 +71,6 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
MacIONVRAMState *s = opaque;
uint32_t value;
addr -= s->mem_base;
addr = (addr >> 4) & 0x1fff;
value = s->data[addr];
// printf("macio_nvram_readb %04x = %02x\n", addr, value);
@@ -112,7 +109,6 @@ void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
MacIONVRAMState *s;
s = opaque;
s->mem_base = mem_base;
cpu_register_physical_memory(mem_base, s->size, s->mem_index);
}

Some files were not shown because too many files have changed in this diff Show More