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Remove the deprecated moxie target

Browse Source 
There are no known users of this CPU anymore, and there are no
binaries available online which could be used for regression tests,
so the code has likely completely bit-rotten already. It's been
marked as deprecated since two releases now and nobody spoke up
that there is still a need to keep it, thus let's remove it now.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210430160355.698194-1-thuth@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[Commit message typos fixed, trivial conflicts resolved]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
This commit is contained in:
Thomas Huth
2021-05-12 17:42:23 +02:00
committed by Markus Armbruster
parent a67b996e78
commit 875bb7e35b
38 changed files with 13 additions and 1987 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.gitlab-ci.yml
+3 -3
View File
@@ -89,7 +89,7 @@ build-system-alpine:
variables:
IMAGE: alpine
TARGETS: aarch64-softmmu alpha-softmmu cris-softmmu hppa-softmmu
moxie-softmmu microblazeel-softmmu mips64el-softmmu
microblazeel-softmmu mips64el-softmmu
MAKE_CHECK_ARGS: check-build
CONFIGURE_ARGS: --enable-docs --enable-trace-backends=log,simple,syslog
artifacts:
@@ -125,7 +125,7 @@ build-system-ubuntu:
IMAGE: ubuntu2004
CONFIGURE_ARGS: --enable-docs --enable-fdt=system --enable-slirp=system
TARGETS: aarch64-softmmu alpha-softmmu cris-softmmu hppa-softmmu
moxie-softmmu microblazeel-softmmu mips64el-softmmu
microblazeel-softmmu mips64el-softmmu
MAKE_CHECK_ARGS: check-build
artifacts:
expire_in: 2 days
@@ -684,7 +684,7 @@ build-tci:
variables:
IMAGE: debian-all-test-cross
script:
- TARGETS="aarch64 alpha arm hppa m68k microblaze moxie ppc64 s390x x86_64"
- TARGETS="aarch64 alpha arm hppa m68k microblaze ppc64 s390x x86_64"
- mkdir build
- cd build
- ../configure --enable-tcg-interpreter
MAINTAINERS
-8
View File
@@ -258,14 +258,6 @@ MIPS TCG CPUs (nanoMIPS ISA)
S: Orphan
F: disas/nanomips.*
Moxie TCG CPUs
M: Anthony Green <green@moxielogic.com>
S: Maintained
F: target/moxie/
F: disas/moxie.c
F: hw/moxie/
F: default-configs/*/moxie-softmmu.mak
NiosII TCG CPUs
M: Chris Wulff <crwulff@gmail.com>
M: Marek Vasut <marex@denx.de>
default-configs/devices/moxie-softmmu.mak
-5
View File
@@ -1,5 +0,0 @@
# Default configuration for moxie-softmmu
# Boards:
#
CONFIG_MOXIESIM=y
default-configs/targets/moxie-softmmu.mak
-2
View File
@@ -1,2 +0,0 @@
TARGET_ARCH=moxie
TARGET_WORDS_BIGENDIAN=y
disas/meson.build
-1
View File
@@ -13,7 +13,6 @@ common_ss.add(when: 'CONFIG_LM32_DIS', if_true: files('lm32.c'))
common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c'))
common_ss.add(when: 'CONFIG_MICROBLAZE_DIS', if_true: files('microblaze.c'))
common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c'))
common_ss.add(when: 'CONFIG_MOXIE_DIS', if_true: files('moxie.c'))
common_ss.add(when: 'CONFIG_NANOMIPS_DIS', if_true: files('nanomips.cpp'))
common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c'))
common_ss.add(when: 'CONFIG_PPC_DIS', if_true: files('ppc.c'))
disas/moxie.c
-360
View File
@@ -1,360 +0,0 @@
/* Disassemble moxie instructions.
Copyright (c) 2009 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
#include "qemu/osdep.h"
#define STATIC_TABLE
#define DEFINE_TABLE
#include "disas/dis-asm.h"
static void *stream;
/* Form 1 instructions come in different flavors:
Some have no arguments (MOXIE_F1_NARG)
Some only use the A operand (MOXIE_F1_A)
Some use A and B registers (MOXIE_F1_AB)
Some use A and consume a 4 byte immediate value (MOXIE_F1_A4)
Some use just a 4 byte immediate value (MOXIE_F1_4)
Some use just a 4 byte memory address (MOXIE_F1_M)
Some use B and an indirect A (MOXIE_F1_AiB)
Some use A and an indirect B (MOXIE_F1_ABi)
Some consume a 4 byte immediate value and use X (MOXIE_F1_4A)
Some use B and an indirect A plus 4 bytes (MOXIE_F1_AiB4)
Some use A and an indirect B plus 4 bytes (MOXIE_F1_ABi4)
Form 2 instructions also come in different flavors:
Some have no arguments (MOXIE_F2_NARG)
Some use the A register and an 8-bit value (MOXIE_F2_A8V)
Form 3 instructions also come in different flavors:
Some have no arguments (MOXIE_F3_NARG)
Some have a 10-bit PC relative operand (MOXIE_F3_PCREL). */
#define MOXIE_F1_NARG 0x100
#define MOXIE_F1_A 0x101
#define MOXIE_F1_AB 0x102
/* #define MOXIE_F1_ABC 0x103 */
#define MOXIE_F1_A4 0x104
#define MOXIE_F1_4 0x105
#define MOXIE_F1_AiB 0x106
#define MOXIE_F1_ABi 0x107
#define MOXIE_F1_4A 0x108
#define MOXIE_F1_AiB4 0x109
#define MOXIE_F1_ABi4 0x10a
#define MOXIE_F1_M 0x10b
#define MOXIE_F2_NARG 0x200
#define MOXIE_F2_A8V 0x201
#define MOXIE_F3_NARG 0x300
#define MOXIE_F3_PCREL 0x301
typedef struct moxie_opc_info_t {
short opcode;
unsigned itype;
const char * name;
} moxie_opc_info_t;
extern const moxie_opc_info_t moxie_form1_opc_info[64];
extern const moxie_opc_info_t moxie_form2_opc_info[4];
extern const moxie_opc_info_t moxie_form3_opc_info[16];
/* The moxie processor's 16-bit instructions come in two forms:
FORM 1 instructions start with a 0 bit...
0oooooooaaaabbbb
0 F
ooooooo - form 1 opcode number
aaaa - operand A
bbbb - operand B
FORM 2 instructions start with bits "10"...
10ooaaaavvvvvvvv
0 F
oo - form 2 opcode number
aaaa - operand A
vvvvvvvv - 8-bit immediate value
FORM 3 instructions start with a bits "11"...
11oooovvvvvvvvvv
0 F
oooo - form 3 opcode number
vvvvvvvvvv - 10-bit immediate value. */
const moxie_opc_info_t moxie_form1_opc_info[64] =
{
{ 0x00, MOXIE_F1_NARG, "nop" },
{ 0x01, MOXIE_F1_A4, "ldi.l" },
{ 0x02, MOXIE_F1_AB, "mov" },
{ 0x03, MOXIE_F1_M, "jsra" },
{ 0x04, MOXIE_F1_NARG, "ret" },
{ 0x05, MOXIE_F1_AB, "add.l" },
{ 0x06, MOXIE_F1_AB, "push" },
{ 0x07, MOXIE_F1_AB, "pop" },
{ 0x08, MOXIE_F1_A4, "lda.l" },
{ 0x09, MOXIE_F1_4A, "sta.l" },
{ 0x0a, MOXIE_F1_ABi, "ld.l" },
{ 0x0b, MOXIE_F1_AiB, "st.l" },
{ 0x0c, MOXIE_F1_ABi4, "ldo.l" },
{ 0x0d, MOXIE_F1_AiB4, "sto.l" },
{ 0x0e, MOXIE_F1_AB, "cmp" },
{ 0x0f, MOXIE_F1_NARG, "bad" },
{ 0x10, MOXIE_F1_NARG, "bad" },
{ 0x11, MOXIE_F1_NARG, "bad" },
{ 0x12, MOXIE_F1_NARG, "bad" },
{ 0x13, MOXIE_F1_NARG, "bad" },
{ 0x14, MOXIE_F1_NARG, "bad" },
{ 0x15, MOXIE_F1_NARG, "bad" },
{ 0x16, MOXIE_F1_NARG, "bad" },
{ 0x17, MOXIE_F1_NARG, "bad" },
{ 0x18, MOXIE_F1_NARG, "bad" },
{ 0x19, MOXIE_F1_A, "jsr" },
{ 0x1a, MOXIE_F1_M, "jmpa" },
{ 0x1b, MOXIE_F1_A4, "ldi.b" },
{ 0x1c, MOXIE_F1_ABi, "ld.b" },
{ 0x1d, MOXIE_F1_A4, "lda.b" },
{ 0x1e, MOXIE_F1_AiB, "st.b" },
{ 0x1f, MOXIE_F1_4A, "sta.b" },
{ 0x20, MOXIE_F1_A4, "ldi.s" },
{ 0x21, MOXIE_F1_ABi, "ld.s" },
{ 0x22, MOXIE_F1_A4, "lda.s" },
{ 0x23, MOXIE_F1_AiB, "st.s" },
{ 0x24, MOXIE_F1_4A, "sta.s" },
{ 0x25, MOXIE_F1_A, "jmp" },
{ 0x26, MOXIE_F1_AB, "and" },
{ 0x27, MOXIE_F1_AB, "lshr" },
{ 0x28, MOXIE_F1_AB, "ashl" },
{ 0x29, MOXIE_F1_AB, "sub.l" },
{ 0x2a, MOXIE_F1_AB, "neg" },
{ 0x2b, MOXIE_F1_AB, "or" },
{ 0x2c, MOXIE_F1_AB, "not" },
{ 0x2d, MOXIE_F1_AB, "ashr" },
{ 0x2e, MOXIE_F1_AB, "xor" },
{ 0x2f, MOXIE_F1_AB, "mul.l" },
{ 0x30, MOXIE_F1_4, "swi" },
{ 0x31, MOXIE_F1_AB, "div.l" },
{ 0x32, MOXIE_F1_AB, "udiv.l" },
{ 0x33, MOXIE_F1_AB, "mod.l" },
{ 0x34, MOXIE_F1_AB, "umod.l" },
{ 0x35, MOXIE_F1_NARG, "brk" },
{ 0x36, MOXIE_F1_ABi4, "ldo.b" },
{ 0x37, MOXIE_F1_AiB4, "sto.b" },
{ 0x38, MOXIE_F1_ABi4, "ldo.s" },
{ 0x39, MOXIE_F1_AiB4, "sto.s" },
{ 0x3a, MOXIE_F1_NARG, "bad" },
{ 0x3b, MOXIE_F1_NARG, "bad" },
{ 0x3c, MOXIE_F1_NARG, "bad" },
{ 0x3d, MOXIE_F1_NARG, "bad" },
{ 0x3e, MOXIE_F1_NARG, "bad" },
{ 0x3f, MOXIE_F1_NARG, "bad" }
};
const moxie_opc_info_t moxie_form2_opc_info[4] =
{
{ 0x00, MOXIE_F2_A8V, "inc" },
{ 0x01, MOXIE_F2_A8V, "dec" },
{ 0x02, MOXIE_F2_A8V, "gsr" },
{ 0x03, MOXIE_F2_A8V, "ssr" }
};
const moxie_opc_info_t moxie_form3_opc_info[16] =
{
{ 0x00, MOXIE_F3_PCREL,"beq" },
{ 0x01, MOXIE_F3_PCREL,"bne" },
{ 0x02, MOXIE_F3_PCREL,"blt" },
{ 0x03, MOXIE_F3_PCREL,"bgt" },
{ 0x04, MOXIE_F3_PCREL,"bltu" },
{ 0x05, MOXIE_F3_PCREL,"bgtu" },
{ 0x06, MOXIE_F3_PCREL,"bge" },
{ 0x07, MOXIE_F3_PCREL,"ble" },
{ 0x08, MOXIE_F3_PCREL,"bgeu" },
{ 0x09, MOXIE_F3_PCREL,"bleu" },
{ 0x0a, MOXIE_F3_NARG, "bad" },
{ 0x0b, MOXIE_F3_NARG, "bad" },
{ 0x0c, MOXIE_F3_NARG, "bad" },
{ 0x0d, MOXIE_F3_NARG, "bad" },
{ 0x0e, MOXIE_F3_NARG, "bad" },
{ 0x0f, MOXIE_F3_NARG, "bad" }
};
/* Macros to extract operands from the instruction word. */
#define OP_A(i) ((i >> 4) & 0xf)
#define OP_B(i) (i & 0xf)
#define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1)
static const char * reg_names[16] =
{ "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
"$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
int
print_insn_moxie(bfd_vma addr, struct disassemble_info * info)
{
int length = 2;
int status;
stream = info->stream;
const moxie_opc_info_t * opcode;
bfd_byte buffer[4];
unsigned short iword;
fprintf_function fpr = info->fprintf_func;
if ((status = info->read_memory_func(addr, buffer, 2, info)))
goto fail;
iword = (bfd_getb16(buffer) >> 16);
/* Form 1 instructions have the high bit set to 0. */
if ((iword & (1<<15)) == 0) {
/* Extract the Form 1 opcode. */
opcode = &moxie_form1_opc_info[iword >> 8];
switch (opcode->itype) {
case MOXIE_F1_NARG:
fpr(stream, "%s", opcode->name);
break;
case MOXIE_F1_A:
fpr(stream, "%s\t%s", opcode->name,
reg_names[OP_A(iword)]);
break;
case MOXIE_F1_AB:
fpr(stream, "%s\t%s, %s", opcode->name,
reg_names[OP_A(iword)],
reg_names[OP_B(iword)]);
break;
case MOXIE_F1_A4:
{
unsigned imm;
if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t%s, 0x%x", opcode->name,
reg_names[OP_A(iword)], imm);
length = 6;
}
break;
case MOXIE_F1_4:
{
unsigned imm;
if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t0x%x", opcode->name, imm);
length = 6;
}
break;
case MOXIE_F1_M:
{
unsigned imm;
if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t", opcode->name);
info->print_address_func((bfd_vma) imm, info);
length = 6;
}
break;
case MOXIE_F1_AiB:
fpr (stream, "%s\t(%s), %s", opcode->name,
reg_names[OP_A(iword)], reg_names[OP_B(iword)]);
break;
case MOXIE_F1_ABi:
fpr(stream, "%s\t%s, (%s)", opcode->name,
reg_names[OP_A(iword)], reg_names[OP_B(iword)]);
break;
case MOXIE_F1_4A:
{
unsigned imm;
if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t0x%x, %s",
opcode->name, imm, reg_names[OP_A(iword)]);
length = 6;
}
break;
case MOXIE_F1_AiB4:
{
unsigned imm;
if ((status = info->read_memory_func(addr+2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t0x%x(%s), %s", opcode->name,
imm,
reg_names[OP_A(iword)],
reg_names[OP_B(iword)]);
length = 6;
}
break;
case MOXIE_F1_ABi4:
{
unsigned imm;
if ((status = info->read_memory_func(addr+2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t%s, 0x%x(%s)",
opcode->name,
reg_names[OP_A(iword)],
imm,
reg_names[OP_B(iword)]);
length = 6;
}
break;
default:
abort();
}
}
else if ((iword & (1<<14)) == 0) {
/* Extract the Form 2 opcode. */
opcode = &moxie_form2_opc_info[(iword >> 12) & 3];
switch (opcode->itype) {
case MOXIE_F2_A8V:
fpr(stream, "%s\t%s, 0x%x",
opcode->name,
reg_names[(iword >> 8) & 0xf],
iword & ((1 << 8) - 1));
break;
case MOXIE_F2_NARG:
fpr(stream, "%s", opcode->name);
break;
default:
abort();
}
} else {
/* Extract the Form 3 opcode. */
opcode = &moxie_form3_opc_info[(iword >> 10) & 15];
switch (opcode->itype) {
case MOXIE_F3_PCREL:
fpr(stream, "%s\t", opcode->name);
info->print_address_func((bfd_vma) (addr + INST2OFFSET(iword) + 2),
info);
break;
default:
abort();
}
}
return length;
fail:
info->memory_error_func(status, addr, info);
return -1;
}
docs/system/deprecated.rst
-8
View File
@@ -198,14 +198,6 @@ from Linux upstream kernel, declare it deprecated.
System emulator CPUS
--------------------
``moxie`` CPU (since 5.2.0)
'''''''''''''''''''''''''''
The ``moxie`` guest CPU support is deprecated and will be removed in
a future version of QEMU. It's unclear whether anybody is still using
CPU emulation in QEMU, and there are no test images available to make
sure that the code is still working.
``lm32`` CPUs (since 5.2.0)
'''''''''''''''''''''''''''
docs/system/removed-features.rst
+7
View File
@@ -291,6 +291,13 @@ via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
The ``max-cpu-compat`` property of the ``pseries`` machine type should be used
instead.
``moxie`` CPU (removed in 6.1)
''''''''''''''''''''''''''''''
Nobody was using this CPU emulation in QEMU, and there were no test images
available to make sure that the code is still working, so it has been removed
without replacement.
System emulator machines
------------------------
fpu/softfloat-specialize.c.inc
+1 -1
View File
@@ -152,7 +152,7 @@ static FloatParts parts_default_nan(float_status *status)
/* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
* S390, SH4, TriCore, and Xtensa. I cannot find documentation
* for Unicore32; the choice from the original commit is unchanged.
* Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile,
* Our other supported targets, CRIS, LM32, and Nios2,
* do not have floating-point.
*/
if (snan_bit_is_one(status)) {
hw/Kconfig
-1
View File
@@ -51,7 +51,6 @@ source lm32/Kconfig
source m68k/Kconfig
source microblaze/Kconfig
source mips/Kconfig
source moxie/Kconfig
source nios2/Kconfig
source openrisc/Kconfig
source ppc/Kconfig
hw/meson.build
-1
View File
@@ -51,7 +51,6 @@ subdir('lm32')
subdir('m68k')
subdir('microblaze')
subdir('mips')
subdir('moxie')
subdir('nios2')
subdir('openrisc')
subdir('ppc')
hw/moxie/Kconfig
-3
View File
@@ -1,3 +0,0 @@
config MOXIESIM
bool
select SERIAL
hw/moxie/meson.build
-4
View File
@@ -1,4 +0,0 @@
moxie_ss = ss.source_set()
moxie_ss.add(when: 'CONFIG_MOXIESIM', if_true: files('moxiesim.c'))
hw_arch += {'moxie': moxie_ss}
hw/moxie/moxiesim.c
-155
View File
@@ -1,155 +0,0 @@
/*
* QEMU/moxiesim emulation
*
* Emulates a very simple machine model similar to the one used by the
* GDB moxie simulator.
*
* Copyright (c) 2008, 2009, 2010, 2013 Anthony Green
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "cpu.h"
#include "net/net.h"
#include "sysemu/reset.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/char/serial.h"
#include "elf.h"
#define PHYS_MEM_BASE 0x80000000
#define FIRMWARE_BASE 0x1000
#define FIRMWARE_SIZE (128 * 0x1000)
typedef struct {
uint64_t ram_size;
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
} LoaderParams;
static void load_kernel(MoxieCPU *cpu, LoaderParams *loader_params)
{
uint64_t entry, kernel_high;
int64_t initrd_size;
long kernel_size;
ram_addr_t initrd_offset;
kernel_size = load_elf(loader_params->kernel_filename, NULL, NULL, NULL,
&entry, NULL, &kernel_high, NULL, 1, EM_MOXIE,
0, 0);
if (kernel_size <= 0) {
error_report("could not load kernel '%s'",
loader_params->kernel_filename);
exit(1);
}
/* load initrd */
initrd_size = 0;
initrd_offset = 0;
if (loader_params->initrd_filename) {
initrd_size = get_image_size(loader_params->initrd_filename);
if (initrd_size > 0) {
initrd_offset = (kernel_high + ~TARGET_PAGE_MASK)
& TARGET_PAGE_MASK;
if (initrd_offset + initrd_size > loader_params->ram_size) {
error_report("memory too small for initial ram disk '%s'",
loader_params->initrd_filename);
exit(1);
}
initrd_size = load_image_targphys(loader_params->initrd_filename,
initrd_offset,
loader_params->ram_size);
}
if (initrd_size == (target_ulong)-1) {
error_report("could not load initial ram disk '%s'",
loader_params->initrd_filename);
exit(1);
}
}
}
static void main_cpu_reset(void *opaque)
{
MoxieCPU *cpu = opaque;
cpu_reset(CPU(cpu));
}
static void moxiesim_init(MachineState *machine)
{
MoxieCPU *cpu = NULL;
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
CPUMoxieState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *rom = g_new(MemoryRegion, 1);
hwaddr ram_base = 0x200000;
LoaderParams loader_params;
/* Init CPUs. */
cpu = MOXIE_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* Allocate RAM. */
memory_region_init_ram(ram, NULL, "moxiesim.ram", ram_size, &error_fatal);
memory_region_add_subregion(address_space_mem, ram_base, ram);
memory_region_init_ram(rom, NULL, "moxie.rom", FIRMWARE_SIZE, &error_fatal);
memory_region_add_subregion(get_system_memory(), FIRMWARE_BASE, rom);
if (kernel_filename) {
loader_params.ram_size = ram_size;
loader_params.kernel_filename = kernel_filename;
loader_params.kernel_cmdline = kernel_cmdline;
loader_params.initrd_filename = initrd_filename;
load_kernel(cpu, &loader_params);
}
if (machine->firmware) {
if (load_image_targphys(machine->firmware, FIRMWARE_BASE, FIRMWARE_SIZE) < 0) {
error_report("Failed to load firmware '%s'", machine->firmware);
}
}
/* A single 16450 sits at offset 0x3f8. */
if (serial_hd(0)) {
serial_mm_init(address_space_mem, 0x3f8, 0, env->irq[4],
8000000/16, serial_hd(0), DEVICE_LITTLE_ENDIAN);
}
}
static void moxiesim_machine_init(MachineClass *mc)
{
mc->desc = "Moxie simulator platform";
mc->init = moxiesim_init;
mc->is_default = true;
mc->default_cpu_type = MOXIE_CPU_TYPE_NAME("MoxieLite");
}
DEFINE_MACHINE("moxiesim", moxiesim_machine_init)
include/disas/dis-asm.h
-1
View File
@@ -443,7 +443,6 @@ int print_insn_m32r (bfd_vma, disassemble_info*);
int print_insn_m88k (bfd_vma, disassemble_info*);
int print_insn_mn10200 (bfd_vma, disassemble_info*);
int print_insn_mn10300 (bfd_vma, disassemble_info*);
int print_insn_moxie (bfd_vma, disassemble_info*);
int print_insn_ns32k (bfd_vma, disassemble_info*);
int print_insn_big_powerpc (bfd_vma, disassemble_info*);
int print_insn_little_powerpc (bfd_vma, disassemble_info*);
include/elf.h
-3
View File
@@ -206,9 +206,6 @@ typedef struct mips_elf_abiflags_v0 {
#define EM_AARCH64 183
#define EM_MOXIE 223 /* Moxie processor family */
#define EM_MOXIE_OLD 0xFEED
#define EF_AVR_MACH 0x7F /* Mask for AVR e_flags to get core type */
/* This is the info that is needed to parse the dynamic section of the file */
include/exec/poison.h
-2
View File
@@ -20,7 +20,6 @@
#pragma GCC poison TARGET_ABI_MIPSO32
#pragma GCC poison TARGET_MIPS64
#pragma GCC poison TARGET_ABI_MIPSN64
#pragma GCC poison TARGET_MOXIE
#pragma GCC poison TARGET_NIOS2
#pragma GCC poison TARGET_OPENRISC
#pragma GCC poison TARGET_PPC
@@ -79,7 +78,6 @@
#pragma GCC poison CONFIG_MICROBLAZE_DIS
#pragma GCC poison CONFIG_MIPS_DIS
#pragma GCC poison CONFIG_NANOMIPS_DIS
#pragma GCC poison CONFIG_MOXIE_DIS
#pragma GCC poison CONFIG_NIOS2_DIS
#pragma GCC poison CONFIG_PPC_DIS
#pragma GCC poison CONFIG_RISCV_DIS
include/hw/elf_ops.h
-8
View File
@@ -368,14 +368,6 @@ static int glue(load_elf, SZ)(const char *name, int fd,
}
}
break;
case EM_MOXIE:
if (ehdr.e_machine != EM_MOXIE) {
if (ehdr.e_machine != EM_MOXIE_OLD) {
ret = ELF_LOAD_WRONG_ARCH;
goto fail;
}
}
break;
case EM_MIPS:
case EM_NANOMIPS:
if ((ehdr.e_machine != EM_MIPS) &&
include/sysemu/arch_init.h
-1
View File
@@ -19,7 +19,6 @@ enum {
QEMU_ARCH_XTENSA = (1 << 12),
QEMU_ARCH_OPENRISC = (1 << 13),
QEMU_ARCH_UNICORE32 = (1 << 14),
QEMU_ARCH_MOXIE = (1 << 15),
QEMU_ARCH_TRICORE = (1 << 16),
QEMU_ARCH_NIOS2 = (1 << 17),
QEMU_ARCH_HPPA = (1 << 18),
meson.build
-1
View File
@@ -1214,7 +1214,6 @@ disassemblers = {
'm68k' : ['CONFIG_M68K_DIS'],
'microblaze' : ['CONFIG_MICROBLAZE_DIS'],
'mips' : ['CONFIG_MIPS_DIS'],
'moxie' : ['CONFIG_MOXIE_DIS'],
'nios2' : ['CONFIG_NIOS2_DIS'],
'or1k' : ['CONFIG_OPENRISC_DIS'],
'ppc' : ['CONFIG_PPC_DIS'],

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