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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140324' into staging

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target-arm queue for 2.0:
 * Fix wrong-results bug in A64 Neon MLS instruction
 * Fix loading of ELF images for 32 bit boards in qemu-system-aarch64

# gpg: Signature made Mon 24 Mar 2014 17:14:07 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20140324:
  target-arm: Load ELF images with the correct machine type for CPU
  target-arm: Fix A64 Neon MLS

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2014-03-24 19:25:09 +00:00
parent 90c49ef165 da0af40dd7
commit 839a554757
2 changed files with 5 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/arm/boot.c
+4 -1
View File
@@ -448,6 +448,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
int initrd_size;
int is_linux = 0;
uint64_t elf_entry;
int elf_machine;
hwaddr entry, kernel_load_offset;
int big_endian;
static const ARMInsnFixup *primary_loader;
@@ -463,9 +464,11 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
primary_loader = bootloader_aarch64;
kernel_load_offset = KERNEL64_LOAD_ADDR;
elf_machine = EM_AARCH64;
} else {
primary_loader = bootloader;
kernel_load_offset = KERNEL_LOAD_ADDR;
elf_machine = EM_ARM;
}
info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
@@ -501,7 +504,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
/* Assume that raw images are linux kernels, and ELF images are not. */
kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
NULL, NULL, big_endian, ELF_MACHINE, 1);
NULL, NULL, big_endian, elf_machine, 1);
entry = elf_entry;
if (kernel_size < 0) {
kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
target-arm/translate-a64.c
+1 -1
View File
@@ -8925,7 +8925,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn = fns[size][is_sub];
read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
genfn(tcg_res, tcg_res, tcg_op1);
genfn(tcg_res, tcg_op1, tcg_res);
}
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);