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Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into staging

Browse Source 
aspeed queue:

* Fixed memory leaks in qtest tests
* Reworked and fixed HACE (crypto) model for AST2700 SoC
* Extended HACE qtest tests
* Fixed RAM size detection on BE hosts
* Added network backends to ast2700fc machine
* Mapped main SoC memory into system memory on multi SoC machines

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# =00WM
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 26 May 2025 04:04:38 EDT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu: (39 commits)
  docs: Remove ast2700fc from Aspeed family boards
  hw/arm/fby35: Map BMC memory into system memory
  hw/arm/aspeed_ast27x0-fc: Map ca35 memory into system memory
  hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom
  hw/arm/aspeed_ast2700-fc: Reduce ca35 ram size to align with ast2700a1
  hw/arm/aspeed_ast2700-fc: Add network support
  hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts
  hw/intc/aspeed Fix coding style
  hw/intc/aspeed: Set impl.min_access_size to 4
  test/qtest/hace: Add tests for AST2700
  test/qtest/hace: Support to validate 64-bit hmac key buffer addresses
  test/qtest/hace: Support to test upper 32 bits of digest and source addresses
  test/qtest/hace: Support 64-bit source and digest addresses for AST2700
  test/qtest/hace: Update source data and digest data type to 64-bit
  test/qtest/hace: Add tests for AST1030
  test/qtest/hace: Add SHA-384 tests for AST2600
  test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model
  test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations
  test/qtest/hace: Specify explicit array sizes for test vectors and hash results
  test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
2025-05-26 10:16:59 -04:00
parent 3c5a5e213e 8eaea4012c
commit 80db93b2b8
15 changed files with 1340 additions and 673 deletions
Download Patch File Download Diff File Expand all files Collapse all files
docs/system/arm/aspeed.rst
+1 -1
View File
@@ -1,4 +1,4 @@
Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``ast2700fc``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
=================================================================================================================================================================================================================================================================================================================================================================================================================================
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
hw/arm/aspeed_ast27x0-fc.c
+9 -1
View File
@@ -48,7 +48,7 @@ struct Ast2700FCState {
bool mmio_exec;
};
#define AST2700FC_BMC_RAM_SIZE (2 * GiB)
#define AST2700FC_BMC_RAM_SIZE (1 * GiB)
#define AST2700FC_CM4_DRAM_SIZE (32 * MiB)
#define AST2700FC_HW_STRAP1 0x000000C0
@@ -68,6 +68,7 @@ static void ast2700fc_ca35_init(MachineState *machine)
memory_region_init(&s->ca35_memory, OBJECT(&s->ca35), "ca35-memory",
UINT64_MAX);
memory_region_add_subregion(get_system_memory(), 0, &s->ca35_memory);
if (!memory_region_init_ram(&s->ca35_dram, OBJECT(&s->ca35), "ca35-dram",
AST2700FC_BMC_RAM_SIZE, &error_abort)) {
@@ -86,6 +87,13 @@ static void ast2700fc_ca35_init(MachineState *machine)
AST2700FC_BMC_RAM_SIZE, &error_abort)) {
return;
}
for (int i = 0; i < sc->macs_num; i++) {
if (!qemu_configure_nic_device(DEVICE(&soc->ftgmac100[i]),
true, NULL)) {
break;
}
}
if (!object_property_set_int(OBJECT(&s->ca35), "hw-strap1",
AST2700FC_HW_STRAP1, &error_abort)) {
return;
hw/arm/aspeed_ast27x0.c
+8 -6
View File
@@ -23,14 +23,14 @@
#include "qobject/qlist.h"
#include "qemu/log.h"
#define AST2700_SOC_IO_SIZE 0x01000000
#define AST2700_SOC_IO_SIZE 0x00FE0000
#define AST2700_SOC_IOMEM_SIZE 0x01000000
#define AST2700_SOC_DPMCU_SIZE 0x00040000
#define AST2700_SOC_LTPI_SIZE 0x01000000
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_IOMEM] = 0x00000000,
[ASPEED_DEV_VBOOTROM] = 0x00000000,
[ASPEED_DEV_IOMEM] = 0x00020000,
[ASPEED_DEV_SRAM] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x11000000,
[ASPEED_DEV_IOMEM0] = 0x12000000,
@@ -346,8 +346,9 @@ static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data,
* If writes the data to the address which is beyond the ram size,
* it would write the data to the "address % ram_size".
*/
result = address_space_write(&s->dram_as, addr % ram_size,
MEMTXATTRS_UNSPECIFIED, &data, 4);
address_space_stl_le(&s->dram_as, addr % ram_size, data,
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: DRAM write failed, addr:0x%" HWADDR_PRIx
@@ -360,9 +361,10 @@ static const MemoryRegionOps aspeed_ram_capacity_ops = {
.read = aspeed_ram_capacity_read,
.write = aspeed_ram_capacity_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.valid = {
.min_access_size = 1,
.max_access_size = 8,
.min_access_size = 4,
.max_access_size = 4,
},
};
hw/arm/fby35.c
+1
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@@ -77,6 +77,7 @@ static void fby35_bmc_init(Fby35State *s)
memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
UINT64_MAX);
memory_region_add_subregion(get_system_memory(), 0, &s->bmc_memory);
memory_region_init_ram(&s->bmc_dram, OBJECT(&s->bmc), "bmc-dram",
FBY35_BMC_RAM_SIZE, &error_abort);
hw/intc/aspeed_intc.c
+10 -2
View File
@@ -737,6 +737,7 @@ static const MemoryRegionOps aspeed_intc_ops = {
.read = aspeed_intc_read,
.write = aspeed_intc_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -747,6 +748,7 @@ static const MemoryRegionOps aspeed_intcio_ops = {
.read = aspeed_intcio_read,
.write = aspeed_intcio_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -757,6 +759,7 @@ static const MemoryRegionOps aspeed_ssp_intc_ops = {
.read = aspeed_intc_read,
.write = aspeed_ssp_intc_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -767,6 +770,7 @@ static const MemoryRegionOps aspeed_ssp_intcio_ops = {
.read = aspeed_intcio_read,
.write = aspeed_ssp_intcio_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -777,6 +781,7 @@ static const MemoryRegionOps aspeed_tsp_intc_ops = {
.read = aspeed_intc_read,
.write = aspeed_tsp_intc_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -787,6 +792,7 @@ static const MemoryRegionOps aspeed_tsp_intcio_ops = {
.read = aspeed_intcio_read,
.write = aspeed_tsp_intcio_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -995,7 +1001,8 @@ static AspeedINTCIRQ aspeed_2700ssp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
{5, 5, 1, R_SSPINT165_EN, R_SSPINT165_STATUS},
};
static void aspeed_2700ssp_intcio_class_init(ObjectClass *klass, const void *data)
static void aspeed_2700ssp_intcio_class_init(ObjectClass *klass,
const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
@@ -1063,7 +1070,8 @@ static AspeedINTCIRQ aspeed_2700tsp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
{5, 5, 1, R_TSPINT165_EN, R_TSPINT165_STATUS},
};
static void aspeed_2700tsp_intcio_class_init(ObjectClass *klass, const void *data)
static void aspeed_2700tsp_intcio_class_init(ObjectClass *klass,
const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
hw/misc/aspeed_hace.c
+347 -170
View File
File diff suppressed because it is too large Load Diff
hw/misc/trace-events
+8
View File
@@ -302,6 +302,14 @@ aspeed_peci_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%"
aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRIx32 " status 0x%" PRIx32
# aspeed_hace.c
aspeed_hace_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_hace_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_hace_hash_sg(int index, uint64_t list_addr, uint64_t buf_addr, uint32_t len) "%d: list_addr 0x%" PRIx64 " buf_addr 0x%" PRIx64 " len 0x%" PRIx32
aspeed_hace_hash_addr(const char *s, uint64_t addr) "%s: 0x%" PRIx64
aspeed_hace_hash_execute_acc_mode(bool final_request) "final request: %d"
aspeed_hace_hexdump(const char *desc, uint32_t offset, char *s) "%s: 0x%08x: %s"
# bcm2835_property.c
bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu"
include/hw/misc/aspeed_hace.h
+7 -4
View File
@@ -22,7 +22,6 @@
OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
#define ASPEED_HACE_NR_REGS (0x64 >> 2)
#define ASPEED_HACE_MAX_SG 256 /* max number of entries */
struct AspeedHACEState {
@@ -31,10 +30,8 @@ struct AspeedHACEState {
MemoryRegion iomem;
qemu_irq irq;
struct iovec iov_cache[ASPEED_HACE_MAX_SG];
uint32_t regs[ASPEED_HACE_NR_REGS];
uint32_t *regs;
uint32_t total_req_len;
uint32_t iov_count;
MemoryRegion *dram_mr;
AddressSpace dram_as;
@@ -46,11 +43,17 @@ struct AspeedHACEState {
struct AspeedHACEClass {
SysBusDeviceClass parent_class;
const MemoryRegionOps *reg_ops;
uint32_t src_mask;
uint32_t dest_mask;
uint32_t key_mask;
uint32_t hash_mask;
uint64_t nr_regs;
bool raise_crypt_interrupt_workaround;
uint32_t src_hi_mask;
uint32_t dest_hi_mask;
uint32_t key_hi_mask;
bool has_dma64;
};
#endif /* ASPEED_HACE_H */
tests/qtest/aspeed-hace-utils.c
+646
View File
File diff suppressed because it is too large Load Diff
tests/qtest/aspeed-hace-utils.h
+84
View File
@@ -0,0 +1,84 @@
/*
* QTest testcase for the ASPEED Hash and Crypto Engine
*
* SPDX-License-Identifier: GPL-2.0-or-later
* Copyright 2021 IBM Corp.
*/
#ifndef TESTS_ASPEED_HACE_UTILS_H
#define TESTS_ASPEED_HACE_UTILS_H
#include "qemu/osdep.h"
#include "libqtest.h"
#include "qemu/bitops.h"
#define HACE_CMD 0x10
#define HACE_SHA_BE_EN BIT(3)
#define HACE_MD5_LE_EN BIT(2)
#define HACE_ALGO_MD5 0
#define HACE_ALGO_SHA1 BIT(5)
#define HACE_ALGO_SHA224 BIT(6)
#define HACE_ALGO_SHA256 (BIT(4) | BIT(6))
#define HACE_ALGO_SHA512 (BIT(5) | BIT(6))
#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10))
#define HACE_SG_EN BIT(18)
#define HACE_ACCUM_EN BIT(8)
#define HACE_STS 0x1c
#define HACE_RSA_ISR BIT(13)
#define HACE_CRYPTO_ISR BIT(12)
#define HACE_HASH_ISR BIT(9)
#define HACE_RSA_BUSY BIT(2)
#define HACE_CRYPTO_BUSY BIT(1)
#define HACE_HASH_BUSY BIT(0)
#define HACE_HASH_SRC 0x20
#define HACE_HASH_DIGEST 0x24
#define HACE_HASH_KEY_BUFF 0x28
#define HACE_HASH_DATA_LEN 0x2c
#define HACE_HASH_CMD 0x30
#define HACE_HASH_SRC_HI 0x90
#define HACE_HASH_DIGEST_HI 0x94
#define HACE_HASH_KEY_BUFF_HI 0x98
/* Scatter-Gather Hash */
#define SG_LIST_LEN_LAST BIT(31)
struct AspeedSgList {
uint32_t len;
uint32_t addr;
} __attribute__ ((__packed__));
struct AspeedMasks {
uint32_t src;
uint32_t dest;
uint32_t key;
uint32_t len;
uint32_t src_hi;
uint32_t dest_hi;
uint32_t key_hi;
};
void aspeed_test_md5(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_sha256(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_sha384(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_sha512(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_sha384_sg(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_sha256_accum(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_sha384_accum(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_sha512_accum(const char *machine, const uint32_t base,
const uint64_t src_addr);
void aspeed_test_addresses(const char *machine, const uint32_t base,
const struct AspeedMasks *expected);
#endif /* TESTS_ASPEED_HACE_UTILS_H */
tests/qtest/aspeed_hace-test.c
+107 -484
View File
File diff suppressed because it is too large Load Diff
tests/qtest/aspeed_smc-test.c
+5
View File
@@ -228,5 +228,10 @@ int main(int argc, char **argv)
unlink(ast2500_evb_data.tmp_path);
unlink(ast2600_evb_data.tmp_path);
unlink(ast1030_evb_data.tmp_path);
g_free(palmetto_data.tmp_path);
g_free(ast2500_evb_data.tmp_path);
g_free(ast2600_evb_data.tmp_path);
g_free(ast1030_evb_data.tmp_path);
return ret;
}
tests/qtest/ast2700-hace-test.c
+98
View File
@@ -0,0 +1,98 @@
/*
* QTest testcase for the ASPEED Hash and Crypto Engine
*
* SPDX-License-Identifier: GPL-2.0-or-later
* Copyright (C) 2025 ASPEED Technology Inc.
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include "qemu/bitops.h"
#include "aspeed-hace-utils.h"
static const struct AspeedMasks as2700_masks = {
.src = 0x7fffffff,
.dest = 0x7ffffff8,
.key = 0x7ffffff8,
.len = 0x0fffffff,
.src_hi = 0x00000003,
.dest_hi = 0x00000003,
.key_hi = 0x00000003,
};
/* ast2700 */
static void test_md5_ast2700(void)
{
aspeed_test_md5("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_sha256_ast2700(void)
{
aspeed_test_sha256("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_sha256_sg_ast2700(void)
{
aspeed_test_sha256_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_sha384_ast2700(void)
{
aspeed_test_sha384("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_sha384_sg_ast2700(void)
{
aspeed_test_sha384_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_sha512_ast2700(void)
{
aspeed_test_sha512("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_sha512_sg_ast2700(void)
{
aspeed_test_sha512_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_sha256_accum_ast2700(void)
{
aspeed_test_sha256_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_sha384_accum_ast2700(void)
{
aspeed_test_sha384_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_sha512_accum_ast2700(void)
{
aspeed_test_sha512_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000);
}
static void test_addresses_ast2700(void)
{
aspeed_test_addresses("-machine ast2700a1-evb", 0x12070000, &as2700_masks);
}
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
qtest_add_func("ast2700/hace/addresses", test_addresses_ast2700);
qtest_add_func("ast2700/hace/sha512", test_sha512_ast2700);
qtest_add_func("ast2700/hace/sha384", test_sha384_ast2700);
qtest_add_func("ast2700/hace/sha256", test_sha256_ast2700);
qtest_add_func("ast2700/hace/md5", test_md5_ast2700);
qtest_add_func("ast2700/hace/sha512_sg", test_sha512_sg_ast2700);
qtest_add_func("ast2700/hace/sha384_sg", test_sha384_sg_ast2700);
qtest_add_func("ast2700/hace/sha256_sg", test_sha256_sg_ast2700);
qtest_add_func("ast2700/hace/sha512_accum", test_sha512_accum_ast2700);
qtest_add_func("ast2700/hace/sha384_accum", test_sha384_accum_ast2700);
qtest_add_func("ast2700/hace/sha256_accum", test_sha256_accum_ast2700);
return g_test_run();
}
tests/qtest/ast2700-smc-test.c
+1
View File
@@ -67,5 +67,6 @@ int main(int argc, char **argv)
qtest_quit(ast2700_evb_data.s);
unlink(ast2700_evb_data.tmp_path);
g_free(ast2700_evb_data.tmp_path);
return ret;
}
tests/qtest/meson.build
+8 -5
View File
@@ -212,11 +212,12 @@ qtests_npcm7xx = \
'npcm_gmac-test'] + \
(slirp.found() ? ['npcm7xx_emc-test'] : [])
qtests_aspeed = \
['aspeed_hace-test',
'aspeed_smc-test',
'aspeed_gpio-test']
['aspeed_gpio-test',
'aspeed_hace-test',
'aspeed_smc-test']
qtests_aspeed64 = \
['ast2700-gpio-test',
'ast2700-hace-test',
'ast2700-smc-test']
qtests_stm32l4x5 = \
@@ -361,6 +362,10 @@ if gnutls.found()
endif
qtests = {
'aspeed_hace-test': files('aspeed-hace-utils.c', 'aspeed_hace-test.c'),
'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'),
'ast2700-hace-test': files('aspeed-hace-utils.c', 'ast2700-hace-test.c'),
'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'),
'bios-tables-test': [io, 'boot-sector.c', 'acpi-utils.c', 'tpm-emu.c'],
'cdrom-test': files('boot-sector.c'),
'dbus-vmstate-test': files('migration/migration-qmp.c',
@@ -382,8 +387,6 @@ qtests = {
'virtio-net-failover': migration_files,
'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'),
'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'),
'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'),
}
if vnc.found()