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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201027-1' into staging

Browse Source 
target-arm queue:
 * raspi: add model of cprman clock manager
 * sbsa-ref: add an SBSA generic watchdog device
 * arm/trace: Fix hex printing
 * raspi: Add models of Pi 3 model A+, Pi Zero and Pi A+
 * hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly
 * Nuvoton NPCM7xx: Add USB, RNG, GPIO and watchdog support
 * hw/arm: fix min_cpus for xlnx-versal-virt platform
 * hw/arm/highbank: Silence warnings about missing fallthrough statements
 * linux-user: Support Aarch64 BTI
 * Armv7M systick: fix corner case bugs by rewriting to use ptimer

# gpg: Signature made Tue 27 Oct 2020 11:27:10 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20201027-1: (48 commits)
  hw/timer/armv7m_systick: Rewrite to use ptimers
  hw/core/ptimer: Support ptimer being disabled by timer callback
  hw/arm/sbsa-ref: add SBSA watchdog device
  hw/watchdog: Implement SBSA watchdog device
  hw/arm/bcm2835_peripherals: connect the UART clock
  hw/char/pl011: add a clock input
  hw/misc/bcm2835_cprman: add sane reset values to the registers
  hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
  hw/misc/bcm2835_cprman: implement clock mux behaviour
  hw/misc/bcm2835_cprman: add a clock mux skeleton implementation
  hw/misc/bcm2835_cprman: implement PLL channels behaviour
  hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation
  hw/misc/bcm2835_cprman: implement PLLs behaviour
  hw/misc/bcm2835_cprman: add a PLL skeleton implementation
  hw/arm/raspi: add a skeleton implementation of the CPRMAN
  hw/arm/raspi: fix CPRMAN base address
  hw/core/clock: trace clock values in Hz instead of ns
  hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro
  arm/trace: Fix hex printing
  hw/arm/raspi: Add the Raspberry Pi 3 model A+
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2020-10-29 11:40:04 +00:00
parent c044400914 32bd322a01
commit 802427bcda
64 changed files with 5461 additions and 279 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+1
View File
@@ -755,6 +755,7 @@ L: qemu-arm@nongnu.org
S: Supported
F: hw/*/npcm7xx*
F: include/hw/*/npcm7xx*
F: tests/qtest/npcm7xx*
F: pc-bios/npcm7xx_bootrom.bin
F: roms/vbootrom
docs/system/arm/nuvoton.rst
+3 -3
View File
@@ -38,11 +38,13 @@ Supported devices
* DDR4 memory controller (dummy interface indicating memory training is done)
* OTP controllers (no protection features)
* Flash Interface Unit (FIU; no protection features)
* Random Number Generator (RNG)
* USB host (USBH)
* GPIO controller
Missing devices
---------------
* GPIO controller
* LPC/eSPI host-to-BMC interface, including
* Keyboard and mouse controller interface (KBCI)
@@ -53,13 +55,11 @@ Missing devices
* eSPI slave interface
* Ethernet controllers (GMAC and EMC)
* USB host (USBH)
* USB device (USBD)
* SMBus controller (SMBF)
* Peripheral SPI controller (PSPI)
* Analog to Digital Converter (ADC)
* SD/MMC host
* Random Number Generator (RNG)
* PECI interface
* Pulse Width Modulation (PWM)
* Tachometer
hw/arm/Kconfig
+1
View File
@@ -212,6 +212,7 @@ config SBSA_REF
select PL031 # RTC
select PL061 # GPIO
select USB_EHCI_SYSBUS
select WDT_SBSA
config SABRELITE
bool
hw/arm/bcm2835_peripherals.c
+13 -2
View File
@@ -121,6 +121,9 @@ static void bcm2835_peripherals_init(Object *obj)
/* DWC2 */
object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB);
/* CPRMAN clock manager */
object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN);
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
OBJECT(&s->gpu_bus_mr));
}
@@ -160,6 +163,15 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
return;
}
/* CPRMAN clock manager */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) {
return;
}
memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0));
qdev_connect_clock_in(DEVICE(&s->uart0), "clk",
qdev_get_clock_out(DEVICE(&s->cprman), "uart-out"));
memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));
sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
@@ -354,8 +366,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
hw/arm/bcm2836.c
+120 -62
View File
@@ -17,46 +17,45 @@
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
struct BCM283XInfo {
typedef struct BCM283XClass {
/*< private >*/
DeviceClass parent_class;
/*< public >*/
const char *name;
const char *cpu_type;
unsigned core_count;
hwaddr peri_base; /* Peripheral base address seen by the CPU */
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
};
} BCM283XClass;
static const BCM283XInfo bcm283x_socs[] = {
{
.name = TYPE_BCM2836,
.cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"),
.peri_base = 0x3f000000,
.ctrl_base = 0x40000000,
.clusterid = 0xf,
},
#ifdef TARGET_AARCH64
{
.name = TYPE_BCM2837,
.cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
.peri_base = 0x3f000000,
.ctrl_base = 0x40000000,
.clusterid = 0x0,
},
#endif
};
#define BCM283X_CLASS(klass) \
OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
#define BCM283X_GET_CLASS(obj) \
OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
static Property bcm2836_enabled_cores_property =
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
static void bcm2836_init(Object *obj)
{
BCM283XState *s = BCM283X(obj);
BCM283XClass *bc = BCM283X_GET_CLASS(obj);
const BCM283XInfo *info = bc->info;
int n;
for (n = 0; n < BCM283X_NCPUS; n++) {
for (n = 0; n < bc->core_count; n++) {
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
info->cpu_type);
bc->cpu_type);
}
if (bc->core_count > 1) {
qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
}
object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
if (bc->ctrl_base) {
object_initialize_child(obj, "control", &s->control,
TYPE_BCM2836_CONTROL);
}
object_initialize_child(obj, "peripherals", &s->peripherals,
TYPE_BCM2835_PERIPHERALS);
@@ -66,13 +65,11 @@ static void bcm2836_init(Object *obj)
"vcram-size");
}
static void bcm2836_realize(DeviceState *dev, Error **errp)
static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
BCM283XClass *bc = BCM283X_GET_CLASS(dev);
const BCM283XInfo *info = bc->info;
Object *obj;
int n;
/* common peripherals from bcm2835 */
@@ -81,21 +78,52 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
return;
return false;
}
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
"sd-bus");
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
info->peri_base, 1);
bc->peri_base, 1);
return true;
}
static void bcm2835_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
if (!bcm283x_common_realize(dev, errp)) {
return;
}
if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
return;
}
/* Connect irq/fiq outputs from the interrupt controller. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
}
static void bcm2836_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
BCM283XClass *bc = BCM283X_GET_CLASS(dev);
int n;
if (!bcm283x_common_realize(dev, errp)) {
return;
}
/* bcm2836 interrupt controller (and mailboxes, etc.) */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
@@ -104,11 +132,11 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
for (n = 0; n < BCM283X_NCPUS; n++) {
/* TODO: this should be converted to a property of ARM_CPU */
s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n;
s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
/* set periphbase/CBAR value for CPU-local registers */
if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
info->peri_base, errp)) {
bc->peri_base, errp)) {
return;
}
@@ -142,47 +170,77 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
}
}
static Property bcm2836_props[] = {
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
BCM283X_NCPUS),
DEFINE_PROP_END_OF_LIST()
};
static void bcm283x_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->info = data;
dc->realize = bcm2836_realize;
device_class_set_props(dc, bcm2836_props);
/* Reason: Must be wired up in code (see raspi_init() function) */
dc->user_creatable = false;
}
static const TypeInfo bcm283x_type_info = {
.name = TYPE_BCM283X,
.parent = TYPE_DEVICE,
.instance_size = sizeof(BCM283XState),
.instance_init = bcm2836_init,
.class_size = sizeof(BCM283XClass),
.abstract = true,
static void bcm2835_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
bc->core_count = 1;
bc->peri_base = 0x20000000;
dc->realize = bcm2835_realize;
};
static void bcm2836_register_types(void)
static void bcm2836_class_init(ObjectClass *oc, void *data)
{
int i;
DeviceClass *dc = DEVICE_CLASS(oc);
BCM283XClass *bc = BCM283X_CLASS(oc);
type_register_static(&bcm283x_type_info);
for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
TypeInfo ti = {
.name = bcm283x_socs[i].name,
.parent = TYPE_BCM283X,
.class_init = bcm283x_class_init,
.class_data = (void *) &bcm283x_socs[i],
};
type_register(&ti);
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
bc->core_count = BCM283X_NCPUS;
bc->peri_base = 0x3f000000;
bc->ctrl_base = 0x40000000;
bc->clusterid = 0xf;
dc->realize = bcm2836_realize;
};
#ifdef TARGET_AARCH64
static void bcm2837_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
bc->core_count = BCM283X_NCPUS;
bc->peri_base = 0x3f000000;
bc->ctrl_base = 0x40000000;
bc->clusterid = 0x0;
dc->realize = bcm2836_realize;
};
#endif
static const TypeInfo bcm283x_types[] = {
{
.name = TYPE_BCM2835,
.parent = TYPE_BCM283X,
.class_init = bcm2835_class_init,
}, {
.name = TYPE_BCM2836,
.parent = TYPE_BCM283X,
.class_init = bcm2836_class_init,
#ifdef TARGET_AARCH64
}, {
.name = TYPE_BCM2837,
.parent = TYPE_BCM283X,
.class_init = bcm2837_class_init,
#endif
}, {
.name = TYPE_BCM283X,
.parent = TYPE_DEVICE,
.instance_size = sizeof(BCM283XState),
.instance_init = bcm2836_init,
.class_size = sizeof(BCM283XClass),
.class_init = bcm283x_class_init,
.abstract = true,
}
}
};
type_init(bcm2836_register_types)
DEFINE_TYPES(bcm283x_types)
hw/arm/highbank.c
+2
View File
@@ -92,10 +92,12 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
address_space_stl_notdirty(&address_space_memory,
SMP_BOOT_REG + 0x30, 0,
MEMTXATTRS_UNSPECIFIED, NULL);
/* fallthrough */
case 3:
address_space_stl_notdirty(&address_space_memory,
SMP_BOOT_REG + 0x20, 0,
MEMTXATTRS_UNSPECIFIED, NULL);
/* fallthrough */
case 2:
address_space_stl_notdirty(&address_space_memory,
SMP_BOOT_REG + 0x10, 0,
hw/arm/npcm7xx.c
+123 -3
View File
@@ -44,6 +44,11 @@
#define NPCM7XX_GCR_BA (0xf0800000)
#define NPCM7XX_CLK_BA (0xf0801000)
#define NPCM7XX_MC_BA (0xf0824000)
#define NPCM7XX_RNG_BA (0xf000b000)
/* USB Host modules */
#define NPCM7XX_EHCI_BA (0xf0806000)
#define NPCM7XX_OHCI_BA (0xf0807000)
/* Internal AHB SRAM */
#define NPCM7XX_RAM3_BA (0xc0008000)
@@ -86,6 +91,19 @@ enum NPCM7xxInterrupt {
NPCM7XX_TIMER12_IRQ,
NPCM7XX_TIMER13_IRQ,
NPCM7XX_TIMER14_IRQ,
NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
NPCM7XX_EHCI_IRQ = 61,
NPCM7XX_OHCI_IRQ = 62,
NPCM7XX_GPIO0_IRQ = 116,
NPCM7XX_GPIO1_IRQ,
NPCM7XX_GPIO2_IRQ,
NPCM7XX_GPIO3_IRQ,
NPCM7XX_GPIO4_IRQ,
NPCM7XX_GPIO5_IRQ,
NPCM7XX_GPIO6_IRQ,
NPCM7XX_GPIO7_IRQ,
};
/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
@@ -120,6 +138,55 @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
0xb8000000, /* CS3 */
};
static const struct {
hwaddr regs_addr;
uint32_t unconnected_pins;
uint32_t reset_pu;
uint32_t reset_pd;
uint32_t reset_osrc;
uint32_t reset_odsc;
} npcm7xx_gpio[] = {
{
.regs_addr = 0xf0010000,
.reset_pu = 0xff03ffff,
.reset_pd = 0x00fc0000,
}, {
.regs_addr = 0xf0011000,
.unconnected_pins = 0x0000001e,
.reset_pu = 0xfefffe07,
.reset_pd = 0x010001e0,
}, {
.regs_addr = 0xf0012000,
.reset_pu = 0x780fffff,
.reset_pd = 0x07f00000,
.reset_odsc = 0x00700000,
}, {
.regs_addr = 0xf0013000,
.reset_pu = 0x00fc0000,
.reset_pd = 0xff000000,
}, {
.regs_addr = 0xf0014000,
.reset_pu = 0xffffffff,
}, {
.regs_addr = 0xf0015000,
.reset_pu = 0xbf83f801,
.reset_pd = 0x007c0000,
.reset_osrc = 0x000000f1,
.reset_odsc = 0x3f9f80f1,
}, {
.regs_addr = 0xf0016000,
.reset_pu = 0xfc00f801,
.reset_pd = 0x000007fe,
.reset_odsc = 0x00000800,
}, {
.regs_addr = 0xf0017000,
.unconnected_pins = 0xffffff00,
.reset_pu = 0x0000007f,
.reset_osrc = 0x0000007f,
.reset_odsc = 0x0000007f,
},
};
static const struct {
const char *name;
hwaddr regs_addr;
@@ -253,11 +320,19 @@ static void npcm7xx_init(Object *obj)
object_initialize_child(obj, "otp2", &s->fuse_array,
TYPE_NPCM7XX_FUSE_ARRAY);
object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
}
for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
}
object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
@@ -353,6 +428,15 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
qemu_irq irq = npcm7xx_irq(s, first_irq + j);
sysbus_connect_irq(sbd, j, irq);
}
/* IRQ for watchdogs */
sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
/* GPIO that connects clk module with watchdog */
qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
qdev_get_gpio_in_named(DEVICE(&s->clk),
NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
}
/* UART0..3 (16550 compatible) */
@@ -362,6 +446,45 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
serial_hd(i), DEVICE_LITTLE_ENDIAN);
}
/* Random Number Generator. Cannot fail. */
sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
/* GPIO modules. Cannot fail. */
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio));
for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
Object *obj = OBJECT(&s->gpio[i]);
object_property_set_uint(obj, "reset-pullup",
npcm7xx_gpio[i].reset_pu, &error_abort);
object_property_set_uint(obj, "reset-pulldown",
npcm7xx_gpio[i].reset_pd, &error_abort);
object_property_set_uint(obj, "reset-osrc",
npcm7xx_gpio[i].reset_osrc, &error_abort);
object_property_set_uint(obj, "reset-odsc",
npcm7xx_gpio[i].reset_odsc, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
}
/* USB Host */
object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
&error_abort);
object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
/*
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
* specified, but this is a programming error.
@@ -400,7 +523,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
create_unimplemented_device("npcm7xx.rng", 0xf000b000, 4 * KiB);
create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
@@ -447,8 +569,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB);
create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB);
create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
hw/arm/raspi.c
+41
View File
@@ -70,6 +70,7 @@ FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
FIELD(REV_CODE, STYLE, 23, 1);
typedef enum RaspiProcessorId {
PROCESSOR_ID_BCM2835 = 0,
PROCESSOR_ID_BCM2836 = 1,
PROCESSOR_ID_BCM2837 = 2,
} RaspiProcessorId;
@@ -78,6 +79,7 @@ static const struct {
const char *type;
int cores_count;
} soc_property[] = {
[PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1},
[PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
[PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
};
@@ -317,6 +319,24 @@ static void raspi_machine_class_common_init(MachineClass *mc,
mc->default_ram_id = "ram";
};
static void raspi0_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
rmc->board_rev = 0x920092; /* Revision 1.2 */
raspi_machine_class_common_init(mc, rmc->board_rev);
};
static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
rmc->board_rev = 0x900021; /* Revision 1.1 */
raspi_machine_class_common_init(mc, rmc->board_rev);
};
static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -328,6 +348,15 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
};
#ifdef TARGET_AARCH64
static void raspi3ap_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
rmc->board_rev = 0x9020e0; /* Revision 1.0 */
raspi_machine_class_common_init(mc, rmc->board_rev);
};
static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -341,10 +370,22 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo raspi_machine_types[] = {
{
.name = MACHINE_TYPE_NAME("raspi0"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi0_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("raspi1ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi1ap_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("raspi2b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("raspi3ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3ap_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("raspi3b"),
.parent = TYPE_RASPI_MACHINE,
hw/arm/sbsa-ref.c
+23
View File
@@ -40,6 +40,7 @@
#include "hw/qdev-properties.h"
#include "hw/usb.h"
#include "hw/char/pl011.h"
#include "hw/watchdog/sbsa_gwdt.h"
#include "net/net.h"
#include "qom/object.h"
@@ -64,6 +65,9 @@ enum {
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
SBSA_SECURE_EC,
SBSA_GWDT,
SBSA_GWDT_REFRESH,
SBSA_GWDT_CONTROL,
SBSA_SMMU,
SBSA_UART,
SBSA_RTC,
@@ -104,6 +108,8 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
[SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
[SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
[SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
[SBSA_UART] = { 0x60000000, 0x00001000 },
[SBSA_RTC] = { 0x60010000, 0x00001000 },
[SBSA_GPIO] = { 0x60020000, 0x00001000 },
@@ -134,6 +140,7 @@ static const int sbsa_ref_irqmap[] = {
[SBSA_AHCI] = 10,
[SBSA_EHCI] = 11,
[SBSA_SMMU] = 12, /* ... to 15 */
[SBSA_GWDT] = 16,
};
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
@@ -448,6 +455,20 @@ static void create_rtc(const SBSAMachineState *sms)
sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
}
static void create_wdt(const SBSAMachineState *sms)
{
hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base;
hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
int irq = sbsa_ref_irqmap[SBSA_GWDT];
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, rbase);
sysbus_mmio_map(s, 1, cbase);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
}
static DeviceState *gpio_key_dev;
static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
{
@@ -731,6 +752,8 @@ static void sbsa_ref_init(MachineState *machine)
create_rtc(sms);
create_wdt(sms);
create_gpio(sms);
create_ahci(sms);
hw/arm/smmuv3.c
+1
View File
@@ -1440,6 +1440,7 @@ static const VMStateDescription vmstate_smmuv3 = {
.name = "smmuv3",
.version_id = 1,
.minimum_version_id = 1,
.priority = MIG_PRI_IOMMU,
.fields = (VMStateField[]) {
VMSTATE_UINT32(features, SMMUv3State),
VMSTATE_UINT8(sid_size, SMMUv3State),
hw/arm/trace-events
+1 -1
View File
@@ -41,7 +41,7 @@ smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
smmuv3_decode_cd(uint32_t oas) "oas=%d"
smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d"
smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d"
smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"
smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"
hw/arm/xlnx-versal-virt.c
+1
View File
@@ -561,6 +561,7 @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
mc->desc = "Xilinx Versal Virtual development board";
mc->init = versal_virt_init;
mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
mc->no_cdrom = true;
hw/char/pl011.c
+45
View File
@@ -22,6 +22,7 @@
#include "hw/char/pl011.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "hw/qdev-clock.h"
#include "migration/vmstate.h"
#include "chardev/char-fe.h"
#include "qemu/log.h"
@@ -169,6 +170,25 @@ static void pl011_set_read_trigger(PL011State *s)
s->read_trigger = 1;
}
static unsigned int pl011_get_baudrate(const PL011State *s)
{
uint64_t clk;
if (s->fbrd == 0) {
return 0;
}
clk = clock_get_hz(s->clk);
return (clk / ((s->ibrd << 6) + s->fbrd)) << 2;
}
static void pl011_trace_baudrate_change(const PL011State *s)
{
trace_pl011_baudrate_change(pl011_get_baudrate(s),
clock_get_hz(s->clk),
s->ibrd, s->fbrd);
}
static void pl011_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
@@ -198,9 +218,11 @@ static void pl011_write(void *opaque, hwaddr offset,
break;
case 9: /* UARTIBRD */
s->ibrd = value;
pl011_trace_baudrate_change(s);
break;
case 10: /* UARTFBRD */
s->fbrd = value;
pl011_trace_baudrate_change(s);
break;
case 11: /* UARTLCR_H */
/* Reset the FIFO state on FIFO enable or disable */
@@ -286,12 +308,29 @@ static void pl011_event(void *opaque, QEMUChrEvent event)
pl011_put_fifo(opaque, 0x400);
}
static void pl011_clock_update(void *opaque)
{
PL011State *s = PL011(opaque);
pl011_trace_baudrate_change(s);
}
static const MemoryRegionOps pl011_ops = {
.read = pl011_read,
.write = pl011_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_pl011_clock = {
.name = "pl011/clock",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_CLOCK(clk, PL011State),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_pl011 = {
.name = "pl011",
.version_id = 2,
@@ -314,6 +353,10 @@ static const VMStateDescription vmstate_pl011 = {
VMSTATE_INT32(read_count, PL011State),
VMSTATE_INT32(read_trigger, PL011State),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * []) {
&vmstate_pl011_clock,
NULL
}
};
@@ -334,6 +377,8 @@ static void pl011_init(Object *obj)
sysbus_init_irq(sbd, &s->irq[i]);
}
s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s);
s->read_trigger = 1;
s->ifl = 0x12;
s->cr = 0x300;
hw/char/trace-events
+1
View File
@@ -65,6 +65,7 @@ pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d"
pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d"
pl011_put_fifo_full(void) "FIFO now full, RXFF set"
pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")"
# cmsdk-apb-uart.c
cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
hw/core/clock.c
+3 -3
View File
@@ -54,8 +54,8 @@ bool clock_set(Clock *clk, uint64_t period)
if (clk->period == period) {
return false;
}
trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
CLOCK_PERIOD_TO_NS(period));
trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period),
CLOCK_PERIOD_TO_HZ(period));
clk->period = period;
return true;
@@ -69,7 +69,7 @@ static void clock_propagate_period(Clock *clk, bool call_callbacks)
if (child->period != clk->period) {
child->period = clk->period;
trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
CLOCK_PERIOD_TO_NS(clk->period),
CLOCK_PERIOD_TO_HZ(clk->period),
call_callbacks);
if (call_callbacks && child->callback) {
child->callback(child->callback_opaque);
hw/core/ptimer.c
+4
View File
@@ -117,6 +117,10 @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
}
if (delta == 0) {
if (s->enabled == 0) {
/* trigger callback disabled the timer already */
return;
}
if (!qtest_enabled()) {
fprintf(stderr, "Timer with delta zero, disabling\n");
}
hw/core/trace-events
+2 -2
View File
@@ -31,6 +31,6 @@ resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)"
# clock.c
clock_set_source(const char *clk, const char *src) "'%s', src='%s'"
clock_disconnect(const char *clk) "'%s'"
clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', ns=%"PRIu64"->%"PRIu64
clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', %"PRIu64"Hz->%"PRIu64"Hz"
clock_propagate(const char *clk) "'%s'"
clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s', src='%s', ns=%"PRIu64", cb=%d"
clock_update(const char *clk, const char *src, uint64_t hz, int cb) "'%s', src='%s', val=%"PRIu64"Hz cb=%d"
hw/gpio/meson.build
+1
View File
@@ -6,6 +6,7 @@ softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c'))
softmmu_ss.add(when: 'CONFIG_ZAURUS', if_true: files('zaurus.c'))
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpio.c'))
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_gpio.c'))
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
hw/gpio/npcm7xx_gpio.c
+424
View File
@@ -0,0 +1,424 @@
/*
* Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "qemu/osdep.h"
#include "hw/gpio/npcm7xx_gpio.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/units.h"
#include "trace.h"
/* 32-bit register indices. */
enum NPCM7xxGPIORegister {
NPCM7XX_GPIO_TLOCK1,
NPCM7XX_GPIO_DIN,
NPCM7XX_GPIO_POL,
NPCM7XX_GPIO_DOUT,
NPCM7XX_GPIO_OE,
NPCM7XX_GPIO_OTYP,
NPCM7XX_GPIO_MP,
NPCM7XX_GPIO_PU,
NPCM7XX_GPIO_PD,
NPCM7XX_GPIO_DBNC,
NPCM7XX_GPIO_EVTYP,
NPCM7XX_GPIO_EVBE,
NPCM7XX_GPIO_OBL0,
NPCM7XX_GPIO_OBL1,
NPCM7XX_GPIO_OBL2,
NPCM7XX_GPIO_OBL3,
NPCM7XX_GPIO_EVEN,
NPCM7XX_GPIO_EVENS,
NPCM7XX_GPIO_EVENC,
NPCM7XX_GPIO_EVST,
NPCM7XX_GPIO_SPLCK,
NPCM7XX_GPIO_MPLCK,
NPCM7XX_GPIO_IEM,
NPCM7XX_GPIO_OSRC,
NPCM7XX_GPIO_ODSC,
NPCM7XX_GPIO_DOS = 0x68 / sizeof(uint32_t),
NPCM7XX_GPIO_DOC,
NPCM7XX_GPIO_OES,
NPCM7XX_GPIO_OEC,
NPCM7XX_GPIO_TLOCK2 = 0x7c / sizeof(uint32_t),
NPCM7XX_GPIO_REGS_END,
};
#define NPCM7XX_GPIO_REGS_SIZE (4 * KiB)
#define NPCM7XX_GPIO_LOCK_MAGIC1 (0xc0defa73)
#define NPCM7XX_GPIO_LOCK_MAGIC2 (0xc0de1248)
static void npcm7xx_gpio_update_events(NPCM7xxGPIOState *s, uint32_t din_diff)
{
uint32_t din_new = s->regs[NPCM7XX_GPIO_DIN];
/* Trigger on high level */
s->regs[NPCM7XX_GPIO_EVST] |= din_new & ~s->regs[NPCM7XX_GPIO_EVTYP];
/* Trigger on both edges */
s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & s->regs[NPCM7XX_GPIO_EVTYP]
& s->regs[NPCM7XX_GPIO_EVBE]);
/* Trigger on rising edge */
s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & din_new
& s->regs[NPCM7XX_GPIO_EVTYP]);
trace_npcm7xx_gpio_update_events(DEVICE(s)->canonical_path,
s->regs[NPCM7XX_GPIO_EVST],
s->regs[NPCM7XX_GPIO_EVEN]);
qemu_set_irq(s->irq, !!(s->regs[NPCM7XX_GPIO_EVST]
& s->regs[NPCM7XX_GPIO_EVEN]));
}
static void npcm7xx_gpio_update_pins(NPCM7xxGPIOState *s, uint32_t diff)
{
uint32_t drive_en;
uint32_t drive_lvl;
uint32_t not_driven;
uint32_t undefined;
uint32_t pin_diff;
uint32_t din_old;
/* Calculate level of each pin driven by GPIO controller. */
drive_lvl = s->regs[NPCM7XX_GPIO_DOUT] ^ s->regs[NPCM7XX_GPIO_POL];
/* If OTYP=1, only drive low (open drain) */
drive_en = s->regs[NPCM7XX_GPIO_OE] & ~(s->regs[NPCM7XX_GPIO_OTYP]
& drive_lvl);
/*
* If a pin is driven to opposite levels by the GPIO controller and the
* external driver, the result is undefined.
*/
undefined = drive_en & s->ext_driven & (drive_lvl ^ s->ext_level);
if (undefined) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: pins have multiple drivers: 0x%" PRIx32 "\n",
DEVICE(s)->canonical_path, undefined);
}
not_driven = ~(drive_en | s->ext_driven);
pin_diff = s->pin_level;
/* Set pins to externally driven level. */
s->pin_level = s->ext_level & s->ext_driven;
/* Set internally driven pins, ignoring any conflicts. */
s->pin_level |= drive_lvl & drive_en;
/* Pull up undriven pins with internal pull-up enabled. */
s->pin_level |= not_driven & s->regs[NPCM7XX_GPIO_PU];
/* Pins not driven, pulled up or pulled down are undefined */
undefined |= not_driven & ~(s->regs[NPCM7XX_GPIO_PU]
| s->regs[NPCM7XX_GPIO_PD]);
/* If any pins changed state, update the outgoing GPIOs. */
pin_diff ^= s->pin_level;
pin_diff |= undefined & diff;
if (pin_diff) {
int i;
for (i = 0; i < NPCM7XX_GPIO_NR_PINS; i++) {
uint32_t mask = BIT(i);
if (pin_diff & mask) {
int level = (undefined & mask) ? -1 : !!(s->pin_level & mask);
trace_npcm7xx_gpio_set_output(DEVICE(s)->canonical_path,
i, level);
qemu_set_irq(s->output[i], level);
}
}
}
/* Calculate new value of DIN after masking and polarity setting. */
din_old = s->regs[NPCM7XX_GPIO_DIN];
s->regs[NPCM7XX_GPIO_DIN] = ((s->pin_level & s->regs[NPCM7XX_GPIO_IEM])
^ s->regs[NPCM7XX_GPIO_POL]);
/* See if any new events triggered because of all this. */
npcm7xx_gpio_update_events(s, din_old ^ s->regs[NPCM7XX_GPIO_DIN]);
}
static bool npcm7xx_gpio_is_locked(NPCM7xxGPIOState *s)
{
return s->regs[NPCM7XX_GPIO_TLOCK1] == 1;
}
static uint64_t npcm7xx_gpio_regs_read(void *opaque, hwaddr addr,
unsigned int size)
{
hwaddr reg = addr / sizeof(uint32_t);
NPCM7xxGPIOState *s = opaque;
uint64_t value = 0;
switch (reg) {
case NPCM7XX_GPIO_TLOCK1 ... NPCM7XX_GPIO_EVEN:
case NPCM7XX_GPIO_EVST ... NPCM7XX_GPIO_ODSC:
value = s->regs[reg];
break;
case NPCM7XX_GPIO_EVENS ... NPCM7XX_GPIO_EVENC:
case NPCM7XX_GPIO_DOS ... NPCM7XX_GPIO_TLOCK2:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: read from write-only register 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: read from invalid offset 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
}
trace_npcm7xx_gpio_read(DEVICE(s)->canonical_path, addr, value);
return value;
}
static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
unsigned int size)
{
hwaddr reg = addr / sizeof(uint32_t);
NPCM7xxGPIOState *s = opaque;
uint32_t value = v;
uint32_t diff;
trace_npcm7xx_gpio_write(DEVICE(s)->canonical_path, addr, v);
if (npcm7xx_gpio_is_locked(s)) {
switch (reg) {
case NPCM7XX_GPIO_TLOCK1:
if (s->regs[NPCM7XX_GPIO_TLOCK2] == NPCM7XX_GPIO_LOCK_MAGIC2 &&
value == NPCM7XX_GPIO_LOCK_MAGIC1) {
s->regs[NPCM7XX_GPIO_TLOCK1] = 0;
s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
}
break;
case NPCM7XX_GPIO_TLOCK2:
s->regs[reg] = value;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to locked register @ 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
}
return;
}
diff = s->regs[reg] ^ value;
switch (reg) {
case NPCM7XX_GPIO_TLOCK1:
case NPCM7XX_GPIO_TLOCK2:
s->regs[NPCM7XX_GPIO_TLOCK1] = 1;
s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
break;
case NPCM7XX_GPIO_DIN:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
case NPCM7XX_GPIO_POL:
case NPCM7XX_GPIO_DOUT:
case NPCM7XX_GPIO_OE:
case NPCM7XX_GPIO_OTYP:
case NPCM7XX_GPIO_PU:
case NPCM7XX_GPIO_PD:
case NPCM7XX_GPIO_IEM:
s->regs[reg] = value;
npcm7xx_gpio_update_pins(s, diff);
break;
case NPCM7XX_GPIO_DOS:
s->regs[NPCM7XX_GPIO_DOUT] |= value;
npcm7xx_gpio_update_pins(s, value);
break;
case NPCM7XX_GPIO_DOC:
s->regs[NPCM7XX_GPIO_DOUT] &= ~value;
npcm7xx_gpio_update_pins(s, value);
break;
case NPCM7XX_GPIO_OES:
s->regs[NPCM7XX_GPIO_OE] |= value;
npcm7xx_gpio_update_pins(s, value);
break;
case NPCM7XX_GPIO_OEC:
s->regs[NPCM7XX_GPIO_OE] &= ~value;
npcm7xx_gpio_update_pins(s, value);
break;
case NPCM7XX_GPIO_EVTYP:
case NPCM7XX_GPIO_EVBE:
case NPCM7XX_GPIO_EVEN:
s->regs[reg] = value;
npcm7xx_gpio_update_events(s, 0);
break;
case NPCM7XX_GPIO_EVENS:
s->regs[NPCM7XX_GPIO_EVEN] |= value;
npcm7xx_gpio_update_events(s, 0);
break;
case NPCM7XX_GPIO_EVENC:
s->regs[NPCM7XX_GPIO_EVEN] &= ~value;
npcm7xx_gpio_update_events(s, 0);
break;
case NPCM7XX_GPIO_EVST:
s->regs[reg] &= ~value;
npcm7xx_gpio_update_events(s, 0);
break;
case NPCM7XX_GPIO_MP:
case NPCM7XX_GPIO_DBNC:
case NPCM7XX_GPIO_OSRC:
case NPCM7XX_GPIO_ODSC:
/* Nothing to do; just store the value. */
s->regs[reg] = value;
break;
case NPCM7XX_GPIO_OBL0:
case NPCM7XX_GPIO_OBL1:
case NPCM7XX_GPIO_OBL2:
case NPCM7XX_GPIO_OBL3:
s->regs[reg] = value;
qemu_log_mask(LOG_UNIMP, "%s: Blinking is not implemented\n",
__func__);
break;
case NPCM7XX_GPIO_SPLCK:
case NPCM7XX_GPIO_MPLCK:
qemu_log_mask(LOG_UNIMP, "%s: Per-pin lock is not implemented\n",
__func__);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to invalid offset 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
}
}
static const MemoryRegionOps npcm7xx_gpio_regs_ops = {
.read = npcm7xx_gpio_regs_read,
.write = npcm7xx_gpio_regs_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
.unaligned = false,
},
};
static void npcm7xx_gpio_set_input(void *opaque, int line, int level)
{
NPCM7xxGPIOState *s = opaque;
trace_npcm7xx_gpio_set_input(DEVICE(s)->canonical_path, line, level);
g_assert(line >= 0 && line < NPCM7XX_GPIO_NR_PINS);
s->ext_driven = deposit32(s->ext_driven, line, 1, level >= 0);
s->ext_level = deposit32(s->ext_level, line, 1, level > 0);
npcm7xx_gpio_update_pins(s, BIT(line));
}
static void npcm7xx_gpio_enter_reset(Object *obj, ResetType type)
{
NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
memset(s->regs, 0, sizeof(s->regs));
s->regs[NPCM7XX_GPIO_PU] = s->reset_pu;
s->regs[NPCM7XX_GPIO_PD] = s->reset_pd;
s->regs[NPCM7XX_GPIO_OSRC] = s->reset_osrc;
s->regs[NPCM7XX_GPIO_ODSC] = s->reset_odsc;
}
static void npcm7xx_gpio_hold_reset(Object *obj)
{
NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
npcm7xx_gpio_update_pins(s, -1);
}
static void npcm7xx_gpio_init(Object *obj)
{
NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
DeviceState *dev = DEVICE(obj);
memory_region_init_io(&s->mmio, obj, &npcm7xx_gpio_regs_ops, s,
"regs", NPCM7XX_GPIO_REGS_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
qdev_init_gpio_in(dev, npcm7xx_gpio_set_input, NPCM7XX_GPIO_NR_PINS);
qdev_init_gpio_out(dev, s->output, NPCM7XX_GPIO_NR_PINS);
}
static const VMStateDescription vmstate_npcm7xx_gpio = {
.name = "npcm7xx-gpio",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT32(pin_level, NPCM7xxGPIOState),
VMSTATE_UINT32(ext_level, NPCM7xxGPIOState),
VMSTATE_UINT32(ext_driven, NPCM7xxGPIOState),
VMSTATE_UINT32_ARRAY(regs, NPCM7xxGPIOState, NPCM7XX_GPIO_NR_REGS),
VMSTATE_END_OF_LIST(),
},
};
static Property npcm7xx_gpio_properties[] = {
/* Bit n set => pin n has pullup enabled by default. */
DEFINE_PROP_UINT32("reset-pullup", NPCM7xxGPIOState, reset_pu, 0),
/* Bit n set => pin n has pulldown enabled by default. */
DEFINE_PROP_UINT32("reset-pulldown", NPCM7xxGPIOState, reset_pd, 0),
/* Bit n set => pin n has high slew rate by default. */
DEFINE_PROP_UINT32("reset-osrc", NPCM7xxGPIOState, reset_osrc, 0),
/* Bit n set => pin n has high drive strength by default. */
DEFINE_PROP_UINT32("reset-odsc", NPCM7xxGPIOState, reset_odsc, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void npcm7xx_gpio_class_init(ObjectClass *klass, void *data)
{
ResettableClass *reset = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
QEMU_BUILD_BUG_ON(NPCM7XX_GPIO_REGS_END > NPCM7XX_GPIO_NR_REGS);
dc->desc = "NPCM7xx GPIO Controller";
dc->vmsd = &vmstate_npcm7xx_gpio;
reset->phases.enter = npcm7xx_gpio_enter_reset;
reset->phases.hold = npcm7xx_gpio_hold_reset;
device_class_set_props(dc, npcm7xx_gpio_properties);
}
static const TypeInfo npcm7xx_gpio_types[] = {
{
.name = TYPE_NPCM7XX_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCM7xxGPIOState),
.class_init = npcm7xx_gpio_class_init,
.instance_init = npcm7xx_gpio_init,
},
};
DEFINE_TYPES(npcm7xx_gpio_types);
hw/gpio/trace-events
+7
View File
@@ -1,5 +1,12 @@
# See docs/devel/tracing.txt for syntax documentation.
# npcm7xx_gpio.c
npcm7xx_gpio_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
npcm7xx_gpio_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
npcm7xx_gpio_set_input(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32
npcm7xx_gpio_set_output(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32
npcm7xx_gpio_update_events(const char *id, uint32_t evst, uint32_t even) "%s evst: 0x%08" PRIx32 " even: 0x%08" PRIx32
# nrf51_gpio.c
nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64

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