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target/arm: Use tlb_set_page_full

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Adjust GetPhysAddrResult to fill in CPUTLBEntryFull,
so that it may be passed directly to tlb_set_page_full.

The change is large, but mostly mechanical.  The major
non-mechanical change is page_size -> lg_page_size.
Most of the time this is obvious, and is related to
TARGET_PAGE_BITS.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221001162318.153420-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
2022-10-10 14:52:25 +01:00
committed by Peter Maydell
parent 5b74f9b4ed
commit 7fa7ea8f48
5 changed files with 111 additions and 114 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/arm/helper.c
+6 -6
View File
@@ -3323,8 +3323,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
/* Create a 64-bit PAR */
par64 = (1 << 11); /* LPAE bit always set */
if (!ret) {
par64 |= res.phys & ~0xfffULL;
if (!res.attrs.secure) {
par64 |= res.f.phys_addr & ~0xfffULL;
if (!res.f.attrs.secure) {
par64 |= (1 << 9); /* NS */
}
par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
@@ -3348,13 +3348,13 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
*/
if (!ret) {
/* We do not set any attribute bits in the PAR */
if (res.page_size == (1 << 24)
if (res.f.lg_page_size == 24
&& arm_feature(env, ARM_FEATURE_V7)) {
par64 = (res.phys & 0xff000000) | (1 << 1);
par64 = (res.f.phys_addr & 0xff000000) | (1 << 1);
} else {
par64 = res.phys & 0xfffff000;
par64 = res.f.phys_addr & 0xfffff000;
}
if (!res.attrs.secure) {
if (!res.f.attrs.secure) {
par64 |= (1 << 9); /* NS */
}
} else {
target/arm/internals.h
+1 -4
View File
@@ -1071,10 +1071,7 @@ typedef struct ARMCacheAttrs {
/* Fields that are valid upon success. */
typedef struct GetPhysAddrResult {
hwaddr phys;
target_ulong page_size;
int prot;
MemTxAttrs attrs;
CPUTLBEntryFull f;
ARMCacheAttrs cacheattrs;
} GetPhysAddrResult;
target/arm/m_helper.c
+10 -10
View File
@@ -223,8 +223,8 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
}
goto pend_fault;
}
address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value,
res.attrs, &txres);
address_space_stl_le(arm_addressspace(cs, res.f.attrs), res.f.phys_addr,
value, res.f.attrs, &txres);
if (txres != MEMTX_OK) {
/* BusFault trying to write the data */
if (mode == STACK_LAZYFP) {
@@ -298,8 +298,8 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
goto pend_fault;
}
value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
res.attrs, &txres);
value = address_space_ldl(arm_addressspace(cs, res.f.attrs),
res.f.phys_addr, res.f.attrs, &txres);
if (txres != MEMTX_OK) {
/* BusFault trying to read the data */
qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n");
@@ -2022,8 +2022,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
return false;
}
*insn = address_space_lduw_le(arm_addressspace(cs, res.attrs), res.phys,
res.attrs, &txres);
*insn = address_space_lduw_le(arm_addressspace(cs, res.f.attrs),
res.f.phys_addr, res.f.attrs, &txres);
if (txres != MEMTX_OK) {
env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
@@ -2069,8 +2069,8 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
}
return false;
}
value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
res.attrs, &txres);
value = address_space_ldl(arm_addressspace(cs, res.f.attrs),
res.f.phys_addr, res.f.attrs, &txres);
if (txres != MEMTX_OK) {
/* BusFault trying to read the data */
qemu_log_mask(CPU_LOG_INT,
@@ -2817,8 +2817,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
} else {
mrvalid = true;
}
r = res.prot & PAGE_READ;
rw = res.prot & PAGE_WRITE;
r = res.f.prot & PAGE_READ;
rw = res.f.prot & PAGE_WRITE;
} else {
r = false;
rw = false;
target/arm/ptw.c
+90 -89
View File
File diff suppressed because it is too large Load Diff
target/arm/tlb_helper.c
+4 -5
View File
@@ -227,17 +227,16 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
* target page size are handled specially, so for those we
* pass in the exact addresses.
*/
if (res.page_size >= TARGET_PAGE_SIZE) {
res.phys &= TARGET_PAGE_MASK;
if (res.f.lg_page_size >= TARGET_PAGE_BITS) {
res.f.phys_addr &= TARGET_PAGE_MASK;
address &= TARGET_PAGE_MASK;
}
/* Notice and record tagged memory. */
if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
arm_tlb_mte_tagged(&res.attrs) = true;
arm_tlb_mte_tagged(&res.f.attrs) = true;
}
tlb_set_page_with_attrs(cs, address, res.phys, res.attrs,
res.prot, mmu_idx, res.page_size);
tlb_set_page_full(cs, mmu_idx, address, &res.f);
return true;
} else if (probe) {
return false;