mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
hw/block/nvme: support multiple namespaces
This adds support for multiple namespaces by introducing a new 'nvme-ns'
device model. The nvme device creates a bus named from the device name
('id'). The nvme-ns devices then connect to this and registers
themselves with the nvme device.
This changes how an nvme device is created. Example with two namespaces:
-drive file=nvme0n1.img,if=none,id=disk1
-drive file=nvme0n2.img,if=none,id=disk2
-device nvme,serial=deadbeef,id=nvme0
-device nvme-ns,drive=disk1,bus=nvme0,nsid=1
-device nvme-ns,drive=disk2,bus=nvme0,nsid=2
The drive property is kept on the nvme device to keep the change
backward compatible, but the property is now optional. Specifying a
drive for the nvme device will always create the namespace with nsid 1.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com>
This commit is contained in:
Klaus Jensen
@@ -13,7 +13,7 @@ softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c'))
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softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c'))
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softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c'))
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softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('tc58128.c'))
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softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c'))
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softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c', 'nvme-ns.c'))
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specific_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-blk.c'))
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specific_ss.add(when: 'CONFIG_VHOST_USER_BLK', if_true: files('vhost-user-blk.c'))
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@@ -0,0 +1,167 @@
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/*
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* QEMU NVM Express Virtual Namespace
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*
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* Copyright (c) 2019 CNEX Labs
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* Copyright (c) 2020 Samsung Electronics
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*
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* Authors:
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* Klaus Jensen <k.jensen@samsung.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/cutils.h"
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#include "qemu/log.h"
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#include "hw/block/block.h"
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#include "hw/pci/pci.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/block-backend.h"
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#include "qapi/error.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-core.h"
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#include "nvme.h"
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#include "nvme-ns.h"
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static void nvme_ns_init(NvmeNamespace *ns)
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{
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NvmeIdNs *id_ns = &ns->id_ns;
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if (blk_get_flags(ns->blkconf.blk) & BDRV_O_UNMAP) {
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ns->id_ns.dlfeat = 0x9;
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}
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id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
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id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(ns));
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/* no thin provisioning */
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id_ns->ncap = id_ns->nsze;
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id_ns->nuse = id_ns->ncap;
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}
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static int nvme_ns_init_blk(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
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{
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if (!blkconf_blocksizes(&ns->blkconf, errp)) {
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return -1;
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}
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if (!blkconf_apply_backend_options(&ns->blkconf,
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blk_is_read_only(ns->blkconf.blk),
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false, errp)) {
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return -1;
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}
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ns->size = blk_getlength(ns->blkconf.blk);
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if (ns->size < 0) {
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error_setg_errno(errp, -ns->size, "could not get blockdev size");
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return -1;
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}
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if (blk_enable_write_cache(ns->blkconf.blk)) {
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n->features.vwc = 0x1;
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}
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return 0;
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}
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static int nvme_ns_check_constraints(NvmeNamespace *ns, Error **errp)
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{
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if (!ns->blkconf.blk) {
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error_setg(errp, "block backend not configured");
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return -1;
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}
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return 0;
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}
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int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
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{
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if (nvme_ns_check_constraints(ns, errp)) {
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return -1;
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}
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if (nvme_ns_init_blk(n, ns, errp)) {
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return -1;
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}
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nvme_ns_init(ns);
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if (nvme_register_namespace(n, ns, errp)) {
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return -1;
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}
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return 0;
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}
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void nvme_ns_drain(NvmeNamespace *ns)
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{
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blk_drain(ns->blkconf.blk);
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}
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void nvme_ns_flush(NvmeNamespace *ns)
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{
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blk_flush(ns->blkconf.blk);
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}
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static void nvme_ns_realize(DeviceState *dev, Error **errp)
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{
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NvmeNamespace *ns = NVME_NS(dev);
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BusState *s = qdev_get_parent_bus(dev);
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NvmeCtrl *n = NVME(s->parent);
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Error *local_err = NULL;
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if (nvme_ns_setup(n, ns, &local_err)) {
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error_propagate_prepend(errp, local_err,
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"could not setup namespace: ");
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return;
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}
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}
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static Property nvme_ns_props[] = {
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DEFINE_BLOCK_PROPERTIES(NvmeNamespace, blkconf),
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DEFINE_PROP_UINT32("nsid", NvmeNamespace, params.nsid, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void nvme_ns_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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dc->bus_type = TYPE_NVME_BUS;
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dc->realize = nvme_ns_realize;
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device_class_set_props(dc, nvme_ns_props);
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dc->desc = "Virtual NVMe namespace";
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}
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static void nvme_ns_instance_init(Object *obj)
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{
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NvmeNamespace *ns = NVME_NS(obj);
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char *bootindex = g_strdup_printf("/namespace@%d,0", ns->params.nsid);
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device_add_bootindex_property(obj, &ns->bootindex, "bootindex",
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bootindex, DEVICE(obj));
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g_free(bootindex);
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}
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static const TypeInfo nvme_ns_info = {
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.name = TYPE_NVME_NS,
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.parent = TYPE_DEVICE,
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.class_init = nvme_ns_class_init,
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.instance_size = sizeof(NvmeNamespace),
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.instance_init = nvme_ns_instance_init,
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};
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static void nvme_ns_register_types(void)
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{
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type_register_static(&nvme_ns_info);
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}
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type_init(nvme_ns_register_types)
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@@ -0,0 +1,74 @@
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/*
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* QEMU NVM Express Virtual Namespace
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*
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* Copyright (c) 2019 CNEX Labs
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* Copyright (c) 2020 Samsung Electronics
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*
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* Authors:
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* Klaus Jensen <k.jensen@samsung.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*
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*/
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#ifndef NVME_NS_H
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#define NVME_NS_H
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#define TYPE_NVME_NS "nvme-ns"
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#define NVME_NS(obj) \
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OBJECT_CHECK(NvmeNamespace, (obj), TYPE_NVME_NS)
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typedef struct NvmeNamespaceParams {
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uint32_t nsid;
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} NvmeNamespaceParams;
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typedef struct NvmeNamespace {
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DeviceState parent_obj;
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BlockConf blkconf;
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int32_t bootindex;
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int64_t size;
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NvmeIdNs id_ns;
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NvmeNamespaceParams params;
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} NvmeNamespace;
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static inline uint32_t nvme_nsid(NvmeNamespace *ns)
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{
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if (ns) {
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return ns->params.nsid;
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}
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return -1;
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}
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static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns)
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{
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NvmeIdNs *id_ns = &ns->id_ns;
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return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)];
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}
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static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns)
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{
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return nvme_ns_lbaf(ns)->ds;
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}
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/* calculate the number of LBAs that the namespace can accomodate */
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static inline uint64_t nvme_ns_nlbas(NvmeNamespace *ns)
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{
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return ns->size >> nvme_ns_lbads(ns);
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}
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/* convert an LBA to the equivalent in bytes */
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static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba)
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{
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return lba << nvme_ns_lbads(ns);
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}
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typedef struct NvmeCtrl NvmeCtrl;
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int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error **errp);
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void nvme_ns_drain(NvmeNamespace *ns);
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void nvme_ns_flush(NvmeNamespace *ns);
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#endif /* NVME_NS_H */
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+162
-87
File diff suppressed because it is too large
Load Diff
+21
-25
@@ -2,6 +2,9 @@
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#define HW_NVME_H
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#include "block/nvme.h"
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#include "nvme-ns.h"
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#define NVME_MAX_NAMESPACES 256
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typedef struct NvmeParams {
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char *serial;
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@@ -90,26 +93,12 @@ typedef struct NvmeCQueue {
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QTAILQ_HEAD(, NvmeRequest) req_list;
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} NvmeCQueue;
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typedef struct NvmeNamespace {
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NvmeIdNs id_ns;
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} NvmeNamespace;
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#define TYPE_NVME_BUS "nvme-bus"
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#define NVME_BUS(obj) OBJECT_CHECK(NvmeBus, (obj), TYPE_NVME_BUS)
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static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns)
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{
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NvmeIdNs *id_ns = &ns->id_ns;
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return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)];
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}
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static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns)
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{
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return nvme_ns_lbaf(ns)->ds;
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}
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/* convert an LBA to the equivalent in bytes */
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static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba)
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{
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return lba << nvme_ns_lbads(ns);
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}
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typedef struct NvmeBus {
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BusState parent_bus;
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} NvmeBus;
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#define TYPE_NVME "nvme"
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#define NVME(obj) \
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@@ -121,6 +110,7 @@ typedef struct NvmeFeatureVal {
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uint16_t temp_thresh_low;
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};
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uint32_t async_config;
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uint32_t vwc;
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} NvmeFeatureVal;
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typedef struct NvmeCtrl {
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@@ -128,8 +118,9 @@ typedef struct NvmeCtrl {
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MemoryRegion iomem;
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MemoryRegion ctrl_mem;
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NvmeBar bar;
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BlockConf conf;
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NvmeParams params;
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NvmeBus bus;
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BlockConf conf;
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bool qs_created;
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uint32_t page_size;
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@@ -140,7 +131,6 @@ typedef struct NvmeCtrl {
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uint32_t reg_size;
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uint32_t num_namespaces;
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uint32_t max_q_ents;
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uint64_t ns_size;
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uint8_t outstanding_aers;
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uint8_t *cmbuf;
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uint32_t irq_status;
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@@ -156,7 +146,8 @@ typedef struct NvmeCtrl {
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QTAILQ_HEAD(, NvmeAsyncEvent) aer_queue;
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int aer_queued;
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NvmeNamespace *namespaces;
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NvmeNamespace namespace;
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NvmeNamespace *namespaces[NVME_MAX_NAMESPACES];
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NvmeSQueue **sq;
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NvmeCQueue **cq;
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NvmeSQueue admin_sq;
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@@ -165,10 +156,13 @@ typedef struct NvmeCtrl {
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NvmeFeatureVal features;
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} NvmeCtrl;
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/* calculate the number of LBAs that the namespace can accomodate */
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static inline uint64_t nvme_ns_nlbas(NvmeCtrl *n, NvmeNamespace *ns)
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static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid)
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{
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return n->ns_size >> nvme_ns_lbads(ns);
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if (!nsid || nsid > n->num_namespaces) {
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return NULL;
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}
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return n->namespaces[nsid - 1];
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}
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static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
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@@ -185,4 +179,6 @@ static inline NvmeCtrl *nvme_ctrl(NvmeRequest *req)
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return sq->ctrl;
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}
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int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp);
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#endif /* HW_NVME_H */
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@@ -29,6 +29,7 @@ hd_geometry_guess(void *blk, uint32_t cyls, uint32_t heads, uint32_t secs, int t
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# nvme.c
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# nvme traces for successful events
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pci_nvme_register_namespace(uint32_t nsid) "nsid %"PRIu32""
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pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u"
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pci_nvme_irq_pin(void) "pulsing IRQ pin"
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pci_nvme_irq_masked(void) "IRQ is masked"
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@@ -39,9 +40,9 @@ pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2,
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pci_nvme_map_sgl(uint16_t cid, uint8_t typ, uint64_t len) "cid %"PRIu16" type 0x%"PRIx8" len %"PRIu64""
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pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'"
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pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'"
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pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" '%s' nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
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pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" opname '%s' nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
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pci_nvme_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
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pci_nvme_write_zeroes(uint16_t cid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" slba %"PRIu64" nlb %"PRIu32""
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pci_nvme_write_zeroes(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" nsid %"PRIu32" slba %"PRIu64" nlb %"PRIu32""
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pci_nvme_do_aio(uint16_t cid, uint8_t opc, const char *opname, const char *blkname, int64_t offset, size_t len) "cid %"PRIu16" opc 0x%"PRIx8" opname '%s' blk '%s' offset %"PRId64" len %zu"
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pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize, uint16_t qflags) "create submission queue, addr=0x%"PRIx64", sqid=%"PRIu16", cqid=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16""
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pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t size, uint16_t qflags, int ien) "create completion queue, addr=0x%"PRIx64", cqid=%"PRIu16", vector=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16", ien=%d"
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@@ -100,7 +101,6 @@ pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or no
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pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64""
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pci_nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be transferred"
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pci_nvme_err_invalid_prp(void) "invalid PRP"
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pci_nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u not within 1-%u"
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pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8""
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pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8""
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pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "Invalid LBA start=%"PRIu64" len=%"PRIu64" limit=%"PRIu64""
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