Add MIPS32R2 instructions, and generally straighten out the instruction

decoding. This is also the first percent towards MIPS64 support.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/cpu.h

@@ -99,14 +99,16 @@ struct CPUMIPSState {
 #endif
     uint32_t CP0_index;
     uint32_t CP0_random;
-    uint32_t CP0_EntryLo0;
-    uint32_t CP0_EntryLo1;
-    uint32_t CP0_Context;
+    uint64_t CP0_EntryLo0;
+    uint64_t CP0_EntryLo1;
+    uint64_t CP0_Context;
     uint32_t CP0_PageMask;
+    uint32_t CP0_PageGrain;
     uint32_t CP0_Wired;
+    uint32_t CP0_HWREna;
     uint32_t CP0_BadVAddr;
     uint32_t CP0_Count;
-    uint32_t CP0_EntryHi;
+    uint64_t CP0_EntryHi;
     uint32_t CP0_Compare;
     uint32_t CP0_Status;
 #define CP0St_CU3   31
@@ -116,19 +118,36 @@ struct CPUMIPSState {
 #define CP0St_RP    27
 #define CP0St_FR    26
 #define CP0St_RE    25
+#define CP0St_MX    24
+#define CP0St_PX    23
 #define CP0St_BEV   22
 #define CP0St_TS    21
 #define CP0St_SR    20
 #define CP0St_NMI   19
 #define CP0St_IM    8
+#define CP0St_KX    7
+#define CP0St_SX    6
+#define CP0St_UX    5
 #define CP0St_UM    4
+#define CP0St_R0    3
 #define CP0St_ERL   2
 #define CP0St_EXL   1
 #define CP0St_IE    0
+    uint32_t CP0_IntCtl;
+    uint32_t CP0_SRSCtl;
     uint32_t CP0_Cause;
+#define CP0Ca_BD   31
+#define CP0Ca_TI   30
+#define CP0Ca_CE   28
+#define CP0Ca_DC   27
+#define CP0Ca_PCI  26
 #define CP0Ca_IV   23
+#define CP0Ca_WP   22
+#define CP0Ca_IP    8
+#define CP0Ca_EC    2
     uint32_t CP0_EPC;
     uint32_t CP0_PRid;
+    uint32_t CP0_EBase;
     uint32_t CP0_Config0;
 #define CP0C0_M    31
 #define CP0C0_K23  28
@@ -140,8 +159,10 @@ struct CPUMIPSState {
 #define CP0C0_AT   13
 #define CP0C0_AR   10
 #define CP0C0_MT   7
+#define CP0C0_VI   3
 #define CP0C0_K0   0
     uint32_t CP0_Config1;
+#define CP0C1_M    31
 #define CP0C1_MMU  25
 #define CP0C1_IS   22
 #define CP0C1_IL   19
@@ -149,14 +170,38 @@ struct CPUMIPSState {
 #define CP0C1_DS   13
 #define CP0C1_DL   10
 #define CP0C1_DA   7
+#define CP0C1_C2   6
+#define CP0C1_MD   5
 #define CP0C1_PC   4
 #define CP0C1_WR   3
 #define CP0C1_CA   2
 #define CP0C1_EP   1
 #define CP0C1_FP   0
+    uint32_t CP0_Config2;
+#define CP0C2_M    31
+#define CP0C2_TU   28
+#define CP0C2_TS   24
+#define CP0C2_TL   20
+#define CP0C2_TA   16
+#define CP0C2_SU   12
+#define CP0C2_SS   8
+#define CP0C2_SL   4
+#define CP0C2_SA   0
+    uint32_t CP0_Config3;
+#define CP0C3_M    31
+#define CP0C3_DSPP 10
+#define CP0C3_LPA  7
+#define CP0C3_VEIC 6
+#define CP0C3_VInt 5
+#define CP0C3_SP   4
+#define CP0C3_MT   2
+#define CP0C3_SM   1
+#define CP0C3_TL   0
     uint32_t CP0_LLAddr;
     uint32_t CP0_WatchLo;
     uint32_t CP0_WatchHi;
+    uint32_t CP0_XContext;
+    uint32_t CP0_Framemask;
     uint32_t CP0_Debug;
 #define CPDB_DBD   31
 #define CP0DB_DM   30
@@ -177,8 +222,11 @@ struct CPUMIPSState {
 #define CP0DB_DBp  1
 #define CP0DB_DSS  0
     uint32_t CP0_DEPC;
+    uint32_t CP0_Performance0;
     uint32_t CP0_TagLo;
     uint32_t CP0_DataLo;
+    uint32_t CP0_TagHi;
+    uint32_t CP0_DataHi;
     uint32_t CP0_ErrorEPC;
     uint32_t CP0_DESAVE;
     /* Qemu */
@@ -211,6 +259,9 @@ struct CPUMIPSState {
 
     int halted; /* TRUE if the CPU is in suspend state */
 
+    int SYNCI_Step; /* Address step size for SYNCI */
+    int CCRes; /* Cycle count resolution/divisor */
+
     CPU_COMMON
 
     int ram_size;

target-mips/exec.h

@@ -68,6 +68,7 @@ void do_msubu (void);
 #endif
 void do_mfc0_random(void);
 void do_mfc0_count(void);
+void do_mtc0_entryhi(uint32_t in);
 void do_mtc0_status_debug(uint32_t old, uint32_t val);
 void do_mtc0_status_irqraise_debug(void);
 void do_tlbwi (void);

target-mips/helper.c

@@ -302,15 +302,9 @@ void do_interrupt (CPUState *env)
 #endif
         env->CP0_Wired = 0;
         env->CP0_Config0 = MIPS_CONFIG0;
-#if defined (MIPS_CONFIG1)
         env->CP0_Config1 = MIPS_CONFIG1;
-#endif
-#if defined (MIPS_CONFIG2)
         env->CP0_Config2 = MIPS_CONFIG2;
-#endif
-#if defined (MIPS_CONFIG3)
         env->CP0_Config3 = MIPS_CONFIG3;
-#endif
         env->CP0_WatchLo = 0;
         env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
         goto set_error_EPC;

target-mips/mips-defs.h

@@ -29,26 +29,44 @@
  * Define a major version 1, minor version 0.
  */
 #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
-/* Have config1, uses TLB */
-#define MIPS_CONFIG0_1                                          \
-((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) |          \
- (1 << CP0C0_MT) | (2 << CP0C0_K0))
+  /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
+     uncached coherency */
+#define MIPS_CONFIG0_1                                            \
+  ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) |      \
+   (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
+   (0x2 << CP0C0_K0))
 #ifdef TARGET_WORDS_BIGENDIAN
 #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
 #else
 #define MIPS_CONFIG0 MIPS_CONFIG0_1
 #endif
-/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
- * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
- * no performance counters, watch registers present, no code compression,
- * EJTAG present, FPU enable bit depending on MIPS_USES_FPU
- */
-#define MIPS_CONFIG1                                            \
-((15 << CP0C1_MMU) |                                            \
- (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \
- (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \
- (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) |          \
- (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP))
+/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
+   2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
+   no coprocessor2 attached, no MDMX support attached,
+   no performance counters, watch registers present,
+   no code compression, EJTAG present, FPU enable bit depending on
+   MIPS_USES_FPU */
+#define MIPS_CONFIG1_1                                            \
+((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) |              \
+ (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) |      \
+ (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) |      \
+ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
+ (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP))
+#ifdef MIPS_USES_FPU
+#define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (1 << CP0C1_FP))
+#else
+#define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (0 << CP0C1_FP))
+#endif
+/* Have config3, no tertiary/secondary caches implemented */
+#define MIPS_CONFIG2                                              \
+((1 << CP0C2_M))
+/* No config4, no DSP ASE, no large physaddr,
+   no external interrupt controller, no vectored interupts,
+   no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
+#define MIPS_CONFIG3                                              \
+((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
+ (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
+ (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
 #elif (MIPS_CPU == MIPS_R4Kp)
 /* 32 bits target */
 #define TARGET_LONG_BITS 32
@@ -60,7 +78,7 @@
 #define MIPS_USES_R4K_FPM
 #else
 #error "MIPS CPU not defined"
-/* Remainder for other flags */
+/* Reminder for other flags */
 //#define TARGET_MIPS64
 //#define MIPS_USES_FPU
 #endif

target-mips/op_helper.c

@@ -153,12 +153,12 @@ void cpu_mips_store_compare(CPUState *env, uint32_t value)
 
 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 {
-    cpu_abort(env, "mtc0 status\n");
+    cpu_abort(env, "mtc0 status debug\n");
 }
 
-void do_mtc0_status_irqraise_debug(void)
+void do_mtc0_status_irqraise_debug (void)
 {
-    cpu_abort(env, "mtc0 status\n");
+    cpu_abort(env, "mtc0 status irqraise debug\n");
 }
 
 void do_tlbwi (void)