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Merge tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu into staging

Browse Source 
Second RISC-V PR for QEMU 7.1

 * Improve device tree generation
 * Support configuarable marchid, mvendorid, mipid CSR values
 * Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions
 * Fix incorrect PTE merge in walk_pte
 * Add TPM support to the virt board

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmJraeUACgkQIeENKd+X
# cFRLjgf9GFmxPhOC8cb7wN6xsiJIiVmmcTGHKfUgFTAIR2KLOEm2fo28YNrgewok
# Hi7FBHLhYKEivz70GFVg7q6oJlqhYx8fL4AB0sodTetIcJGQPQgz8zN7ZD8utnzA
# d6n7ZruyW5IuUqCBUcsHNqBHxoYanR88rr6YpxU+nSz0WALYRgQliXm5zqK1rwNc
# v8HpLHyN7JUmAQmJ1U6Uc6IFi/cFn9e/Hs/uRMevKov2nCTxeeAq5G2r8JGKpx35
# VRid91dcWbGiRY1xHWqnl/0WZxl8Jp4av1e5NDbXfwYPvwiI2fza5KFasp2S38yR
# VvnUcI+p73qclCF7LkfL9c//xQT1iA==
# =Xkoz
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 28 Apr 2022 09:30:29 PM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu: (25 commits)
  hw/riscv: Enable TPM backends
  hw/riscv: virt: Add device plug support
  hw/riscv: virt: Add support for generating platform FDT entries
  hw/riscv: virt: Create a platform bus
  hw/core: Move the ARM sysbus-fdt to core
  hw/riscv: virt: Add a machine done notifier
  target/riscv: add scalar crypto related extenstion strings to isa_string
  target/riscv: Fix incorrect PTE merge in walk_pte
  target/riscv: rvk: expose zbk* and zk* properties
  disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
  target/riscv: rvk: add CSR support for Zkr
  target/riscv: rvk: add support for zksed/zksh extension
  target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
  target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
  target/riscv: rvk: add support for sha256 related instructions in zknh extension
  target/riscv: rvk: add support for zkne/zknd extension in RV64
  target/riscv: rvk: add support for zknd/zkne extension in RV32
  crypto: move sm4_sbox from target/arm
  target/riscv: rvk: add support for zbkx extension
  target/riscv: rvk: add support for zbkc extension
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2022-04-29 08:46:55 -07:00
parent f228336020 325b7c4e75
commit 731340813f
33 changed files with 1682 additions and 199 deletions
Download Patch File Download Diff File Expand all files Collapse all files
crypto/meson.build
+1
View File
@@ -42,6 +42,7 @@ if have_afalg
endif
crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
util_ss.add(files('sm4.c'))
util_ss.add(files('aes.c'))
util_ss.add(files('init.c'))
if gnutls.found()
crypto/sm4.c
+49
View File
@@ -0,0 +1,49 @@
/*
* QEMU crypto sm4 support
*
* Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*/
#include "qemu/osdep.h"
#include "crypto/sm4.h"
uint8_t const sm4_sbox[] = {
0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
};
disas/riscv.c
+172 -1
View File
@@ -156,6 +156,8 @@ typedef enum {
rv_codec_css_swsp,
rv_codec_css_sdsp,
rv_codec_css_sqsp,
rv_codec_k_bs,
rv_codec_k_rnum,
} rv_codec;
typedef enum {
@@ -521,6 +523,43 @@ typedef enum {
rv_op_bclr = 359,
rv_op_binv = 360,
rv_op_bext = 361,
rv_op_aes32esmi = 362,
rv_op_aes32esi = 363,
rv_op_aes32dsmi = 364,
rv_op_aes32dsi = 365,
rv_op_aes64ks1i = 366,
rv_op_aes64ks2 = 367,
rv_op_aes64im = 368,
rv_op_aes64esm = 369,
rv_op_aes64es = 370,
rv_op_aes64dsm = 371,
rv_op_aes64ds = 372,
rv_op_sha256sig0 = 373,
rv_op_sha256sig1 = 374,
rv_op_sha256sum0 = 375,
rv_op_sha256sum1 = 376,
rv_op_sha512sig0 = 377,
rv_op_sha512sig1 = 378,
rv_op_sha512sum0 = 379,
rv_op_sha512sum1 = 380,
rv_op_sha512sum0r = 381,
rv_op_sha512sum1r = 382,
rv_op_sha512sig0l = 383,
rv_op_sha512sig0h = 384,
rv_op_sha512sig1l = 385,
rv_op_sha512sig1h = 386,
rv_op_sm3p0 = 387,
rv_op_sm3p1 = 388,
rv_op_sm4ed = 389,
rv_op_sm4ks = 390,
rv_op_brev8 = 391,
rv_op_pack = 392,
rv_op_packh = 393,
rv_op_packw = 394,
rv_op_unzip = 395,
rv_op_zip = 396,
rv_op_xperm4 = 397,
rv_op_xperm8 = 398,
} rv_op;
/* structures */
@@ -540,6 +579,8 @@ typedef struct {
uint8_t succ;
uint8_t aq;
uint8_t rl;
uint8_t bs;
uint8_t rnum;
} rv_decode;
typedef struct {
@@ -615,6 +656,8 @@ static const char rv_freg_name_sym[32][5] = {
#define rv_fmt_rd_rs2 "O\t0,2"
#define rv_fmt_rs1_offset "O\t1,o"
#define rv_fmt_rs2_offset "O\t2,o"
#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
/* pseudo-instruction constraints */
@@ -766,6 +809,7 @@ static const rv_comp_data rvcp_csrrw[] = {
{ rv_op_illegal, NULL }
};
static const rv_comp_data rvcp_csrrs[] = {
{ rv_op_rdcycle, rvcc_rdcycle },
{ rv_op_rdtime, rvcc_rdtime },
@@ -1203,6 +1247,43 @@ const rv_opcode_data opcode_data[] = {
{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
{ "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
};
/* CSR names */
@@ -1216,6 +1297,7 @@ static const char *csr_name(int csrno)
case 0x0003: return "fcsr";
case 0x0004: return "uie";
case 0x0005: return "utvec";
case 0x0015: return "seed";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
@@ -1594,7 +1676,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_slli; break;
case 0b00001:
switch (((inst >> 20) & 0b1111111)) {
case 0b0001111: op = rv_op_zip; break;
}
break;
case 0b00010:
switch (((inst >> 20) & 0b1111111)) {
case 0b0000000: op = rv_op_sha256sum0; break;
case 0b0000001: op = rv_op_sha256sum1; break;
case 0b0000010: op = rv_op_sha256sig0; break;
case 0b0000011: op = rv_op_sha256sig1; break;
case 0b0000100: op = rv_op_sha512sum0; break;
case 0b0000101: op = rv_op_sha512sum1; break;
case 0b0000110: op = rv_op_sha512sig0; break;
case 0b0000111: op = rv_op_sha512sig1; break;
case 0b0001000: op = rv_op_sm3p0; break;
case 0b0001001: op = rv_op_sm3p1; break;
}
break;
case 0b00101: op = rv_op_bseti; break;
case 0b00110:
switch (((inst >> 20) & 0b1111111)) {
case 0b0000000: op = rv_op_aes64im; break;
default:
if (((inst >> 24) & 0b0111) == 0b001) {
op = rv_op_aes64ks1i;
}
break;
}
break;
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
@@ -1615,13 +1726,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 5:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_srli; break;
case 0b00001:
switch (((inst >> 20) & 0b1111111)) {
case 0b0001111: op = rv_op_unzip; break;
}
break;
case 0b00101: op = rv_op_orc_b; break;
case 0b01000: op = rv_op_srai; break;
case 0b01001: op = rv_op_bexti; break;
case 0b01100: op = rv_op_rori; break;
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
case 0b0011000: op = rv_op_rev8; break;
case 0b0111000: op = rv_op_rev8; break;
case 0b0000111: op = rv_op_brev8; break;
}
break;
}
@@ -1742,8 +1860,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
default: op = rv_op_pack; break;
}
break;
case 39: op = rv_op_packh; break;
case 41: op = rv_op_clmul; break;
case 42: op = rv_op_clmulr; break;
case 43: op = rv_op_clmulh; break;
@@ -1755,6 +1876,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
case 161: op = rv_op_bset; break;
case 162: op = rv_op_xperm4; break;
case 164: op = rv_op_xperm8; break;
case 200: op = rv_op_aes64es; break;
case 216: op = rv_op_aes64esm; break;
case 232: op = rv_op_aes64ds; break;
case 248: op = rv_op_aes64dsm; break;
case 256: op = rv_op_sub; break;
case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break;
@@ -1762,9 +1889,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 263: op = rv_op_andn; break;
case 289: op = rv_op_bclr; break;
case 293: op = rv_op_bext; break;
case 320: op = rv_op_sha512sum0r; break;
case 328: op = rv_op_sha512sum1r; break;
case 336: op = rv_op_sha512sig0l; break;
case 344: op = rv_op_sha512sig1l; break;
case 368: op = rv_op_sha512sig0h; break;
case 376: op = rv_op_sha512sig1h; break;
case 385: op = rv_op_rol; break;
case 386: op = rv_op_ror; break;
case 389: op = rv_op_ror; break;
case 417: op = rv_op_binv; break;
case 504: op = rv_op_aes64ks2; break;
}
switch ((inst >> 25) & 0b0011111) {
case 17: op = rv_op_aes32esi; break;
case 19: op = rv_op_aes32esmi; break;
case 21: op = rv_op_aes32dsi; break;
case 23: op = rv_op_aes32dsmi; break;
case 24: op = rv_op_sm4ed; break;
case 26: op = rv_op_sm4ks; break;
}
break;
case 13: op = rv_op_lui; break;
@@ -1782,6 +1924,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
default: op = rv_op_packw; break;
}
break;
case 130: op = rv_op_sh1add_uw; break;
@@ -2374,6 +2517,16 @@ static uint32_t operand_cimmq(rv_inst inst)
((inst << 57) >> 62) << 6;
}
static uint32_t operand_bs(rv_inst inst)
{
return (inst << 32) >> 62;
}
static uint32_t operand_rnum(rv_inst inst)
{
return (inst << 40) >> 60;
}
/* decode operands */
static void decode_inst_operands(rv_decode *dec)
@@ -2653,6 +2806,16 @@ static void decode_inst_operands(rv_decode *dec)
dec->rs2 = operand_crs2(inst);
dec->imm = operand_cimmsqsp(inst);
break;
case rv_codec_k_bs:
dec->rs1 = operand_rs1(inst);
dec->rs2 = operand_rs2(inst);
dec->bs = operand_bs(inst);
break;
case rv_codec_k_rnum:
dec->rd = operand_rd(inst);
dec->rs1 = operand_rs1(inst);
dec->rnum = operand_rnum(inst);
break;
};
}
@@ -2812,6 +2975,14 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
case ')':
append(buf, ")", buflen);
break;
case 'b':
snprintf(tmp, sizeof(tmp), "%d", dec->bs);
append(buf, tmp, buflen);
break;
case 'n':
snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
append(buf, tmp, buflen);
break;
case '0':
append(buf, rv_ireg_name_sym[dec->rd], buflen);
break;
docs/system/riscv/virt.rst
+20
View File
@@ -162,3 +162,23 @@ The minimal QEMU commands to run U-Boot SPL are:
To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and
riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with
``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.
Enabling TPM
------------
A TPM device can be connected to the virt board by following the steps below.
First launch the TPM emulator
swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
--ctrl type=unixio,path=swtpm-sock
Then launch QEMU with:
...
-chardev socket,id=chrtpm,path=swtpm-sock \
-tpmdev emulator,id=tpm0,chardev=chrtpm \
-device tpm-tis-device,tpmdev=tpm0
The TPM device can be seen in the memory tree and the generated device
tree and should be accessible from the guest software.
hw/arm/meson.build
-1
View File
@@ -1,6 +1,5 @@
arm_ss = ss.source_set()
arm_ss.add(files('boot.c'), fdt)
arm_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
hw/arm/virt.c
+1 -1
View File
@@ -56,7 +56,7 @@
#include "qemu/module.h"
#include "hw/pci-host/gpex.h"
#include "hw/virtio/virtio-pci.h"
#include "hw/arm/sysbus-fdt.h"
#include "hw/core/sysbus-fdt.h"
#include "hw/platform-bus.h"
#include "hw/qdev-properties.h"
#include "hw/arm/fdt.h"
hw/arm/xlnx-versal-virt.c
-1
View File
@@ -15,7 +15,6 @@
#include "sysemu/device_tree.h"
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/arm/sysbus-fdt.h"
#include "hw/arm/fdt.h"
#include "cpu.h"
#include "hw/qdev-properties.h"
hw/core/meson.build
+1
View File
@@ -33,6 +33,7 @@ softmmu_ss.add(when: 'CONFIG_PTIMER', if_true: files('ptimer.c'))
softmmu_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c'))
softmmu_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c'))
softmmu_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c'))
softmmu_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
softmmu_ss.add(files(
'cpu-sysemu.c',
hw/arm/sysbus-fdt.c → hw/core/sysbus-fdt.c
+1 -1
View File
@@ -27,7 +27,7 @@
#ifdef CONFIG_LINUX
#include <linux/vfio.h>
#endif
#include "hw/arm/sysbus-fdt.h"
#include "hw/core/sysbus-fdt.h"
#include "qemu/error-report.h"
#include "sysemu/device_tree.h"
#include "sysemu/tpm.h"
hw/riscv/Kconfig
+2
View File
@@ -34,6 +34,7 @@ config RISCV_VIRT
imply PCI_DEVICES
imply VIRTIO_VGA
imply TEST_DEVICES
imply TPM_TIS_SYSBUS
select RISCV_NUMA
select GOLDFISH_RTC
select MSI_NONBROKEN
@@ -48,6 +49,7 @@ config RISCV_VIRT
select SIFIVE_TEST
select VIRTIO_MMIO
select FW_CFG_DMA
select PLATFORM_BUS
config SIFIVE_E
bool
hw/riscv/microchip_pfsoc.c
+1 -1
View File
@@ -571,7 +571,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
"linux,initrd-end", end);
}
if (machine->kernel_cmdline) {
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
qemu_fdt_setprop_string(machine->fdt, "/chosen",
"bootargs", machine->kernel_cmdline);
}
hw/riscv/sifive_u.c
+1 -1
View File
@@ -511,7 +511,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
g_free(nodename);
update_bootargs:
if (cmdline) {
if (cmdline && *cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
}
hw/riscv/spike.c
+4 -3
View File
@@ -174,10 +174,11 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
riscv_socket_fdt_write_distance_matrix(mc, fdt);
if (cmdline) {
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
if (cmdline && *cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
}
}
hw/riscv/virt.c
+209 -110
View File
@@ -28,6 +28,7 @@
#include "hw/qdev-properties.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/core/sysbus-fdt.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
@@ -37,10 +38,12 @@
#include "hw/intc/riscv_imsic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_test.h"
#include "hw/platform-bus.h"
#include "chardev/char.h"
#include "sysemu/device_tree.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "sysemu/tpm.h"
#include "hw/pci/pci.h"
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
@@ -68,25 +71,26 @@
#endif
static const MemMapEntry virt_memmap[] = {
[VIRT_DEBUG] = { 0x0, 0x100 },
[VIRT_MROM] = { 0x1000, 0xf000 },
[VIRT_TEST] = { 0x100000, 0x1000 },
[VIRT_RTC] = { 0x101000, 0x1000 },
[VIRT_CLINT] = { 0x2000000, 0x10000 },
[VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
[VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
[VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
[VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
[VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
[VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
[VIRT_DRAM] = { 0x80000000, 0x0 },
[VIRT_DEBUG] = { 0x0, 0x100 },
[VIRT_MROM] = { 0x1000, 0xf000 },
[VIRT_TEST] = { 0x100000, 0x1000 },
[VIRT_RTC] = { 0x101000, 0x1000 },
[VIRT_CLINT] = { 0x2000000, 0x10000 },
[VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
[VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
[VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
[VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
[VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
[VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
[VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
[VIRT_DRAM] = { 0x80000000, 0x0 },
};
/* PCIe high mmio is fixed for RV32 */
@@ -473,6 +477,12 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
plic_phandles[socket]);
platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
memmap[VIRT_PLATFORM_BUS].base,
memmap[VIRT_PLATFORM_BUS].size,
VIRT_PLATFORM_BUS_IRQ);
g_free(plic_name);
g_free(plic_cells);
@@ -550,6 +560,12 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
IMSIC_MMIO_GROUP_MIN_SHIFT);
}
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name,
memmap[VIRT_PLATFORM_BUS].base,
memmap[VIRT_PLATFORM_BUS].size,
VIRT_PLATFORM_BUS_IRQ);
g_free(imsic_name);
/* S-level IMSIC node */
@@ -687,6 +703,12 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
VIRT_IRQCHIP_NUM_SOURCES);
riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
memmap[VIRT_PLATFORM_BUS].base,
memmap[VIRT_PLATFORM_BUS].size,
VIRT_PLATFORM_BUS_IRQ);
g_free(aplic_name);
g_free(aplic_cells);
@@ -1004,7 +1026,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
create_fdt_flash(s, memmap);
update_bootargs:
if (cmdline) {
if (cmdline && *cmdline) {
qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
}
}
@@ -1162,6 +1184,126 @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
return aplic_m;
}
static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
{
DeviceState *dev;
SysBusDevice *sysbus;
const MemMapEntry *memmap = virt_memmap;
int i;
MemoryRegion *sysmem = get_system_memory();
dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s->platform_bus_dev = dev;
sysbus = SYS_BUS_DEVICE(dev);
for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
int irq = VIRT_PLATFORM_BUS_IRQ + i;
sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq));
}
memory_region_add_subregion(sysmem,
memmap[VIRT_PLATFORM_BUS].base,
sysbus_mmio_get_region(sysbus, 0));
}
static void virt_machine_done(Notifier *notifier, void *data)
{
RISCVVirtState *s = container_of(notifier, RISCVVirtState,
machine_done);
const MemMapEntry *memmap = virt_memmap;
MachineState *machine = MACHINE(s);
target_ulong start_addr = memmap[VIRT_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
uint32_t fdt_load_addr;
uint64_t kernel_entry;
/*
* Only direct boot kernel is currently supported for KVM VM,
* so the "-bios" parameter is not supported when KVM is enabled.
*/
if (kvm_enabled()) {
if (machine->firmware) {
if (strcmp(machine->firmware, "none")) {
error_report("Machine mode firmware is not supported in "
"combination with KVM.");
exit(1);
}
} else {
machine->firmware = g_strdup("none");
}
}
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV32_BIOS_BIN, start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV64_BIOS_BIN, start_addr, NULL);
}
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine->kernel_filename,
kernel_start_addr, NULL);
if (machine->initrd_filename) {
hwaddr start;
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
qemu_fdt_setprop_cell(machine->fdt, "/chosen",
"linux,initrd-start", start);
qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
end);
}
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
* if kernel argument is not set.
*/
kernel_entry = 0;
}
if (drive_get(IF_PFLASH, 0, 0)) {
/*
* Pflash was supplied, let's overwrite the address we jump to after
* reset to the base of the flash.
*/
start_addr = virt_memmap[VIRT_FLASH].base;
}
/*
* Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
* tree cannot be altered and we get FDT_ERR_NOSPACE.
*/
s->fw_cfg = create_fw_cfg(machine);
rom_set_fw(s->fw_cfg);
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
machine->ram_size, machine->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
virt_memmap[VIRT_MROM].base,
virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, machine->fdt);
/*
* Only direct boot kernel is currently supported for KVM VM,
* So here setup kernel start address and fdt address.
* TODO:Support firmware loading and integrate to TCG start
*/
if (kvm_enabled()) {
riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
}
}
static void virt_machine_init(MachineState *machine)
{
const MemMapEntry *memmap = virt_memmap;
@@ -1169,10 +1311,6 @@ static void virt_machine_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
char *soc_name;
target_ulong start_addr = memmap[VIRT_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
uint32_t fdt_load_addr;
uint64_t kernel_entry;
DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
int i, base_hartid, hart_count;
@@ -1302,98 +1440,12 @@ static void virt_machine_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
machine->ram);
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(&s->soc[0]));
/* boot rom */
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
memmap[VIRT_MROM].size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
mask_rom);
/*
* Only direct boot kernel is currently supported for KVM VM,
* so the "-bios" parameter is not supported when KVM is enabled.
*/
if (kvm_enabled()) {
if (machine->firmware) {
if (strcmp(machine->firmware, "none")) {
error_report("Machine mode firmware is not supported in "
"combination with KVM.");
exit(1);
}
} else {
machine->firmware = g_strdup("none");
}
}
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV32_BIOS_BIN, start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV64_BIOS_BIN, start_addr, NULL);
}
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine->kernel_filename,
kernel_start_addr, NULL);
if (machine->initrd_filename) {
hwaddr start;
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
qemu_fdt_setprop_cell(machine->fdt, "/chosen",
"linux,initrd-start", start);
qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
end);
}
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
* if kernel argument is not set.
*/
kernel_entry = 0;
}
if (drive_get(IF_PFLASH, 0, 0)) {
/*
* Pflash was supplied, let's overwrite the address we jump to after
* reset to the base of the flash.
*/
start_addr = virt_memmap[VIRT_FLASH].base;
}
/*
* Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
* tree cannot be altered and we get FDT_ERR_NOSPACE.
*/
s->fw_cfg = create_fw_cfg(machine);
rom_set_fw(s->fw_cfg);
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
machine->ram_size, machine->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
virt_memmap[VIRT_MROM].base,
virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, machine->fdt);
/*
* Only direct boot kernel is currently supported for KVM VM,
* So here setup kernel start address and fdt address.
* TODO:Support firmware loading and integrate to TCG start
*/
if (kvm_enabled()) {
riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
}
/* SiFive Test MMIO device */
sifive_test_create(memmap[VIRT_TEST].base);
@@ -1414,6 +1466,8 @@ static void virt_machine_init(MachineState *machine)
memmap[VIRT_PCIE_PIO].base,
DEVICE(pcie_irqchip));
create_platform_bus(s, DEVICE(mmio_irqchip));
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
@@ -1429,6 +1483,13 @@ static void virt_machine_init(MachineState *machine)
drive_get(IF_PFLASH, 0, i));
}
virt_flash_map(s, system_memory);
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(&s->soc[0]));
s->machine_done.notify = virt_machine_done;
qemu_add_machine_init_done_notifier(&s->machine_done);
}
static void virt_machine_instance_init(Object *obj)
@@ -1509,10 +1570,37 @@ static void virt_set_aclint(Object *obj, bool value, Error **errp)
s->have_aclint = value;
}
static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
DeviceState *dev)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
if (device_is_dynamic_sysbus(mc, dev)) {
return HOTPLUG_HANDLER(machine);
}
return NULL;
}
static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
if (s->platform_bus_dev) {
MachineClass *mc = MACHINE_GET_CLASS(s);
if (device_is_dynamic_sysbus(mc, dev)) {
platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
SYS_BUS_DEVICE(dev));
}
}
}
static void virt_machine_class_init(ObjectClass *oc, void *data)
{
char str[128];
MachineClass *mc = MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
mc->desc = "RISC-V VirtIO board";
mc->init = virt_machine_init;
@@ -1524,8 +1612,15 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
mc->numa_mem_supported = true;
mc->default_ram_id = "riscv_virt_board.ram";
assert(!mc->get_hotplug_handler);
mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
hc->plug = virt_machine_device_plug_cb;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
#ifdef CONFIG_TPM
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
#endif
object_class_property_add_bool(oc, "aclint", virt_get_aclint,
virt_set_aclint);
@@ -1554,6 +1649,10 @@ static const TypeInfo virt_machine_typeinfo = {
.class_init = virt_machine_class_init,
.instance_init = virt_machine_instance_init,
.instance_size = sizeof(RISCVVirtState),
.interfaces = (InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
{ }
},
};
static void virt_machine_init_register_types(void)
include/crypto/sm4.h
+6
View File
@@ -0,0 +1,6 @@
#ifndef QEMU_SM4_H
#define QEMU_SM4_H
extern const uint8_t sm4_sbox[256];
#endif
include/hw/arm/sysbus-fdt.h → include/hw/core/sysbus-fdt.h
View File
include/hw/riscv/virt.h
+7 -1
View File
@@ -45,6 +45,8 @@ struct RISCVVirtState {
MachineState parent;
/*< public >*/
Notifier machine_done;
DeviceState *platform_bus_dev;
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
DeviceState *irqchip[VIRT_SOCKETS_MAX];
PFlashCFI01 *flash[2];
@@ -75,6 +77,7 @@ enum {
VIRT_DRAM,
VIRT_PCIE_MMIO,
VIRT_PCIE_PIO,
VIRT_PLATFORM_BUS,
VIRT_PCIE_ECAM
};
@@ -84,9 +87,12 @@ enum {
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
PCIE_IRQ = 0x20, /* 32 to 35 */
VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
};
#define VIRT_PLATFORM_BUS_NUM_IRQS 32
#define VIRT_IRQCHIP_IPI_MSI 1
#define VIRT_IRQCHIP_NUM_MSIS 255
#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
target/arm/crypto_helper.c
+1 -35
View File
@@ -15,6 +15,7 @@
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "crypto/aes.h"
#include "crypto/sm4.h"
#include "vec_internal.h"
union CRYPTO_STATE {
@@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
#undef DO_SM3TT
static uint8_t const sm4_sbox[] = {
0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
};
static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
{
union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
target/riscv/bitmanip_helper.c
+80
View File
@@ -49,3 +49,83 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
return result;
}
static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
{
return ((x & mask) << shift) | ((x & ~mask) >> shift);
}
target_ulong HELPER(brev8)(target_ulong rs1)
{
target_ulong x = rs1;
x = do_swap(x, 0x5555555555555555ull, 1);
x = do_swap(x, 0x3333333333333333ull, 2);
x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
return x;
}
static const uint64_t shuf_masks[] = {
dup_const(MO_8, 0x44),
dup_const(MO_8, 0x30),
dup_const(MO_16, 0x0f00),
dup_const(MO_32, 0xff0000)
};
static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
uint64_t maskR, int shift)
{
target_ulong x = src & ~(maskL | maskR);
x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
return x;
}
target_ulong HELPER(unzip)(target_ulong rs1)
{
target_ulong x = rs1;
x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
return x;
}
target_ulong HELPER(zip)(target_ulong rs1)
{
target_ulong x = rs1;
x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
return x;
}
static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
uint32_t sz_log2)
{
target_ulong r = 0;
target_ulong sz = 1LL << sz_log2;
target_ulong mask = (1LL << sz) - 1;
target_ulong pos;
for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
pos = ((rs2 >> i) & mask) << sz_log2;
if (pos < sizeof(target_ulong) * 8) {
r |= ((rs1 >> pos) & mask) << i;
}
}
return r;
}
target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
{
return do_xperm(rs1, rs2, 2);
}
target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
{
return do_xperm(rs1, rs2, 3);
}
target/riscv/cpu.c
+58
View File
@@ -34,6 +34,11 @@
/* RISC-V CPU definitions */
#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
(QEMU_VERSION_MINOR << 8) | \
(QEMU_VERSION_MICRO))
#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
struct isa_ext_data {
@@ -607,6 +612,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_zfinx = true;
}
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
cpu->cfg.ext_zkt = true;
}
if (cpu->cfg.ext_zkn) {
cpu->cfg.ext_zbkb = true;
cpu->cfg.ext_zbkc = true;
cpu->cfg.ext_zbkx = true;
cpu->cfg.ext_zkne = true;
cpu->cfg.ext_zknd = true;
cpu->cfg.ext_zknh = true;
}
if (cpu->cfg.ext_zks) {
cpu->cfg.ext_zbkb = true;
cpu->cfg.ext_zbkc = true;
cpu->cfg.ext_zbkx = true;
cpu->cfg.ext_zksed = true;
cpu->cfg.ext_zksh = true;
}
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
ext |= RVI;
@@ -810,6 +838,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
@@ -817,7 +849,20 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
@@ -960,7 +1005,20 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
ISA_EDATA_ENTRY(zba, ext_zba),
ISA_EDATA_ENTRY(zbb, ext_zbb),
ISA_EDATA_ENTRY(zbc, ext_zbc),
ISA_EDATA_ENTRY(zbkb, ext_zbkb),
ISA_EDATA_ENTRY(zbkc, ext_zbkc),
ISA_EDATA_ENTRY(zbkx, ext_zbkx),
ISA_EDATA_ENTRY(zbs, ext_zbs),
ISA_EDATA_ENTRY(zk, ext_zk),
ISA_EDATA_ENTRY(zkn, ext_zkn),
ISA_EDATA_ENTRY(zknd, ext_zknd),
ISA_EDATA_ENTRY(zkne, ext_zkne),
ISA_EDATA_ENTRY(zknh, ext_zknh),
ISA_EDATA_ENTRY(zkr, ext_zkr),
ISA_EDATA_ENTRY(zks, ext_zks),
ISA_EDATA_ENTRY(zksed, ext_zksed),
ISA_EDATA_ENTRY(zksh, ext_zksh),
ISA_EDATA_ENTRY(zkt, ext_zkt),
ISA_EDATA_ENTRY(zve32f, ext_zve32f),
ISA_EDATA_ENTRY(zve64f, ext_zve64f),
ISA_EDATA_ENTRY(svinval, ext_svinval),

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