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target/arm: Implement GCSPUSHX

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Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251008215613.300150-51-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
2025-10-10 13:19:10 +01:00
committed by Peter Maydell
parent 0982f58db6
commit 6fb1678f90
3 changed files with 56 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/arm/cpregs-gcs.c
+17
View File
@@ -53,6 +53,19 @@ static CPAccessResult access_gcspushm(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
static CPAccessResult access_gcspushx(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
/* Trap if lock taken, and enabled. */
if (!(env->pstate & PSTATE_EXLOCK)) {
int el = arm_current_el(env);
if (env->cp15.gcscr_el[el] & GCSCR_EXLOCKEN) {
return CP_ACCESS_EXLOCK;
}
}
return CP_ACCESS_OK;
}
static const ARMCPRegInfo gcs_reginfo[] = {
{ .name = "GCSCRE0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 5, .opc2 = 2,
@@ -103,6 +116,10 @@ static const ARMCPRegInfo gcs_reginfo[] = {
{ .name = "GCSPOPM", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 7, .opc2 = 1,
.access = PL0_R, .type = ARM_CP_GCSPOPM },
{ .name = "GCSPUSHX", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 7, .opc2 = 4,
.access = PL1_W, .accessfn = access_gcspushx, .fgt = FGT_NGCSEPP,
.type = ARM_CP_GCSPUSHX },
};
void define_gcs_cpregs(ARMCPU *cpu)
target/arm/cpregs.h
+2
View File
@@ -50,6 +50,7 @@ enum {
/* Special: gcs instructions */
ARM_CP_GCSPUSHM = 0x0008,
ARM_CP_GCSPOPM = 0x0009,
ARM_CP_GCSPUSHX = 0x000a,
/* Flag: reads produce resetvalue; writes ignored. */
ARM_CP_CONST = 1 << 4,
@@ -875,6 +876,7 @@ typedef enum FGTBit {
DO_BIT(HFGITR, CPPRCTX),
DO_BIT(HFGITR, DCCVAC),
DO_REV_BIT(HFGITR, NGCSPUSHM_EL1),
DO_REV_BIT(HFGITR, NGCSEPP),
DO_BIT(HFGITR, ATS1E1A),
} FGTBit;
target/arm/tcg/translate-a64.c
+37
View File
@@ -2539,6 +2539,35 @@ static void gen_gcspopm(DisasContext *s, int rt)
tcg_gen_mov_i64(cpu_reg(s, rt), value);
}
static void gen_gcspushx(DisasContext *s)
{
TCGv_i64 gcspr = cpu_gcspr[s->current_el];
int spsr_idx = aarch64_banked_spsr_index(s->current_el);
int spsr_off = offsetof(CPUARMState, banked_spsr[spsr_idx]);
int elr_off = offsetof(CPUARMState, elr_el[s->current_el]);
int mmuidx = core_gcs_mem_index(s->mmu_idx);
MemOp mop = finalize_memop(s, MO_64 | MO_ALIGN);
TCGv_i64 addr = tcg_temp_new_i64();
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_addi_i64(addr, gcspr, -8);
tcg_gen_qemu_st_i64(cpu_reg(s, 30), addr, mmuidx, mop);
tcg_gen_ld_i64(tmp, tcg_env, spsr_off);
tcg_gen_addi_i64(addr, addr, -8);
tcg_gen_qemu_st_i64(tmp, addr, mmuidx, mop);
tcg_gen_ld_i64(tmp, tcg_env, elr_off);
tcg_gen_addi_i64(addr, addr, -8);
tcg_gen_qemu_st_i64(tmp, addr, mmuidx, mop);
tcg_gen_addi_i64(addr, addr, -8);
tcg_gen_qemu_st_i64(tcg_constant_i64(0b1001), addr, mmuidx, mop);
tcg_gen_mov_i64(gcspr, addr);
clear_pstate_bits(PSTATE_EXLOCK);
}
/*
* Look up @key, returning the cpreg, which must exist.
* Additionally, the new cpreg must also be accessible.
@@ -2856,6 +2885,14 @@ static void handle_sys(DisasContext *s, bool isread,
gen_gcspopm(s, rt);
}
return;
case ARM_CP_GCSPUSHX:
/* Choose the CONSTRAINED UNPREDICTABLE for UNDEF. */
if (rt != 31) {
unallocated_encoding(s);
} else if (s->gcs_en) {
gen_gcspushx(s);
}
return;
default:
g_assert_not_reached();
}