izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210314' into staging

Browse Source 
target-arm queue:
 * versal: Support XRAMs and XRAM controller
 * smmu: Various minor bug fixes
 * SVE emulation: fix bugs handling odd vector lengths
 * allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
 * tests/acceptance: fix orangepi-pc acceptance tests
 * hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
 * hw/arm/virt: KVM: The IPA lower bound is 32
 * npcm7xx: support MFT module
 * pl110, pxa2xx_lcd: tidy up template headers

# gpg: Signature made Sun 14 Mar 2021 13:17:43 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210314: (39 commits)
  hw/display/pxa2xx: Inline template header
  hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
  hw/display/pxa2xx: Apply brace-related coding style fixes to template header
  hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
  hw/display/pxa2xx_lcd: Remove dest_width state field
  hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
  hw/display/pl110: Remove use of BITS from pl110_template.h
  hw/display/pl110: Pull included-once parts of template header into pl110.c
  hw/display/pl110: Remove dead code for non-32-bpp surfaces
  tests/qtest: Test PWM fan RPM using MFT in PWM test
  hw/arm: Connect PWM fans in NPCM7XX boards
  hw/arm: Add MFT device to NPCM7xx Soc
  hw/misc: Add NPCM7XX MFT Module
  hw/misc: Add GPIOs for duty in NPCM7xx PWM
  hw/arm/virt: KVM: The IPA lower bound is 32
  accel: kvm: Fix kvm_type invocation
  hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
  tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests
  tests/acceptance: update sunxi kernel from armbian to 5.10.16
  tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2021-03-14 13:18:49 +00:00
parent 8e6bc6cdc8 6500ac13ff
commit 6f8a81fc29
39 changed files with 2235 additions and 937 deletions
Download Patch File Download Diff File Expand all files Collapse all files
accel/kvm/kvm-all.c
+2
View File
@@ -2068,6 +2068,8 @@ static int kvm_init(MachineState *ms)
"kvm-type",
&error_abort);
type = mc->kvm_type(ms, kvm_type);
} else if (mc->kvm_type) {
type = mc->kvm_type(ms, NULL);
}
do {
docs/system/arm/nuvoton.rst
+1 -1
View File
@@ -45,6 +45,7 @@ Supported devices
* Pulse Width Modulation (PWM)
* SMBus controller (SMBF)
* Ethernet controller (EMC)
* Tachometer
Missing devices
---------------
@@ -63,7 +64,6 @@ Missing devices
* Peripheral SPI controller (PSPI)
* SD/MMC host
* PECI interface
* Tachometer
* PCI and PCIe root complex and bridges
* VDM and MCTP support
* Serial I/O expansion
docs/system/arm/xlnx-versal-virt.rst
+1
View File
@@ -30,6 +30,7 @@ Implemented devices:
- 8 ADMA (Xilinx zDMA) channels
- 2 SD Controllers
- OCM (256KB of On Chip Memory)
- XRAM (4MB of on chip Accelerator RAM)
- DDR memory
QEMU does not yet model any other devices, including the PL and the AI Engine.
hw/arm/npcm7xx.c
+37 -8
View File
@@ -122,6 +122,14 @@ enum NPCM7xxInterrupt {
NPCM7XX_SMBUS15_IRQ,
NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
NPCM7XX_PWM1_IRQ, /* PWM module 1 */
NPCM7XX_MFT0_IRQ = 96, /* MFT module 0 */
NPCM7XX_MFT1_IRQ, /* MFT module 1 */
NPCM7XX_MFT2_IRQ, /* MFT module 2 */
NPCM7XX_MFT3_IRQ, /* MFT module 3 */
NPCM7XX_MFT4_IRQ, /* MFT module 4 */
NPCM7XX_MFT5_IRQ, /* MFT module 5 */
NPCM7XX_MFT6_IRQ, /* MFT module 6 */
NPCM7XX_MFT7_IRQ, /* MFT module 7 */
NPCM7XX_EMC2RX_IRQ = 114,
NPCM7XX_EMC2TX_IRQ,
NPCM7XX_GPIO0_IRQ = 116,
@@ -172,6 +180,18 @@ static const hwaddr npcm7xx_pwm_addr[] = {
0xf0104000,
};
/* Register base address for each MFT Module */
static const hwaddr npcm7xx_mft_addr[] = {
0xf0180000,
0xf0181000,
0xf0182000,
0xf0183000,
0xf0184000,
0xf0185000,
0xf0186000,
0xf0187000,
};
/* Direct memory-mapped access to each SMBus Module. */
static const hwaddr npcm7xx_smbus_addr[] = {
0xf0080000,
@@ -417,6 +437,10 @@ static void npcm7xx_init(Object *obj)
object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
}
for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT);
}
for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
}
@@ -603,6 +627,19 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
}
/* MFT Modules. Cannot fail. */
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_mft_addr) != ARRAY_SIZE(s->mft));
for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]);
qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in",
qdev_get_clock_out(DEVICE(&s->clk),
"apb4-clock"));
sysbus_realize(sbd, &error_abort);
sysbus_mmio_map(sbd, 0, npcm7xx_mft_addr[i]);
sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, NPCM7XX_MFT0_IRQ + i));
}
/*
* EMC Modules. Cannot fail.
* The mapping of the device to its netdev backend works as follows:
@@ -680,14 +717,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB);
create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB);
create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB);
create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB);
create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB);
create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB);
create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB);
create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
hw/arm/npcm7xx_boards.c
+99
View File
@@ -21,6 +21,7 @@
#include "hw/core/cpu.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/loader.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qemu-common.h"
@@ -116,6 +117,64 @@ static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
}
static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
NPCM7xxState *soc, const int *fan_counts)
{
SplitIRQ *splitters = machine->fan_splitter;
/*
* PWM 0~3 belong to module 0 output 0~3.
* PWM 4~7 belong to module 1 output 0~3.
*/
for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) {
for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {
int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;
DeviceState *splitter;
if (fan_counts[splitter_no] < 1) {
continue;
}
object_initialize_child(OBJECT(machine), "fan-splitter[*]",
&splitters[splitter_no], TYPE_SPLIT_IRQ);
splitter = DEVICE(&splitters[splitter_no]);
qdev_prop_set_uint16(splitter, "num-lines",
fan_counts[splitter_no]);
qdev_realize(splitter, NULL, &error_abort);
qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",
j, qdev_get_gpio_in(splitter, 0));
}
}
}
static void npcm7xx_connect_pwm_fan(NPCM7xxState *soc, SplitIRQ *splitter,
int fan_no, int output_no)
{
DeviceState *fan;
int fan_input;
qemu_irq fan_duty_gpio;
g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);
/*
* Fan 0~1 belong to module 0 input 0~1.
* Fan 2~3 belong to module 1 input 0~1.
* ...
* Fan 14~15 belong to module 7 input 0~1.
* Fan 16~17 belong to module 0 input 2~3.
* Fan 18~19 belong to module 1 input 2~3.
*/
if (fan_no < 16) {
fan = DEVICE(&soc->mft[fan_no / 2]);
fan_input = fan_no % 2;
} else {
fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);
fan_input = fan_no % 2 + 2;
}
/* Connect the Fan to PWM module */
fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);
qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);
}
static void npcm750_evb_i2c_init(NPCM7xxState *soc)
{
/* lm75 temperature sensor on SVB, tmp105 is compatible */
@@ -128,6 +187,30 @@ static void npcm750_evb_i2c_init(NPCM7xxState *soc)
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
}
static void npcm750_evb_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
{
SplitIRQ *splitter = machine->fan_splitter;
static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2};
npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);
npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);
npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);
npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);
npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);
}
static void quanta_gsj_i2c_init(NPCM7xxState *soc)
{
/* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */
@@ -142,6 +225,20 @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc)
/* TODO: Add additional i2c devices. */
}
static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
{
SplitIRQ *splitter = machine->fan_splitter;
static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0};
npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
}
static void npcm750_evb_init(MachineState *machine)
{
NPCM7xxState *soc;
@@ -153,6 +250,7 @@ static void npcm750_evb_init(MachineState *machine)
npcm7xx_load_bootrom(machine, soc);
npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
npcm750_evb_i2c_init(soc);
npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc);
npcm7xx_load_kernel(machine, soc);
}
@@ -168,6 +266,7 @@ static void quanta_gsj_init(MachineState *machine)
npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
drive_get(IF_MTD, 0, 0));
quanta_gsj_i2c_init(soc);
quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc);
npcm7xx_load_kernel(machine, soc);
}
hw/arm/smmu-common.c
+19 -13
View File
@@ -151,22 +151,28 @@ inline void
smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
uint8_t tg, uint64_t num_pages, uint8_t ttl)
{
if (ttl && (num_pages == 1)) {
/* if tg is not set we use 4KB range invalidation */
uint8_t granule = tg ? tg * 2 + 10 : 12;
if (ttl && (num_pages == 1) && (asid >= 0)) {
SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl);
g_hash_table_remove(s->iotlb, &key);
} else {
/* if tg is not set we use 4KB range invalidation */
uint8_t granule = tg ? tg * 2 + 10 : 12;
SMMUIOTLBPageInvInfo info = {
.asid = asid, .iova = iova,
.mask = (num_pages * 1 << granule) - 1};
g_hash_table_foreach_remove(s->iotlb,
smmu_hash_remove_by_asid_iova,
&info);
if (g_hash_table_remove(s->iotlb, &key)) {
return;
}
/*
* if the entry is not found, let's see if it does not
* belong to a larger IOTLB entry
*/
}
SMMUIOTLBPageInvInfo info = {
.asid = asid, .iova = iova,
.mask = (num_pages * 1 << granule) - 1};
g_hash_table_foreach_remove(s->iotlb,
smmu_hash_remove_by_asid_iova,
&info);
}
inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
hw/arm/smmu-internal.h
+5
View File
@@ -104,4 +104,9 @@ typedef struct SMMUIOTLBPageInvInfo {
uint64_t mask;
} SMMUIOTLBPageInvInfo;
typedef struct SMMUSIDRange {
uint32_t start;
uint32_t end;
} SMMUSIDRange;
#endif
hw/arm/smmuv3.c
+40 -18
View File
@@ -32,6 +32,7 @@
#include "hw/arm/smmuv3.h"
#include "smmuv3-internal.h"
#include "smmu-internal.h"
/**
* smmuv3_trigger_irq - pulse @irq if enabled and update
@@ -861,7 +862,8 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
uint16_t vmid = CMD_VMID(cmd);
bool leaf = CMD_LEAF(cmd);
uint8_t tg = CMD_TG(cmd);
hwaddr num_pages = 1;
uint64_t first_page = 0, last_page;
uint64_t num_pages = 1;
int asid = -1;
if (tg) {
@@ -874,9 +876,38 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
if (type == SMMU_CMD_TLBI_NH_VA) {
asid = CMD_ASID(cmd);
}
trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl);
/* Split invalidations into ^2 range invalidations */
last_page = num_pages - 1;
while (num_pages) {
uint8_t granule = tg * 2 + 10;
uint64_t mask, count;
mask = dma_aligned_pow2_mask(first_page, last_page, 64 - granule);
count = mask + 1;
trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, count, ttl, leaf);
smmuv3_inv_notifiers_iova(s, asid, addr, tg, count);
smmu_iotlb_inv_iova(s, asid, addr, tg, count, ttl);
num_pages -= count;
first_page += count;
addr += count * BIT_ULL(granule);
}
}
static gboolean
smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)
{
SMMUDevice *sdev = (SMMUDevice *)key;
uint32_t sid = smmu_get_sid(sdev);
SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
if (sid < sid_range->start || sid > sid_range->end) {
return false;
}
trace_smmuv3_config_cache_inv(sid);
return true;
}
static int smmuv3_cmdq_consume(SMMUv3State *s)
@@ -949,27 +980,18 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
}
case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
{
uint32_t start = CMD_SID(&cmd), end, i;
uint32_t start = CMD_SID(&cmd);
uint8_t range = CMD_STE_RANGE(&cmd);
uint64_t end = start + (1ULL << (range + 1)) - 1;
SMMUSIDRange sid_range = {start, end};
if (CMD_SSEC(&cmd)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
end = start + (1 << (range + 1)) - 1;
trace_smmuv3_cmdq_cfgi_ste_range(start, end);
for (i = start; i <= end; i++) {
IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, i);
SMMUDevice *sdev;
if (!mr) {
continue;
}
sdev = container_of(mr, SMMUDevice, iommu);
smmuv3_flush_config(sdev);
}
g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
&sid_range);
break;
}
case SMMU_CMD_CFGI_CD:
hw/arm/trace-events
+12 -12
View File
@@ -29,26 +29,26 @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s"
smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d "
smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) "Error on %s command execution: %d"
smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
smmuv3_record_event(const char *type, uint32_t sid) "%s sid=%d"
smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "SID:0x%x features:0x%x, sid_split:0x%x"
smmuv3_record_event(const char *type, uint32_t sid) "%s sid=0x%x"
smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "sid=0x%x features:0x%x, sid_split:0x%x"
smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRIx64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d"
smmuv3_get_ste(uint64_t addr) "STE addr: 0x%"PRIx64
smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=%d bypass (smmu disabled) iova:0x%"PRIx64" is_write=%d"
smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=%d STE bypass iova:0x%"PRIx64" is_write=%d"
smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=%d abort on iova:0x%"PRIx64" is_write=%d"
smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t translated, int perm) "%s sid=%d iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x"
smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x bypass (smmu disabled) iova:0x%"PRIx64" is_write=%d"
smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x STE bypass iova:0x%"PRIx64" is_write=%d"
smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x abort on iova:0x%"PRIx64" is_write=%d"
smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t translated, int perm) "%s sid=0x%x iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x"
smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
smmuv3_decode_cd(uint32_t oas) "oas=%d"
smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d"
smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d"
smmuv3_cmdq_cfgi_ste(int streamid) "streamid= 0x%x"
smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"
smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"
smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x"
smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
smmuv3_cmdq_tlbi_nh(void) ""
smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"
smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
hw/arm/virt.c
+16 -7
View File
@@ -2548,27 +2548,36 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
static int virt_kvm_type(MachineState *ms, const char *type_str)
{
VirtMachineState *vms = VIRT_MACHINE(ms);
int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
int requested_pa_size;
int max_vm_pa_size, requested_pa_size;
bool fixed_ipa;
max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
/* we freeze the memory map to compute the highest gpa */
virt_set_memmap(vms);
requested_pa_size = 64 - clz64(vms->highest_gpa);
/*
* KVM requires the IPA size to be at least 32 bits.
*/
if (requested_pa_size < 32) {
requested_pa_size = 32;
}
if (requested_pa_size > max_vm_pa_size) {
error_report("-m and ,maxmem option values "
"require an IPA range (%d bits) larger than "
"the one supported by the host (%d bits)",
requested_pa_size, max_vm_pa_size);
exit(1);
exit(1);
}
/*
* By default we return 0 which corresponds to an implicit legacy
* 40b IPA setting. Otherwise we return the actual requested PA
* logsize
* We return the requested PA log size, unless KVM only supports
* the implicit legacy 40b IPA setting, in which case the kvm_type
* must be 0.
*/
return requested_pa_size > 40 ? requested_pa_size : 0;
return fixed_ipa ? 0 : requested_pa_size;
}
static void virt_machine_class_init(ObjectClass *oc, void *data)
hw/arm/xlnx-versal.c
+36
View File
@@ -10,6 +10,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
@@ -278,6 +279,40 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic)
sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
}
static void versal_create_xrams(Versal *s, qemu_irq *pic)
{
int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl);
DeviceState *orgate;
int i;
/* XRAM IRQs get ORed into a single line. */
object_initialize_child(OBJECT(s), "xram-irq-orgate",
&s->lpd.xram.irq_orgate, TYPE_OR_IRQ);
orgate = DEVICE(&s->lpd.xram.irq_orgate);
object_property_set_int(OBJECT(orgate),
"num-lines", nr_xrams, &error_fatal);
qdev_realize(orgate, NULL, &error_fatal);
qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]);
for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) {
SysBusDevice *sbd;
MemoryRegion *mr;
object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i],
TYPE_XLNX_XRAM_CTRL);
sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]);
sysbus_realize(sbd, &error_fatal);
mr = sysbus_mmio_get_region(sbd, 0);
memory_region_add_subregion(&s->mr_ps,
MM_XRAMC + i * MM_XRAMC_SIZE, mr);
mr = sysbus_mmio_get_region(sbd, 1);
memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr);
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i));
}
}
/* This takes the board allocated linear DDR memory and creates aliases
* for each split DDR range/aperture on the Versal address map.
*/
@@ -363,6 +398,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_admas(s, pic);
versal_create_sds(s, pic);
versal_create_rtc(s, pic);
versal_create_xrams(s, pic);
versal_map_ddr(s);
versal_unimp(s);
hw/display/pl110.c
+81 -42
View File
@@ -123,16 +123,84 @@ static const unsigned char *idregs[] = {
pl111_id
};
#define BITS 8
#define COPY_PIXEL(to, from) do { *(uint32_t *)to = from; to += 4; } while (0)
#undef RGB
#define BORDER bgr
#define ORDER 0
#include "pl110_template.h"
#define BITS 15
#define ORDER 1
#include "pl110_template.h"
#define BITS 16
#define ORDER 2
#include "pl110_template.h"
#define BITS 24
#undef BORDER
#define RGB
#define BORDER rgb
#define ORDER 0
#include "pl110_template.h"
#define BITS 32
#define ORDER 1
#include "pl110_template.h"
#define ORDER 2
#include "pl110_template.h"
#undef BORDER
#undef COPY_PIXEL
static drawfn pl110_draw_fn_32[48] = {
pl110_draw_line1_lblp_bgr,
pl110_draw_line2_lblp_bgr,
pl110_draw_line4_lblp_bgr,
pl110_draw_line8_lblp_bgr,
pl110_draw_line16_555_lblp_bgr,
pl110_draw_line32_lblp_bgr,
pl110_draw_line16_lblp_bgr,
pl110_draw_line12_lblp_bgr,
pl110_draw_line1_bbbp_bgr,
pl110_draw_line2_bbbp_bgr,
pl110_draw_line4_bbbp_bgr,
pl110_draw_line8_bbbp_bgr,
pl110_draw_line16_555_bbbp_bgr,
pl110_draw_line32_bbbp_bgr,
pl110_draw_line16_bbbp_bgr,
pl110_draw_line12_bbbp_bgr,
pl110_draw_line1_lbbp_bgr,
pl110_draw_line2_lbbp_bgr,
pl110_draw_line4_lbbp_bgr,
pl110_draw_line8_lbbp_bgr,
pl110_draw_line16_555_lbbp_bgr,
pl110_draw_line32_lbbp_bgr,
pl110_draw_line16_lbbp_bgr,
pl110_draw_line12_lbbp_bgr,
pl110_draw_line1_lblp_rgb,
pl110_draw_line2_lblp_rgb,
pl110_draw_line4_lblp_rgb,
pl110_draw_line8_lblp_rgb,
pl110_draw_line16_555_lblp_rgb,
pl110_draw_line32_lblp_rgb,
pl110_draw_line16_lblp_rgb,
pl110_draw_line12_lblp_rgb,
pl110_draw_line1_bbbp_rgb,
pl110_draw_line2_bbbp_rgb,
pl110_draw_line4_bbbp_rgb,
pl110_draw_line8_bbbp_rgb,
pl110_draw_line16_555_bbbp_rgb,
pl110_draw_line32_bbbp_rgb,
pl110_draw_line16_bbbp_rgb,
pl110_draw_line12_bbbp_rgb,
pl110_draw_line1_lbbp_rgb,
pl110_draw_line2_lbbp_rgb,
pl110_draw_line4_lbbp_rgb,
pl110_draw_line8_lbbp_rgb,
pl110_draw_line16_555_lbbp_rgb,
pl110_draw_line32_lbbp_rgb,
pl110_draw_line16_lbbp_rgb,
pl110_draw_line12_lbbp_rgb,
};
static int pl110_enabled(PL110State *s)
{
@@ -144,9 +212,7 @@ static void pl110_update_display(void *opaque)
PL110State *s = (PL110State *)opaque;
SysBusDevice *sbd;
DisplaySurface *surface = qemu_console_surface(s->con);
drawfn* fntable;
drawfn fn;
int dest_width;
int src_width;
int bpp_offset;
int first;
@@ -158,33 +224,6 @@ static void pl110_update_display(void *opaque)
sbd = SYS_BUS_DEVICE(s);
switch (surface_bits_per_pixel(surface)) {
case 0:
return;
case 8:
fntable = pl110_draw_fn_8;
dest_width = 1;
break;
case 15:
fntable = pl110_draw_fn_15;
dest_width = 2;
break;
case 16:
fntable = pl110_draw_fn_16;
dest_width = 2;
break;
case 24:
fntable = pl110_draw_fn_24;
dest_width = 3;
break;
case 32:
fntable = pl110_draw_fn_32;
dest_width = 4;
break;
default:
fprintf(stderr, "pl110: Bad color depth\n");
exit(1);
}
if (s->cr & PL110_CR_BGR)
bpp_offset = 0;
else
@@ -218,12 +257,13 @@ static void pl110_update_display(void *opaque)
}
}
if (s->cr & PL110_CR_BEBO)
fn = fntable[s->bpp + 8 + bpp_offset];
else if (s->cr & PL110_CR_BEPO)
fn = fntable[s->bpp + 16 + bpp_offset];
else
fn = fntable[s->bpp + bpp_offset];
if (s->cr & PL110_CR_BEBO) {
fn = pl110_draw_fn_32[s->bpp + 8 + bpp_offset];
} else if (s->cr & PL110_CR_BEPO) {
fn = pl110_draw_fn_32[s->bpp + 16 + bpp_offset];
} else {
fn = pl110_draw_fn_32[s->bpp + bpp_offset];
}
src_width = s->cols;
switch (s->bpp) {
@@ -247,7 +287,6 @@ static void pl110_update_display(void *opaque)
src_width <<= 2;
break;
}
dest_width *= s->cols;
first = 0;
if (s->invalidate) {
framebuffer_update_memory_section(&s->fbsection,
@@ -258,7 +297,7 @@ static void pl110_update_display(void *opaque)
framebuffer_update_display(surface, &s->fbsection,
s->cols, s->rows,
src_width, dest_width, 0,
src_width, s->cols * 4, 0,
s->invalidate,
fn, s->palette,
&first, &last);
hw/display/pl110_template.h
+11 -109
View File
@@ -10,118 +10,22 @@
*/
#ifndef ORDER
#if BITS == 8
#define COPY_PIXEL(to, from) *(to++) = from
#elif BITS == 15 || BITS == 16
#define COPY_PIXEL(to, from) do { *(uint16_t *)to = from; to += 2; } while (0)
#elif BITS == 24
#define COPY_PIXEL(to, from) \
do { \
*(to++) = from; \
*(to++) = (from) >> 8; \
*(to++) = (from) >> 16; \
} while (0)
#elif BITS == 32
#define COPY_PIXEL(to, from) do { *(uint32_t *)to = from; to += 4; } while (0)
#else
#error unknown bit depth
#error "pl110_template.h is only for inclusion by pl110.c"
#endif
#undef RGB
#define BORDER bgr
#define ORDER 0
#include "pl110_template.h"
#define ORDER 1
#include "pl110_template.h"
#define ORDER 2
#include "pl110_template.h"
#undef BORDER
#define RGB
#define BORDER rgb
#define ORDER 0
#include "pl110_template.h"
#define ORDER 1
#include "pl110_template.h"
#define ORDER 2
#include "pl110_template.h"
#undef BORDER
static drawfn glue(pl110_draw_fn_,BITS)[48] =
{
glue(pl110_draw_line1_lblp_bgr,BITS),
glue(pl110_draw_line2_lblp_bgr,BITS),
glue(pl110_draw_line4_lblp_bgr,BITS),
glue(pl110_draw_line8_lblp_bgr,BITS),
glue(pl110_draw_line16_555_lblp_bgr,BITS),
glue(pl110_draw_line32_lblp_bgr,BITS),
glue(pl110_draw_line16_lblp_bgr,BITS),
glue(pl110_draw_line12_lblp_bgr,BITS),
glue(pl110_draw_line1_bbbp_bgr,BITS),
glue(pl110_draw_line2_bbbp_bgr,BITS),
glue(pl110_draw_line4_bbbp_bgr,BITS),
glue(pl110_draw_line8_bbbp_bgr,BITS),
glue(pl110_draw_line16_555_bbbp_bgr,BITS),
glue(pl110_draw_line32_bbbp_bgr,BITS),
glue(pl110_draw_line16_bbbp_bgr,BITS),
glue(pl110_draw_line12_bbbp_bgr,BITS),
glue(pl110_draw_line1_lbbp_bgr,BITS),
glue(pl110_draw_line2_lbbp_bgr,BITS),
glue(pl110_draw_line4_lbbp_bgr,BITS),
glue(pl110_draw_line8_lbbp_bgr,BITS),
glue(pl110_draw_line16_555_lbbp_bgr,BITS),
glue(pl110_draw_line32_lbbp_bgr,BITS),
glue(pl110_draw_line16_lbbp_bgr,BITS),
glue(pl110_draw_line12_lbbp_bgr,BITS),
glue(pl110_draw_line1_lblp_rgb,BITS),
glue(pl110_draw_line2_lblp_rgb,BITS),
glue(pl110_draw_line4_lblp_rgb,BITS),
glue(pl110_draw_line8_lblp_rgb,BITS),
glue(pl110_draw_line16_555_lblp_rgb,BITS),
glue(pl110_draw_line32_lblp_rgb,BITS),
glue(pl110_draw_line16_lblp_rgb,BITS),
glue(pl110_draw_line12_lblp_rgb,BITS),
glue(pl110_draw_line1_bbbp_rgb,BITS),
glue(pl110_draw_line2_bbbp_rgb,BITS),
glue(pl110_draw_line4_bbbp_rgb,BITS),
glue(pl110_draw_line8_bbbp_rgb,BITS),
glue(pl110_draw_line16_555_bbbp_rgb,BITS),
glue(pl110_draw_line32_bbbp_rgb,BITS),
glue(pl110_draw_line16_bbbp_rgb,BITS),
glue(pl110_draw_line12_bbbp_rgb,BITS),
glue(pl110_draw_line1_lbbp_rgb,BITS),
glue(pl110_draw_line2_lbbp_rgb,BITS),
glue(pl110_draw_line4_lbbp_rgb,BITS),
glue(pl110_draw_line8_lbbp_rgb,BITS),
glue(pl110_draw_line16_555_lbbp_rgb,BITS),
glue(pl110_draw_line32_lbbp_rgb,BITS),
glue(pl110_draw_line16_lbbp_rgb,BITS),
glue(pl110_draw_line12_lbbp_rgb,BITS),
};
#undef BITS
#undef COPY_PIXEL
#else
#if ORDER == 0
#define NAME glue(glue(lblp_, BORDER), BITS)
#define NAME glue(lblp_, BORDER)
#ifdef HOST_WORDS_BIGENDIAN
#define SWAP_WORDS 1
#endif
#elif ORDER == 1
#define NAME glue(glue(bbbp_, BORDER), BITS)
#define NAME glue(bbbp_, BORDER)
#ifndef HOST_WORDS_BIGENDIAN
#define SWAP_WORDS 1
#endif
#else
#define SWAP_PIXELS 1
#define NAME glue(glue(lbbp_, BORDER), BITS)
#define NAME glue(lbbp_, BORDER)
#ifdef HOST_WORDS_BIGENDIAN
#define SWAP_WORDS 1
#endif
@@ -270,14 +174,14 @@ static void glue(pl110_draw_line16_,NAME)(void *opaque, uint8_t *d, const uint8_
MSB = (data & 0x1f) << 3;
data >>= 5;
#endif
COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
LSB = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x3f) << 2;
data >>= 6;
MSB = (data & 0x1f) << 3;
data >>= 5;
COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
#undef MSB
#undef LSB
width -= 2;
@@ -307,7 +211,7 @@ static void glue(pl110_draw_line32_,NAME)(void *opaque, uint8_t *d, const uint8_
g = (data >> 16) & 0xff;
MSB = (data >> 8) & 0xff;
#endif
COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
#undef MSB
#undef LSB
width--;
@@ -338,14 +242,14 @@ static void glue(pl110_draw_line16_555_,NAME)(void *opaque, uint8_t *d, const ui
data >>= 5;
MSB = (data & 0x1f) << 3;
data >>= 5;
COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
LSB = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x1f) << 3;
data >>= 5;
MSB = (data & 0x1f) << 3;
data >>= 6;
COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
#undef MSB
#undef LSB
width -= 2;
@@ -376,14 +280,14 @@ static void glue(pl110_draw_line12_,NAME)(void *opaque, uint8_t *d, const uint8_
data >>= 4;
MSB = (data & 0xf) << 4;
data >>= 8;
COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
LSB = (data & 0xf) << 4;
data >>= 4;
g = (data & 0xf) << 4;
data >>= 4;
MSB = (data & 0xf) << 4;
data >>= 8;
COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
#undef MSB
#undef LSB
width -= 2;
@@ -395,5 +299,3 @@ static void glue(pl110_draw_line12_,NAME)(void *opaque, uint8_t *d, const uint8_
#undef NAME
#undef SWAP_WORDS
#undef ORDER
#endif
hw/display/pxa2xx_lcd.c
+450 -70
View File
File diff suppressed because it is too large Load Diff
hw/display/pxa2xx_template.h
-447
View File
@@ -1,447 +0,0 @@
/*
* Intel XScale PXA255/270 LCDC emulation.
*
* Copyright (c) 2006 Openedhand Ltd.
* Written by Andrzej Zaborowski <balrog@zabor.org>
*
* This code is licensed under the GPLv2.
*
* Framebuffer format conversion routines.
*/
# define SKIP_PIXEL(to) to += deststep
#if BITS == 8
# define COPY_PIXEL(to, from) do { *to = from; SKIP_PIXEL(to); } while (0)
#elif BITS == 15 || BITS == 16
# define COPY_PIXEL(to, from) \
do { \
*(uint16_t *) to = from; \
SKIP_PIXEL(to); \
} while (0)
#elif BITS == 24
# define COPY_PIXEL(to, from) \
do { \
*(uint16_t *) to = from; \
*(to + 2) = (from) >> 16; \
SKIP_PIXEL(to); \
} while (0)
#elif BITS == 32
# define COPY_PIXEL(to, from) \
do { \
*(uint32_t *) to = from; \
SKIP_PIXEL(to); \
} while (0)
#else
# error unknown bit depth
#endif
#ifdef HOST_WORDS_BIGENDIAN
# define SWAP_WORDS 1
#endif
#define FN_2(x) FN(x + 1) FN(x)
#define FN_4(x) FN_2(x + 2) FN_2(x)
static void glue(pxa2xx_draw_line2_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t *palette = opaque;
uint32_t data;
while (width > 0) {
data = *(uint32_t *) src;
#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 2)) & 3]);
#ifdef SWAP_WORDS
FN_4(12)
FN_4(8)
FN_4(4)
FN_4(0)
#else
FN_4(0)
FN_4(4)
FN_4(8)
FN_4(12)
#endif
#undef FN
width -= 16;
src += 4;
}
}
static void glue(pxa2xx_draw_line4_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t *palette = opaque;
uint32_t data;
while (width > 0) {
data = *(uint32_t *) src;
#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 4)) & 0xf]);
#ifdef SWAP_WORDS
FN_2(6)
FN_2(4)
FN_2(2)
FN_2(0)
#else
FN_2(0)
FN_2(2)
FN_2(4)
FN_2(6)
#endif
#undef FN
width -= 8;
src += 4;
}
}
static void glue(pxa2xx_draw_line8_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t *palette = opaque;
uint32_t data;
while (width > 0) {
data = *(uint32_t *) src;
#define FN(x) COPY_PIXEL(dest, palette[(data >> (x)) & 0xff]);
#ifdef SWAP_WORDS
FN(24)
FN(16)
FN(8)
FN(0)
#else
FN(0)
FN(8)
FN(16)
FN(24)
#endif
#undef FN
width -= 4;
src += 4;
}
}
static void glue(pxa2xx_draw_line16_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x1f) << 3;
data >>= 5;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x1f) << 3;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 2;
src += 4;
}
}
static void glue(pxa2xx_draw_line16t_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x1f) << 3;
data >>= 5;
r = (data & 0x1f) << 3;
data >>= 5;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
data >>= 1;
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x1f) << 3;
data >>= 5;
r = (data & 0x1f) << 3;
data >>= 5;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 2;
src += 4;
}
}
static void glue(pxa2xx_draw_line18_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x3f) << 2;
data >>= 6;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x3f) << 2;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
/* The wicked packed format */
static void glue(pxa2xx_draw_line18p_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data[3];
unsigned int r, g, b;
while (width > 0) {
data[0] = *(uint32_t *) src;
src += 4;
data[1] = *(uint32_t *) src;
src += 4;
data[2] = *(uint32_t *) src;
src += 4;
#ifdef SWAP_WORDS
data[0] = bswap32(data[0]);
data[1] = bswap32(data[1]);
data[2] = bswap32(data[2]);
#endif
b = (data[0] & 0x3f) << 2;
data[0] >>= 6;
g = (data[0] & 0x3f) << 2;
data[0] >>= 6;
r = (data[0] & 0x3f) << 2;
data[0] >>= 12;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
b = (data[0] & 0x3f) << 2;
data[0] >>= 6;
g = ((data[1] & 0xf) << 4) | (data[0] << 2);
data[1] >>= 4;
r = (data[1] & 0x3f) << 2;
data[1] >>= 12;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
b = (data[1] & 0x3f) << 2;
data[1] >>= 6;
g = (data[1] & 0x3f) << 2;
data[1] >>= 6;
r = ((data[2] & 0x3) << 6) | (data[1] << 2);
data[2] >>= 8;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
b = (data[2] & 0x3f) << 2;
data[2] >>= 6;
g = (data[2] & 0x3f) << 2;
data[2] >>= 6;
r = data[2] << 2;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 4;
}
}
static void glue(pxa2xx_draw_line19_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x3f) << 2;
data >>= 6;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x3f) << 2;
data >>= 6;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
/* The wicked packed format */
static void glue(pxa2xx_draw_line19p_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data[3];
unsigned int r, g, b;
while (width > 0) {
data[0] = *(uint32_t *) src;
src += 4;
data[1] = *(uint32_t *) src;
src += 4;
data[2] = *(uint32_t *) src;
src += 4;
# ifdef SWAP_WORDS
data[0] = bswap32(data[0]);
data[1] = bswap32(data[1]);
data[2] = bswap32(data[2]);
# endif
b = (data[0] & 0x3f) << 2;
data[0] >>= 6;
g = (data[0] & 0x3f) << 2;
data[0] >>= 6;
r = (data[0] & 0x3f) << 2;
data[0] >>= 6;
if (data[0] & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
data[0] >>= 6;
b = (data[0] & 0x3f) << 2;
data[0] >>= 6;
g = ((data[1] & 0xf) << 4) | (data[0] << 2);
data[1] >>= 4;
r = (data[1] & 0x3f) << 2;
data[1] >>= 6;
if (data[1] & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
data[1] >>= 6;
b = (data[1] & 0x3f) << 2;
data[1] >>= 6;
g = (data[1] & 0x3f) << 2;
data[1] >>= 6;
r = ((data[2] & 0x3) << 6) | (data[1] << 2);
data[2] >>= 2;
if (data[2] & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
data[2] >>= 6;
b = (data[2] & 0x3f) << 2;
data[2] >>= 6;
g = (data[2] & 0x3f) << 2;
data[2] >>= 6;
r = data[2] << 2;
data[2] >>= 6;
if (data[2] & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 4;
}
}
static void glue(pxa2xx_draw_line24_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = data & 0xff;
data >>= 8;
g = data & 0xff;
data >>= 8;
r = data & 0xff;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
static void glue(pxa2xx_draw_line24t_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x7f) << 1;
data >>= 7;
g = data & 0xff;
data >>= 8;
r = data & 0xff;
data >>= 8;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
static void glue(pxa2xx_draw_line25_, BITS)(void *opaque,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = data & 0xff;
data >>= 8;
g = data & 0xff;
data >>= 8;
r = data & 0xff;
data >>= 8;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
/* Overlay planes disabled, no transparency */
static drawfn glue(pxa2xx_draw_fn_, BITS)[16] =
{
[0 ... 0xf] = NULL,
[pxa_lcdc_2bpp] = glue(pxa2xx_draw_line2_, BITS),
[pxa_lcdc_4bpp] = glue(pxa2xx_draw_line4_, BITS),
[pxa_lcdc_8bpp] = glue(pxa2xx_draw_line8_, BITS),
[pxa_lcdc_16bpp] = glue(pxa2xx_draw_line16_, BITS),
[pxa_lcdc_18bpp] = glue(pxa2xx_draw_line18_, BITS),
[pxa_lcdc_18pbpp] = glue(pxa2xx_draw_line18p_, BITS),
[pxa_lcdc_24bpp] = glue(pxa2xx_draw_line24_, BITS),
};
/* Overlay planes enabled, transparency used */
static drawfn glue(glue(pxa2xx_draw_fn_, BITS), t)[16] =
{
[0 ... 0xf] = NULL,
[pxa_lcdc_4bpp] = glue(pxa2xx_draw_line4_, BITS),
[pxa_lcdc_8bpp] = glue(pxa2xx_draw_line8_, BITS),
[pxa_lcdc_16bpp] = glue(pxa2xx_draw_line16t_, BITS),
[pxa_lcdc_19bpp] = glue(pxa2xx_draw_line19_, BITS),
[pxa_lcdc_19pbpp] = glue(pxa2xx_draw_line19p_, BITS),
[pxa_lcdc_24bpp] = glue(pxa2xx_draw_line24t_, BITS),
[pxa_lcdc_25bpp] = glue(pxa2xx_draw_line25_, BITS),
};
#undef BITS
#undef COPY_PIXEL
#undef SKIP_PIXEL
#ifdef SWAP_WORDS
# undef SWAP_WORDS
#endif
hw/i386/intel_iommu.c
+9 -23
View File
@@ -35,6 +35,7 @@
#include "hw/i386/x86-iommu.h"
#include "hw/pci-host/q35.h"
#include "sysemu/kvm.h"
#include "sysemu/dma.h"
#include "sysemu/sysemu.h"
#include "hw/i386/apic_internal.h"
#include "kvm/kvm_i386.h"
@@ -1884,6 +1885,8 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
case 3:
mask = 7; /* Mask bit 2:0 in the SID field */
break;
default:
g_assert_not_reached();
}
mask = ~mask;
@@ -3453,24 +3456,6 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
return vtd_dev_as;
}
static uint64_t get_naturally_aligned_size(uint64_t start,
uint64_t size, int gaw)
{
uint64_t max_mask = 1ULL << gaw;
uint64_t alignment = start ? start & -start : max_mask;
alignment = MIN(alignment, max_mask);
size = MIN(size, max_mask);
if (alignment <= size) {
/* Increase the alignment of start */
return alignment;
} else {
/* Find the largest page mask from size */
return 1ULL << (63 - clz64(size));
}
}
/* Unmap the whole range in the notifier's scope. */
static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
{
@@ -3499,13 +3484,14 @@ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
while (remain >= VTD_PAGE_SIZE) {
IOMMUTLBEvent event;
uint64_t mask = get_naturally_aligned_size(start, remain, s->aw_bits);
uint64_t mask = dma_aligned_pow2_mask(start, end, s->aw_bits);
uint64_t size = mask + 1;
assert(mask);
assert(size);
event.type = IOMMU_NOTIFIER_UNMAP;
event.entry.iova = start;
event.entry.addr_mask = mask - 1;
event.entry.addr_mask = mask;
event.entry.target_as = &address_space_memory;
event.entry.perm = IOMMU_NONE;
/* This field is meaningless for unmap */
@@ -3513,8 +3499,8 @@ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
memory_region_notify_iommu_one(n, &event);
start += mask;
remain -= mask;
start += size;
remain -= size;
}
assert(!remain);
hw/misc/meson.build
+2
View File
@@ -65,6 +65,7 @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
'npcm7xx_clk.c',
'npcm7xx_gcr.c',
'npcm7xx_mft.c',
'npcm7xx_pwm.c',
'npcm7xx_rng.c',
))
@@ -85,6 +86,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
))
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-xramc.c'))
softmmu_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
softmmu_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
softmmu_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))
hw/misc/npcm7xx_mft.c
+540
View File
File diff suppressed because it is too large Load Diff
hw/misc/npcm7xx_pwm.c
+4
View File
@@ -139,6 +139,7 @@ static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
p->index, p->duty, duty);
p->duty = duty;
qemu_set_irq(p->module->duty_gpio_out[p->index], p->duty);
}
}
@@ -483,6 +484,7 @@ static void npcm7xx_pwm_init(Object *obj)
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
int i;
QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->pwm) != NPCM7XX_PWM_PER_MODULE);
for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
NPCM7xxPWM *p = &s->pwm[i];
p->module = s;
@@ -501,6 +503,8 @@ static void npcm7xx_pwm_init(Object *obj)
object_property_add_uint32_ptr(obj, "duty[*]",
&s->pwm[i].duty, OBJ_PROP_FLAG_READ);
}
qdev_init_gpio_out_named(DEVICE(s), s->duty_gpio_out,
"duty-gpio-out", NPCM7XX_PWM_PER_MODULE);
}
static const VMStateDescription vmstate_npcm7xx_pwm = {
hw/misc/trace-events
+8
View File
@@ -116,6 +116,14 @@ npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
# npcm7xx_mft.c
npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
npcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
npcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32
npcm7xx_mft_capture(const char *name, int irq_level) "%s: level: %d"
npcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64
npcm7xx_mft_set_duty(const char *name, int n, int value) "%s[%d]: %d"
# npcm7xx_rng.c
npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"

Some files were not shown because too many files have changed in this diff Show More