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Merge tag 'pull-hex-20230421' of https://github.com/quic/qemu into staging

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Hexagon update

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* tag 'pull-hex-20230421' of https://github.com/quic/qemu:
  Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions
  Hexagon (target/hexagon) Remove unused slot variable in helpers
  Hexagon (tests/tcg/hexagon) Move HVX test infra to header file
  Hexagon (target/hexagon) Updates to USR should use get_result_gpr
  Hexagon (target/hexagon) Add overrides for count trailing zeros/ones
  Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_stores
  Hexagon (target/hexagon) Remove redundant/unused macros
  Use black code style for python scripts
  Use f-strings in python scripts
  Hexagon (translate.c): avoid redundant PC updates on COF

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2023-04-22 08:31:38 +01:00
parent 1cc6e1a201 a305a17039
commit 6dd0621489
28 changed files with 1662 additions and 1350 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/hexagon/dectree.py
+224 -172
View File
File diff suppressed because it is too large Load Diff
target/hexagon/gen_analyze_funcs.py
+104 -122
View File
@@ -22,162 +22,141 @@ import re
import string
import hex_common
##
## Helpers for gen_analyze_func
##
def is_predicated(tag):
return 'A_CONDEXEC' in hex_common.attribdict[tag]
return "A_CONDEXEC" in hex_common.attribdict[tag]
def analyze_opn_old(f, tag, regtype, regid, regno):
regN = "%s%sN" % (regtype, regid)
regN = f"{regtype}{regid}N"
predicated = "true" if is_predicated(tag) else "false"
if (regtype == "R"):
if (regid in {"ss", "tt"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"dd", "ee", "xx", "yy"}):
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
f.write(" ctx_log_reg_write_pair(ctx, %s, %s);\n" % \
(regN, predicated))
elif (regid in {"s", "t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"d", "e", "x", "y"}):
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
f.write(" ctx_log_reg_write(ctx, %s, %s);\n" % \
(regN, predicated))
if regtype == "R":
if regid in {"ss", "tt"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"dd", "ee", "xx", "yy"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
elif regid in {"s", "t", "u", "v"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"d", "e", "x", "y"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid in {"s", "t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"d", "e", "x"}):
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
f.write(" ctx_log_pred_write(ctx, %s);\n" % (regN))
elif regtype == "P":
if regid in {"s", "t", "u", "v"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"d", "e", "x"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_pred_write(ctx, {regN});\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "C"):
if (regid == "ss"):
f.write("// const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
elif (regid == "dd"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
f.write(" ctx_log_reg_write_pair(ctx, %s, %s);\n" % \
(regN, predicated))
elif (regid == "s"):
f.write("// const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
elif (regid == "d"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
f.write(" ctx_log_reg_write(ctx, %s, %s);\n" % \
(regN, predicated))
elif regtype == "C":
if regid == "ss":
f.write(
f"// const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n"
)
elif regid == "dd":
f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
elif regid == "s":
f.write(
f"// const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n"
)
elif regid == "d":
f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "M"):
if (regid == "u"):
f.write("// const int %s = insn->regno[%d];\n"% \
(regN, regno))
elif regtype == "M":
if regid == "u":
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "V"):
elif regtype == "V":
newv = "EXT_DFL"
if (hex_common.is_new_result(tag)):
if hex_common.is_new_result(tag):
newv = "EXT_NEW"
elif (hex_common.is_tmp_result(tag)):
elif hex_common.is_tmp_result(tag):
newv = "EXT_TMP"
if (regid in {"dd", "xx"}):
f.write(" const int %s = insn->regno[%d];\n" %\
(regN, regno))
f.write(" ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \
(regN, newv, predicated))
elif (regid in {"uu", "vv"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"s", "u", "v", "w"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"d", "x", "y"}):
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(" ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \
(regN, newv, predicated))
if regid in {"dd", "xx"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(
f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, " f"{predicated});\n"
)
elif regid in {"uu", "vv"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"s", "u", "v", "w"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"d", "x", "y"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, " f"{predicated});\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
if (regid in {"d", "e", "x"}):
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(" ctx_log_qreg_write(ctx, %s);\n" % (regN))
elif (regid in {"s", "t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif regtype == "Q":
if regid in {"d", "e", "x"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_qreg_write(ctx, {regN});\n")
elif regid in {"s", "t", "u", "v"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "G"):
if (regid in {"dd"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"d"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"ss"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"s"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif regtype == "G":
if regid in {"dd"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"d"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"ss"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"s"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "S"):
if (regid in {"dd"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"d"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"ss"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"s"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif regtype == "S":
if regid in {"dd"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"d"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"ss"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"s"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)
def analyze_opn_new(f, tag, regtype, regid, regno):
regN = "%s%sN" % (regtype, regid)
if (regtype == "N"):
if (regid in {"s", "t"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
regN = f"{regtype}{regid}N"
if regtype == "N":
if regid in {"s", "t"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid in {"t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif regtype == "P":
if regid in {"t", "u", "v"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "O"):
if (regid == "s"):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif regtype == "O":
if regid == "s":
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)
def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
if (hex_common.is_pair(regid)):
if hex_common.is_pair(regid):
analyze_opn_old(f, tag, regtype, regid, i)
elif (hex_common.is_single(regid)):
elif hex_common.is_single(regid):
if hex_common.is_old_val(regtype, regid, tag):
analyze_opn_old(f,tag, regtype, regid, i)
analyze_opn_old(f, tag, regtype, regid, i)
elif hex_common.is_new_val(regtype, regid, tag):
analyze_opn_new(f, tag, regtype, regid, i)
else:
@@ -185,6 +164,7 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
else:
print("Bad register parse: ", regtype, regid, toss, numregs)
##
## Generate the code to analyze the instruction
## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
@@ -199,25 +179,26 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
## }
##
def gen_analyze_func(f, tag, regs, imms):
f.write("static void analyze_%s(DisasContext *ctx)\n" %tag)
f.write('{\n')
f.write(f"static void analyze_{tag}(DisasContext *ctx)\n")
f.write("{\n")
f.write(" Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
i=0
i = 0
## Analyze all the registers
for regtype, regid, toss, numregs in regs:
analyze_opn(f, tag, regtype, regid, toss, numregs, i)
i += 1
has_generated_helper = (not hex_common.skip_qemu_helper(tag) and
not hex_common.is_idef_parser_enabled(tag))
if (has_generated_helper and
'A_SCALAR_LOAD' in hex_common.attribdict[tag]):
has_generated_helper = not hex_common.skip_qemu_helper(
tag
) and not hex_common.is_idef_parser_enabled(tag)
if has_generated_helper and "A_SCALAR_LOAD" in hex_common.attribdict[tag]:
f.write(" ctx->need_pkt_has_store_s1 = true;\n")
f.write("}\n\n")
def main():
hex_common.read_semantics_file(sys.argv[1])
hex_common.read_attribs_file(sys.argv[2])
@@ -239,7 +220,7 @@ def main():
tagregs = hex_common.get_tagregs()
tagimms = hex_common.get_tagimms()
with open(sys.argv[-1], 'w') as f:
with open(sys.argv[-1], "w") as f:
f.write("#ifndef HEXAGON_TCG_FUNCS_H\n")
f.write("#define HEXAGON_TCG_FUNCS_H\n\n")
@@ -248,5 +229,6 @@ def main():
f.write("#endif /* HEXAGON_TCG_FUNCS_H */\n")
if __name__ == "__main__":
main()
target/hexagon/gen_helper_funcs.py
+203 -159
View File
File diff suppressed because it is too large Load Diff
target/hexagon/gen_helper_protos.py
+95 -74
View File
@@ -26,32 +26,34 @@ import hex_common
## Helpers for gen_helper_prototype
##
def_helper_types = {
'N' : 's32',
'O' : 's32',
'P' : 's32',
'M' : 's32',
'C' : 's32',
'R' : 's32',
'V' : 'ptr',
'Q' : 'ptr'
"N": "s32",
"O": "s32",
"P": "s32",
"M": "s32",
"C": "s32",
"R": "s32",
"V": "ptr",
"Q": "ptr",
}
def_helper_types_pair = {
'R' : 's64',
'C' : 's64',
'S' : 's64',
'G' : 's64',
'V' : 'ptr',
'Q' : 'ptr'
"R": "s64",
"C": "s64",
"S": "s64",
"G": "s64",
"V": "ptr",
"Q": "ptr",
}
def gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i):
if (hex_common.is_pair(regid)):
f.write(", %s" % (def_helper_types_pair[regtype]))
elif (hex_common.is_single(regid)):
f.write(", %s" % (def_helper_types[regtype]))
if hex_common.is_pair(regid):
f.write(f", {def_helper_types_pair[regtype]}")
elif hex_common.is_single(regid):
f.write(f", {def_helper_types[regtype]}")
else:
print("Bad register parse: ",regtype,regid,toss,numregs)
print("Bad register parse: ", regtype, regid, toss, numregs)
##
## Generate the DEF_HELPER prototype for an instruction
@@ -66,90 +68,108 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
numresults = 0
numscalarresults = 0
numscalarreadwrite = 0
for regtype,regid,toss,numregs in regs:
if (hex_common.is_written(regid)):
for regtype, regid, toss, numregs in regs:
if hex_common.is_written(regid):
numresults += 1
if (hex_common.is_scalar_reg(regtype)):
if hex_common.is_scalar_reg(regtype):
numscalarresults += 1
if (hex_common.is_readwrite(regid)):
if (hex_common.is_scalar_reg(regtype)):
if hex_common.is_readwrite(regid):
if hex_common.is_scalar_reg(regtype):
numscalarreadwrite += 1
if (numscalarresults > 1):
if numscalarresults > 1:
## The helper is bogus when there is more than one result
f.write('DEF_HELPER_1(%s, void, env)\n' % tag)
f.write(f"DEF_HELPER_1({tag}, void, env)\n")
else:
## Figure out how many arguments the helper will take
if (numscalarresults == 0):
def_helper_size = len(regs)+len(imms)+numscalarreadwrite+1
if hex_common.need_pkt_has_multi_cof(tag): def_helper_size += 1
if hex_common.need_part1(tag): def_helper_size += 1
if hex_common.need_slot(tag): def_helper_size += 1
if hex_common.need_PC(tag): def_helper_size += 1
if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1
f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
if numscalarresults == 0:
def_helper_size = len(regs) + len(imms) + numscalarreadwrite + 1
if hex_common.need_pkt_has_multi_cof(tag):
def_helper_size += 1
if hex_common.need_part1(tag):
def_helper_size += 1
if hex_common.need_slot(tag):
def_helper_size += 1
if hex_common.need_PC(tag):
def_helper_size += 1
if hex_common.helper_needs_next_PC(tag):
def_helper_size += 1
if hex_common.need_condexec_reg(tag, regs):
def_helper_size += 1
f.write(f"DEF_HELPER_{def_helper_size}({tag}")
## The return type is void
f.write(', void' )
f.write(", void")
else:
def_helper_size = len(regs)+len(imms)+numscalarreadwrite
if hex_common.need_pkt_has_multi_cof(tag): def_helper_size += 1
if hex_common.need_part1(tag): def_helper_size += 1
if hex_common.need_slot(tag): def_helper_size += 1
if hex_common.need_PC(tag): def_helper_size += 1
if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1
if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
def_helper_size = len(regs) + len(imms) + numscalarreadwrite
if hex_common.need_pkt_has_multi_cof(tag):
def_helper_size += 1
if hex_common.need_part1(tag):
def_helper_size += 1
if hex_common.need_slot(tag):
def_helper_size += 1
if hex_common.need_PC(tag):
def_helper_size += 1
if hex_common.need_condexec_reg(tag, regs):
def_helper_size += 1
if hex_common.helper_needs_next_PC(tag):
def_helper_size += 1
f.write(f"DEF_HELPER_{def_helper_size}({tag}")
## Generate the qemu DEF_HELPER type for each result
## Iterate over this list twice
## - Emit the scalar result
## - Emit the vector result
i=0
for regtype,regid,toss,numregs in regs:
if (hex_common.is_written(regid)):
if (not hex_common.is_hvx_reg(regtype)):
i = 0
for regtype, regid, toss, numregs in regs:
if hex_common.is_written(regid):
if not hex_common.is_hvx_reg(regtype):
gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
i += 1
## Put the env between the outputs and inputs
f.write(', env' )
f.write(", env")
i += 1
# Second pass
for regtype,regid,toss,numregs in regs:
if (hex_common.is_written(regid)):
if (hex_common.is_hvx_reg(regtype)):
for regtype, regid, toss, numregs in regs:
if hex_common.is_written(regid):
if hex_common.is_hvx_reg(regtype):
gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
i += 1
## For conditional instructions, we pass in the destination register
if 'A_CONDEXEC' in hex_common.attribdict[tag]:
if "A_CONDEXEC" in hex_common.attribdict[tag]:
for regtype, regid, toss, numregs in regs:
if (hex_common.is_writeonly(regid) and
not hex_common.is_hvx_reg(regtype)):
if hex_common.is_writeonly(regid) and not hex_common.is_hvx_reg(
regtype
):
gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
i += 1
## Generate the qemu type for each input operand (regs and immediates)
for regtype,regid,toss,numregs in regs:
if (hex_common.is_read(regid)):
if (hex_common.is_hvx_reg(regtype) and
hex_common.is_readwrite(regid)):
for regtype, regid, toss, numregs in regs:
if hex_common.is_read(regid):
if hex_common.is_hvx_reg(regtype) and hex_common.is_readwrite(regid):
continue
gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
i += 1
for immlett,bits,immshift in imms:
for immlett, bits, immshift in imms:
f.write(", s32")
## Add the arguments for the instruction pkt_has_multi_cof, slot and
## part1 (if needed)
if hex_common.need_pkt_has_multi_cof(tag): f.write(', i32')
if hex_common.need_PC(tag): f.write(', i32')
if hex_common.helper_needs_next_PC(tag): f.write(', i32')
if hex_common.need_slot(tag): f.write(', i32' )
if hex_common.need_part1(tag): f.write(' , i32' )
f.write(')\n')
if hex_common.need_pkt_has_multi_cof(tag):
f.write(", i32")
if hex_common.need_PC(tag):
f.write(", i32")
if hex_common.helper_needs_next_PC(tag):
f.write(", i32")
if hex_common.need_slot(tag):
f.write(", i32")
if hex_common.need_part1(tag):
f.write(" , i32")
f.write(")\n")
def main():
hex_common.read_semantics_file(sys.argv[1])
@@ -173,28 +193,29 @@ def main():
tagimms = hex_common.get_tagimms()
output_file = sys.argv[-1]
with open(output_file, 'w') as f:
with open(output_file, "w") as f:
for tag in hex_common.tags:
## Skip the priv instructions
if ( "A_PRIV" in hex_common.attribdict[tag] ) :
if "A_PRIV" in hex_common.attribdict[tag]:
continue
## Skip the guest instructions
if ( "A_GUEST" in hex_common.attribdict[tag] ) :
if "A_GUEST" in hex_common.attribdict[tag]:
continue
## Skip the diag instructions
if ( tag == "Y6_diag" ) :
if tag == "Y6_diag":
continue
if ( tag == "Y6_diag0" ) :
if tag == "Y6_diag0":
continue
if ( tag == "Y6_diag1" ) :
if tag == "Y6_diag1":
continue
if ( hex_common.skip_qemu_helper(tag) ):
if hex_common.skip_qemu_helper(tag):
continue
if ( hex_common.is_idef_parser_enabled(tag) ):
if hex_common.is_idef_parser_enabled(tag):
continue
gen_helper_prototype(f, tag, tagregs, tagimms)
if __name__ == "__main__":
main()
target/hexagon/gen_idef_parser_funcs.py
+51 -34
View File
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
## Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
## Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -24,6 +24,7 @@ from io import StringIO
import hex_common
##
## Generate code to be fed to the idef_parser
##
@@ -48,83 +49,99 @@ def main():
tagregs = hex_common.get_tagregs()
tagimms = hex_common.get_tagimms()
with open(sys.argv[3], 'w') as f:
with open(sys.argv[3], "w") as f:
f.write('#include "macros.inc"\n\n')
for tag in hex_common.tags:
## Skip the priv instructions
if ( "A_PRIV" in hex_common.attribdict[tag] ) :
if "A_PRIV" in hex_common.attribdict[tag]:
continue
## Skip the guest instructions
if ( "A_GUEST" in hex_common.attribdict[tag] ) :
if "A_GUEST" in hex_common.attribdict[tag]:
continue
## Skip instructions that saturate in a ternary expression
if ( tag in {'S2_asr_r_r_sat', 'S2_asl_r_r_sat'} ) :
if tag in {"S2_asr_r_r_sat", "S2_asl_r_r_sat"}:
continue
## Skip instructions using switch
if ( tag in {'S4_vrcrotate_acc', 'S4_vrcrotate'} ) :
if tag in {"S4_vrcrotate_acc", "S4_vrcrotate"}:
continue
## Skip trap instructions
if ( tag in {'J2_trap0', 'J2_trap1'} ) :
if tag in {"J2_trap0", "J2_trap1"}:
continue
## Skip 128-bit instructions
if ( tag in {'A7_croundd_ri', 'A7_croundd_rr'} ) :
if tag in {"A7_croundd_ri", "A7_croundd_rr"}:
continue
if ( tag in {'M7_wcmpyrw', 'M7_wcmpyrwc',
'M7_wcmpyiw', 'M7_wcmpyiwc',
'M7_wcmpyrw_rnd', 'M7_wcmpyrwc_rnd',
'M7_wcmpyiw_rnd', 'M7_wcmpyiwc_rnd'} ) :
if tag in {
"M7_wcmpyrw",
"M7_wcmpyrwc",
"M7_wcmpyiw",
"M7_wcmpyiwc",
"M7_wcmpyrw_rnd",
"M7_wcmpyrwc_rnd",
"M7_wcmpyiw_rnd",
"M7_wcmpyiwc_rnd",
}:
continue
## Skip interleave/deinterleave instructions
if ( tag in {'S2_interleave', 'S2_deinterleave'} ) :
if tag in {"S2_interleave", "S2_deinterleave"}:
continue
## Skip instructions using bit reverse
if ( tag in {'S2_brev', 'S2_brevp', 'S2_ct0', 'S2_ct1',
'S2_ct0p', 'S2_ct1p', 'A4_tlbmatch'} ) :
if tag in {
"S2_brev",
"S2_brevp",
"S2_ct0",
"S2_ct1",
"S2_ct0p",
"S2_ct1p",
"A4_tlbmatch",
}:
continue
## Skip other unsupported instructions
if ( tag == 'S2_cabacdecbin' or tag == 'A5_ACS' ) :
if tag == "S2_cabacdecbin" or tag == "A5_ACS":
continue
if ( tag.startswith('Y') ) :
if tag.startswith("Y"):
continue
if ( tag.startswith('V6_') ) :
if tag.startswith("V6_"):
continue
if ( tag.startswith('F') ) :
if tag.startswith("F"):
continue
if ( tag.endswith('_locked') ) :
if tag.endswith("_locked"):
continue
if ( "A_COF" in hex_common.attribdict[tag] ) :
if "A_COF" in hex_common.attribdict[tag]:
continue
regs = tagregs[tag]
imms = tagimms[tag]
arguments = []
for regtype,regid,toss,numregs in regs:
for regtype, regid, toss, numregs in regs:
prefix = "in " if hex_common.is_read(regid) else ""
is_pair = hex_common.is_pair(regid)
is_single_old = (hex_common.is_single(regid)
and hex_common.is_old_val(regtype, regid, tag))
is_single_new = (hex_common.is_single(regid)
and hex_common.is_new_val(regtype, regid, tag))
is_single_old = hex_common.is_single(regid) and hex_common.is_old_val(
regtype, regid, tag
)
is_single_new = hex_common.is_single(regid) and hex_common.is_new_val(
regtype, regid, tag
)
if is_pair or is_single_old:
arguments.append("%s%s%sV" % (prefix, regtype, regid))
arguments.append(f"{prefix}{regtype}{regid}V")
elif is_single_new:
arguments.append("%s%s%sN" % (prefix, regtype, regid))
arguments.append(f"{prefix}{regtype}{regid}N")
else:
print("Bad register parse: ",regtype,regid,toss,numregs)
print("Bad register parse: ", regtype, regid, toss, numregs)
for immlett,bits,immshift in imms:
for immlett, bits, immshift in imms:
arguments.append(hex_common.imm_name(immlett))
f.write("%s(%s) {\n" % (tag, ", ".join(arguments)))
f.write(" ");
f.write(f"{tag}({', '.join(arguments)}) {{\n")
f.write(" ")
if hex_common.need_ea(tag):
f.write("size4u_t EA; ");
f.write("%s\n" % hex_common.semdict[tag])
f.write("size4u_t EA; ")
f.write(f"{hex_common.semdict[tag]}\n")
f.write("}\n\n")
if __name__ == "__main__":
main()
target/hexagon/gen_op_attribs.py
+8 -4
View File
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@ import re
import string
import hex_common
def main():
hex_common.read_semantics_file(sys.argv[1])
hex_common.read_attribs_file(sys.argv[2])
@@ -30,10 +31,13 @@ def main():
##
## Generate all the attributes associated with each instruction
##
with open(sys.argv[3], 'w') as f:
with open(sys.argv[3], "w") as f:
for tag in hex_common.tags:
f.write('OP_ATTRIB(%s,ATTRIBS(%s))\n' % \
(tag, ','.join(sorted(hex_common.attribdict[tag]))))
f.write(
f"OP_ATTRIB({tag},ATTRIBS("
f'{",".join(sorted(hex_common.attribdict[tag]))}))\n'
)
if __name__ == "__main__":
main()
target/hexagon/gen_op_regs.py
+46 -33
View File
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -22,21 +22,25 @@ import re
import string
import hex_common
##
## Generate the register and immediate operands for each instruction
##
def calculate_regid_reg(tag):
def letter_inc(x): return chr(ord(x)+1)
ordered_implregs = [ 'SP','FP','LR' ]
srcdst_lett = 'X'
src_lett = 'S'
dst_lett = 'D'
def letter_inc(x):
return chr(ord(x) + 1)
ordered_implregs = ["SP", "FP", "LR"]
srcdst_lett = "X"
src_lett = "S"
dst_lett = "D"
retstr = ""
mapdict = {}
for reg in ordered_implregs:
reg_rd = 0
reg_wr = 0
if ('A_IMPLICIT_WRITES_'+reg) in hex_common.attribdict[tag]: reg_wr = 1
if ("A_IMPLICIT_WRITES_" + reg) in hex_common.attribdict[tag]:
reg_wr = 1
if reg_rd and reg_wr:
retstr += srcdst_lett
mapdict[srcdst_lett] = reg
@@ -49,16 +53,19 @@ def calculate_regid_reg(tag):
retstr += dst_lett
mapdict[dst_lett] = reg
dst_lett = letter_inc(dst_lett)
return retstr,mapdict
return retstr, mapdict
def calculate_regid_letters(tag):
retstr,mapdict = calculate_regid_reg(tag)
retstr, mapdict = calculate_regid_reg(tag)
return retstr
def strip_reg_prefix(x):
y=x.replace('UREG.','')
y=y.replace('MREG.','')
return y.replace('GREG.','')
y = x.replace("UREG.", "")
y = y.replace("MREG.", "")
return y.replace("GREG.", "")
def main():
hex_common.read_semantics_file(sys.argv[1])
@@ -66,45 +73,51 @@ def main():
tagregs = hex_common.get_tagregs()
tagimms = hex_common.get_tagimms()
with open(sys.argv[3], 'w') as f:
with open(sys.argv[3], "w") as f:
for tag in hex_common.tags:
regs = tagregs[tag]
rregs = []
wregs = []
regids = ""
for regtype,regid,toss,numregs in regs:
for regtype, regid, toss, numregs in regs:
if hex_common.is_read(regid):
if regid[0] not in regids: regids += regid[0]
rregs.append(regtype+regid+numregs)
if regid[0] not in regids:
regids += regid[0]
rregs.append(regtype + regid + numregs)
if hex_common.is_written(regid):
wregs.append(regtype+regid+numregs)
if regid[0] not in regids: regids += regid[0]
wregs.append(regtype + regid + numregs)
if regid[0] not in regids:
regids += regid[0]
for attrib in hex_common.attribdict[tag]:
if hex_common.attribinfo[attrib]['rreg']:
rregs.append(strip_reg_prefix(attribinfo[attrib]['rreg']))
if hex_common.attribinfo[attrib]['wreg']:
wregs.append(strip_reg_prefix(attribinfo[attrib]['wreg']))
if hex_common.attribinfo[attrib]["rreg"]:
rregs.append(strip_reg_prefix(attribinfo[attrib]["rreg"]))
if hex_common.attribinfo[attrib]["wreg"]:
wregs.append(strip_reg_prefix(attribinfo[attrib]["wreg"]))
regids += calculate_regid_letters(tag)
f.write('REGINFO(%s,"%s",\t/*RD:*/\t"%s",\t/*WR:*/\t"%s")\n' % \
(tag,regids,",".join(rregs),",".join(wregs)))
f.write(
f'REGINFO({tag},"{regids}",\t/*RD:*/\t"{",".join(rregs)}",'
f'\t/*WR:*/\t"{",".join(wregs)}")\n'
)
for tag in hex_common.tags:
imms = tagimms[tag]
f.write( 'IMMINFO(%s' % tag)
f.write(f"IMMINFO({tag}")
if not imms:
f.write(''','u',0,0,'U',0,0''')
for sign,size,shamt in imms:
if sign == 'r': sign = 's'
f.write(""",'u',0,0,'U',0,0""")
for sign, size, shamt in imms:
if sign == "r":
sign = "s"
if not shamt:
shamt = "0"
f.write(''','%s',%s,%s''' % (sign,size,shamt))
f.write(f""",'{sign}',{size},{shamt}""")
if len(imms) == 1:
if sign.isupper():
myu = 'u'
myu = "u"
else:
myu = 'U'
f.write(''','%s',0,0''' % myu)
f.write(')\n')
myu = "U"
f.write(f""",'{myu}',0,0""")
f.write(")\n")
if __name__ == "__main__":
main()
target/hexagon/gen_opcodes_def.py
+5 -3
View File
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -22,15 +22,17 @@ import re
import string
import hex_common
def main():
hex_common.read_semantics_file(sys.argv[1])
##
## Generate a list of all the opcodes
##
with open(sys.argv[3], 'w') as f:
with open(sys.argv[3], "w") as f:
for tag in hex_common.tags:
f.write ( "OPCODE(%s),\n" % (tag) )
f.write(f"OPCODE({tag}),\n")
if __name__ == "__main__":
main()
target/hexagon/gen_printinsn.py
+44 -40
View File
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -22,24 +22,26 @@ import re
import string
import hex_common
##
## Generate data for printing each instruction (format string + operands)
##
def regprinter(m):
str = m.group(1)
str += ":".join(["%d"]*len(m.group(2)))
str += ":".join(["%d"] * len(m.group(2)))
str += m.group(3)
if ('S' in m.group(1)) and (len(m.group(2)) == 1):
if ("S" in m.group(1)) and (len(m.group(2)) == 1):
str += "/%s"
elif ('C' in m.group(1)) and (len(m.group(2)) == 1):
elif ("C" in m.group(1)) and (len(m.group(2)) == 1):
str += "/%s"
return str
def spacify(s):
# Regular expression that matches any operator that contains '=' character:
opswithequal_re = '[-+^&|!<>=]?='
opswithequal_re = "[-+^&|!<>=]?="
# Regular expression that matches any assignment operator.
assignment_re = '[-+^&|]?='
assignment_re = "[-+^&|]?="
# Out of the operators that contain the = sign, if the operator is also an
# assignment, spaces will be added around it, unless it's enclosed within
@@ -54,9 +56,9 @@ def spacify(s):
pc = 0
while i < slen:
c = s[i]
if c == '(':
if c == "(":
pc += 1
elif c == ')':
elif c == ")":
pc -= 1
paren_count[i] = pc
i += 1
@@ -76,31 +78,33 @@ def spacify(s):
if paren_count[ms] == 0:
# Check if the entire string t is an assignment.
am = assign.match(t)
if am and len(am.group(0)) == me-ms:
if am and len(am.group(0)) == me - ms:
# Don't add spaces if they are already there.
if ms > 0 and s[ms-1] != ' ':
out.append(' ')
if ms > 0 and s[ms - 1] != " ":
out.append(" ")
out += t
if me < slen and s[me] != ' ':
out.append(' ')
if me < slen and s[me] != " ":
out.append(" ")
continue
# If this is not an assignment, just append it to the output
# string.
out += t
# Append the remaining part of the string.
out += s[pos:len(s)]
return ''.join(out)
out += s[pos : len(s)]
return "".join(out)
def main():
hex_common.read_semantics_file(sys.argv[1])
hex_common.read_attribs_file(sys.argv[2])
immext_casere = re.compile(r'IMMEXT\(([A-Za-z])')
immext_casere = re.compile(r"IMMEXT\(([A-Za-z])")
with open(sys.argv[3], 'w') as f:
with open(sys.argv[3], "w") as f:
for tag in hex_common.tags:
if not hex_common.behdict[tag]: continue
if not hex_common.behdict[tag]:
continue
extendable_upper_imm = False
extendable_lower_imm = False
m = immext_casere.search(hex_common.semdict[tag])
@@ -110,46 +114,45 @@ def main():
else:
extendable_lower_imm = True
beh = hex_common.behdict[tag]
beh = hex_common.regre.sub(regprinter,beh)
beh = hex_common.absimmre.sub(r"#%s0x%x",beh)
beh = hex_common.relimmre.sub(r"PC+%s%d",beh)
beh = hex_common.regre.sub(regprinter, beh)
beh = hex_common.absimmre.sub(r"#%s0x%x", beh)
beh = hex_common.relimmre.sub(r"PC+%s%d", beh)
beh = spacify(beh)
# Print out a literal "%s" at the end, used to match empty string
# so C won't complain at us
if ("A_VECX" in hex_common.attribdict[tag]):
if "A_VECX" in hex_common.attribdict[tag]:
macname = "DEF_VECX_PRINTINFO"
else: macname = "DEF_PRINTINFO"
f.write('%s(%s,"%s%%s"' % (macname,tag,beh))
regs_or_imms = \
hex_common.reg_or_immre.findall(hex_common.behdict[tag])
else:
macname = "DEF_PRINTINFO"
f.write(f'{macname}({tag},"{beh}%s"')
regs_or_imms = hex_common.reg_or_immre.findall(hex_common.behdict[tag])
ri = 0
seenregs = {}
for allregs,a,b,c,d,allimm,immlett,bits,immshift in regs_or_imms:
for allregs, a, b, c, d, allimm, immlett, bits, immshift in regs_or_imms:
if a:
#register
# register
if b in seenregs:
regno = seenregs[b]
else:
regno = ri
if len(b) == 1:
f.write(', insn->regno[%d]' % regno)
if 'S' in a:
f.write(', sreg2str(insn->regno[%d])' % regno)
elif 'C' in a:
f.write(', creg2str(insn->regno[%d])' % regno)
f.write(f", insn->regno[{regno}]")
if "S" in a:
f.write(f", sreg2str(insn->regno[{regno}])")
elif "C" in a:
f.write(f", creg2str(insn->regno[{regno}])")
elif len(b) == 2:
f.write(', insn->regno[%d] + 1, insn->regno[%d]' % \
(regno,regno))
f.write(f", insn->regno[{regno}] + 1" f", insn->regno[{regno}]")
else:
print("Put some stuff to handle quads here")
if b not in seenregs:
seenregs[b] = ri
ri += 1
else:
#immediate
if (immlett.isupper()):
# immediate
if immlett.isupper():
if extendable_upper_imm:
if immlett in 'rR':
if immlett in "rR":
f.write(',insn->extension_valid?"##":""')
else:
f.write(',insn->extension_valid?"#":""')
@@ -158,16 +161,17 @@ def main():
ii = 1
else:
if extendable_lower_imm:
if immlett in 'rR':
if immlett in "rR":
f.write(',insn->extension_valid?"##":""')
else:
f.write(',insn->extension_valid?"#":""')
else:
f.write(',""')
ii = 0
f.write(', insn->immed[%d]' % ii)
f.write(f", insn->immed[{ii}]")
# append empty string so there is at least one more arg
f.write(',"")\n')
if __name__ == "__main__":
main()
target/hexagon/gen_shortcode.py
+11 -8
View File
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -22,8 +22,10 @@ import re
import string
import hex_common
def gen_shortcode(f, tag):
f.write('DEF_SHORTCODE(%s, %s)\n' % (tag, hex_common.semdict[tag]))
f.write(f"DEF_SHORTCODE({tag}, {hex_common.semdict[tag]})\n")
def main():
hex_common.read_semantics_file(sys.argv[1])
@@ -32,29 +34,30 @@ def main():
tagregs = hex_common.get_tagregs()
tagimms = hex_common.get_tagimms()
with open(sys.argv[3], 'w') as f:
with open(sys.argv[3], "w") as f:
f.write("#ifndef DEF_SHORTCODE\n")
f.write("#define DEF_SHORTCODE(TAG,SHORTCODE) /* Nothing */\n")
f.write("#endif\n")
for tag in hex_common.tags:
## Skip the priv instructions
if ( "A_PRIV" in hex_common.attribdict[tag] ) :
if "A_PRIV" in hex_common.attribdict[tag]:
continue
## Skip the guest instructions
if ( "A_GUEST" in hex_common.attribdict[tag] ) :
if "A_GUEST" in hex_common.attribdict[tag]:
continue
## Skip the diag instructions
if ( tag == "Y6_diag" ) :
if tag == "Y6_diag":
continue
if ( tag == "Y6_diag0" ) :
if tag == "Y6_diag0":
continue
if ( tag == "Y6_diag1" ) :
if tag == "Y6_diag1":
continue
gen_shortcode(f, tag)
f.write("#undef DEF_SHORTCODE\n")
if __name__ == "__main__":
main()
target/hexagon/gen_tcg.h
+50 -2
View File
@@ -487,6 +487,19 @@
#define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \
fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN))
/* dczeroa clears the 32 byte cache line at the address given */
#define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE
/* In linux-user mode, these are not modelled, suppress compiler warning */
#define fGEN_TCG_Y2_dcinva(SHORTCODE) \
do { RsV = RsV; } while (0)
#define fGEN_TCG_Y2_dccleaninva(SHORTCODE) \
do { RsV = RsV; } while (0)
#define fGEN_TCG_Y2_dccleana(SHORTCODE) \
do { RsV = RsV; } while (0)
#define fGEN_TCG_Y2_icinva(SHORTCODE) \
do { RsV = RsV; } while (0)
/*
* dealloc_return
* Assembler mapped to
@@ -1039,11 +1052,11 @@
/* r0 = asr(r1, r2):sat */
#define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \
gen_asr_r_r_sat(RdV, RsV, RtV)
gen_asr_r_r_sat(ctx, RdV, RsV, RtV)
/* r0 = asl(r1, r2):sat */
#define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \
gen_asl_r_r_sat(RdV, RsV, RtV)
gen_asl_r_r_sat(ctx, RdV, RsV, RtV)
#define fGEN_TCG_SL2_jumpr31(SHORTCODE) \
gen_jumpr(ctx, hex_gpr[HEX_REG_LR])
@@ -1058,6 +1071,30 @@
#define fGEN_TCG_SL2_jumpr31_fnew(SHORTCODE) \
gen_cond_jumpr31(ctx, TCG_COND_NE, hex_new_pred_value[0])
/* Count trailing zeros/ones */
#define fGEN_TCG_S2_ct0(SHORTCODE) \
do { \
tcg_gen_ctzi_tl(RdV, RsV, 32); \
} while (0)
#define fGEN_TCG_S2_ct1(SHORTCODE) \
do { \
tcg_gen_not_tl(RdV, RsV); \
tcg_gen_ctzi_tl(RdV, RdV, 32); \
} while (0)
#define fGEN_TCG_S2_ct0p(SHORTCODE) \
do { \
TCGv_i64 tmp = tcg_temp_new_i64(); \
tcg_gen_ctzi_i64(tmp, RssV, 64); \
tcg_gen_extrl_i64_i32(RdV, tmp); \
} while (0)
#define fGEN_TCG_S2_ct1p(SHORTCODE) \
do { \
TCGv_i64 tmp = tcg_temp_new_i64(); \
tcg_gen_not_i64(tmp, RssV); \
tcg_gen_ctzi_i64(tmp, tmp, 64); \
tcg_gen_extrl_i64_i32(RdV, tmp); \
} while (0)
/* Floating point */
#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
gen_helper_conv_sf2df(RddV, cpu_env, RsV)
@@ -1187,6 +1224,17 @@
do { \
RsV = RsV; \
} while (0)
#define fGEN_TCG_Y2_isync(SHORTCODE) \
do { } while (0)
#define fGEN_TCG_Y2_barrier(SHORTCODE) \
do { } while (0)
#define fGEN_TCG_Y2_syncht(SHORTCODE) \
do { } while (0)
#define fGEN_TCG_Y2_dcfetchbo(SHORTCODE) \
do { \
RsV = RsV; \
uiV = uiV; \
} while (0)
#define fGEN_TCG_J2_trap0(SHORTCODE) \
do { \
target/hexagon/gen_tcg_func_table.py
+10 -8
View File
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@ import re
import string
import hex_common
def main():
hex_common.read_semantics_file(sys.argv[1])
hex_common.read_attribs_file(sys.argv[2])
@@ -29,30 +30,31 @@ def main():
tagregs = hex_common.get_tagregs()
tagimms = hex_common.get_tagimms()
with open(sys.argv[3], 'w') as f:
with open(sys.argv[3], "w") as f:
f.write("#ifndef HEXAGON_FUNC_TABLE_H\n")
f.write("#define HEXAGON_FUNC_TABLE_H\n\n")
f.write("const SemanticInsn opcode_genptr[XX_LAST_OPCODE] = {\n")
for tag in hex_common.tags:
## Skip the priv instructions
if ( "A_PRIV" in hex_common.attribdict[tag] ) :
if "A_PRIV" in hex_common.attribdict[tag]:
continue
## Skip the guest instructions
if ( "A_GUEST" in hex_common.attribdict[tag] ) :
if "A_GUEST" in hex_common.attribdict[tag]:
continue
## Skip the diag instructions
if ( tag == "Y6_diag" ) :
if tag == "Y6_diag":
continue
if ( tag == "Y6_diag0" ) :
if tag == "Y6_diag0":
continue
if ( tag == "Y6_diag1" ) :
if tag == "Y6_diag1":
continue
f.write(" [%s] = generate_%s,\n" % (tag, tag))
f.write(f" [{tag}] = generate_{tag},\n")
f.write("};\n\n")
f.write("#endif /* HEXAGON_FUNC_TABLE_H */\n")
if __name__ == "__main__":
main()
target/hexagon/gen_tcg_funcs.py
+381 -346
View File
File diff suppressed because it is too large Load Diff
target/hexagon/genptr.c
+23 -26
View File
@@ -486,30 +486,27 @@ static void gen_write_new_pc_pcrel(DisasContext *ctx, int pc_off,
}
}
void gen_set_usr_field(int field, TCGv val)
void gen_set_usr_field(DisasContext *ctx, int field, TCGv val)
{
tcg_gen_deposit_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR],
val,
TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
tcg_gen_deposit_tl(usr, usr, val,
reg_field_info[field].offset,
reg_field_info[field].width);
}
void gen_set_usr_fieldi(int field, int x)
void gen_set_usr_fieldi(DisasContext *ctx, int field, int x)
{
if (reg_field_info[field].width == 1) {
TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
target_ulong bit = 1 << reg_field_info[field].offset;
if ((x & 1) == 1) {
tcg_gen_ori_tl(hex_new_value[HEX_REG_USR],
hex_new_value[HEX_REG_USR],
bit);
tcg_gen_ori_tl(usr, usr, bit);
} else {
tcg_gen_andi_tl(hex_new_value[HEX_REG_USR],
hex_new_value[HEX_REG_USR],
~bit);
tcg_gen_andi_tl(usr, usr, ~bit);
}
} else {
TCGv val = tcg_constant_tl(x);
gen_set_usr_field(field, val);
gen_set_usr_field(ctx, field, val);
}
}
@@ -754,7 +751,7 @@ static void gen_endloop0(DisasContext *ctx)
tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2);
{
tcg_gen_subi_tl(lpcfg, lpcfg, 1);
SET_USR_FIELD(USR_LPCFG, lpcfg);
gen_set_usr_field(ctx, USR_LPCFG, lpcfg);
}
gen_set_label(label2);
@@ -829,7 +826,7 @@ static void gen_endloop01(DisasContext *ctx)
tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2);
{
tcg_gen_subi_tl(lpcfg, lpcfg, 1);
SET_USR_FIELD(USR_LPCFG, lpcfg);
gen_set_usr_field(ctx, USR_LPCFG, lpcfg);
}
gen_set_label(label2);
@@ -878,8 +875,9 @@ static void gen_cmpi_jumpnv(DisasContext *ctx,
}
/* Shift left with saturation */
static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
static void gen_shl_sat(DisasContext *ctx, TCGv dst, TCGv src, TCGv shift_amt)
{
TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
TCGv sh32 = tcg_temp_new();
TCGv dst_sar = tcg_temp_new();
TCGv ovf = tcg_temp_new();
@@ -911,7 +909,7 @@ static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
tcg_gen_setcond_tl(TCG_COND_NE, ovf, dst_sar, src);
tcg_gen_shli_tl(ovf, ovf, reg_field_info[USR_OVF].offset);
tcg_gen_or_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR], ovf);
tcg_gen_or_tl(usr, usr, ovf);
tcg_gen_movcond_tl(TCG_COND_EQ, dst, dst_sar, src, dst, satval);
}
@@ -928,7 +926,7 @@ static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt)
}
/* Bidirectional shift right with saturation */
static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
static void gen_asr_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV)
{
TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
@@ -939,7 +937,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
/* Negative shift amount => shift left */
tcg_gen_neg_tl(shift_amt, shift_amt);
gen_shl_sat(RdV, RsV, shift_amt);
gen_shl_sat(ctx, RdV, RsV, shift_amt);
tcg_gen_br(done);
gen_set_label(positive);
@@ -950,7 +948,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
}
/* Bidirectional shift left with saturation */
static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
static void gen_asl_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV)
{
TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
@@ -966,7 +964,7 @@ static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
gen_set_label(positive);
/* Positive shift amount => shift left */
gen_shl_sat(RdV, RsV, shift_amt);
gen_shl_sat(ctx, RdV, RsV, shift_amt);
gen_set_label(done);
}
@@ -1109,20 +1107,19 @@ void probe_noshuf_load(TCGv va, int s, int mi)
* Note: Since this function might branch, `val` is
* required to be a `tcg_temp_local`.
*/
void gen_set_usr_field_if(int field, TCGv val)
void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val)
{
/* Sets the USR field if `val` is non-zero */
if (reg_field_info[field].width == 1) {
TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
TCGv tmp = tcg_temp_new();
tcg_gen_extract_tl(tmp, val, 0, reg_field_info[field].width);
tcg_gen_shli_tl(tmp, tmp, reg_field_info[field].offset);
tcg_gen_or_tl(hex_new_value[HEX_REG_USR],
hex_new_value[HEX_REG_USR],
tmp);
tcg_gen_or_tl(usr, usr, tmp);
} else {
TCGLabel *skip_label = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, val, 0, skip_label);
gen_set_usr_field(field, val);
gen_set_usr_field(ctx, field, val);
gen_set_label(skip_label);
}
}
@@ -1190,7 +1187,7 @@ void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
}
/* Implements the fADDSAT64 macro in TCG */
void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 sum = tcg_temp_new_i64();
TCGv_i64 xor = tcg_temp_new_i64();
@@ -1227,7 +1224,7 @@ void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
gen_set_label(ovfl_label);
tcg_gen_and_i64(cond3, sum, mask);
tcg_gen_movcond_i64(TCG_COND_NE, ret, cond3, zero, max_pos, max_neg);
SET_USR_FIELD(USR_OVF, 1);
gen_set_usr_fieldi(ctx, USR_OVF, 1);
gen_set_label(ret_label);
}
target/hexagon/genptr.h
+5 -5
View File
@@ -1,5 +1,5 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -37,9 +37,9 @@ TCGv gen_read_reg(TCGv result, int num);
TCGv gen_read_preg(TCGv pred, uint8_t num);
void gen_log_reg_write(int rnum, TCGv val);
void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
void gen_set_usr_field(int field, TCGv val);
void gen_set_usr_fieldi(int field, int x);
void gen_set_usr_field_if(int field, TCGv val);
void gen_set_usr_field(DisasContext *ctx, int field, TCGv val);
void gen_set_usr_fieldi(DisasContext *ctx, int field, int x);
void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val);
void gen_sat_i32(TCGv dest, TCGv source, int width);
void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
void gen_satu_i32(TCGv dest, TCGv source, int width);
@@ -48,7 +48,7 @@ void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
TCGv gen_8bitsof(TCGv result, TCGv value);
void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
target/hexagon/helper.h
+2 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -107,4 +107,4 @@ DEF_HELPER_2(vwhist128qm, void, env, s32)
DEF_HELPER_4(probe_noshuf_load, void, env, i32, int, int)
DEF_HELPER_2(probe_pkt_scalar_store_s0, void, env, int)
DEF_HELPER_2(probe_hvx_stores, void, env, int)
DEF_HELPER_3(probe_pkt_scalar_hvx_stores, void, env, int, int)
DEF_HELPER_2(probe_pkt_scalar_hvx_stores, void, env, int)
target/hexagon/hex_common.py
+112 -69
View File
@@ -21,14 +21,15 @@ import sys
import re
import string
behdict = {} # tag ->behavior
semdict = {} # tag -> semantics
attribdict = {} # tag -> attributes
macros = {} # macro -> macro information...
attribinfo = {} # Register information and misc
tags = [] # list of all tags
overrides = {} # tags with helper overrides
idef_parser_enabled = {} # tags enabled for idef-parser
behdict = {} # tag ->behavior
semdict = {} # tag -> semantics
attribdict = {} # tag -> attributes
macros = {} # macro -> macro information...
attribinfo = {} # Register information and misc
tags = [] # list of all tags
overrides = {} # tags with helper overrides
idef_parser_enabled = {} # tags enabled for idef-parser
# We should do this as a hash for performance,
# but to keep order let's keep it as a list.
@@ -37,71 +38,77 @@ def uniquify(seq):
seen_add = seen.add
return [x for x in seq if x not in seen and not seen_add(x)]
regre = re.compile(
r"((?<!DUP)[MNORCPQXSGVZA])([stuvwxyzdefg]+)([.]?[LlHh]?)(\d+S?)")
regre = re.compile(r"((?<!DUP)[MNORCPQXSGVZA])([stuvwxyzdefg]+)([.]?[LlHh]?)(\d+S?)")
immre = re.compile(r"[#]([rRsSuUm])(\d+)(?:[:](\d+))?")
reg_or_immre = \
re.compile(r"(((?<!DUP)[MNRCOPQXSGVZA])([stuvwxyzdefg]+)" + \
"([.]?[LlHh]?)(\d+S?))|([#]([rRsSuUm])(\d+)[:]?(\d+)?)")
reg_or_immre = re.compile(
r"(((?<!DUP)[MNRCOPQXSGVZA])([stuvwxyzdefg]+)"
+ "([.]?[LlHh]?)(\d+S?))|([#]([rRsSuUm])(\d+)[:]?(\d+)?)"
)
relimmre = re.compile(r"[#]([rR])(\d+)(?:[:](\d+))?")
absimmre = re.compile(r"[#]([sSuUm])(\d+)(?:[:](\d+))?")
finished_macros = set()
def expand_macro_attribs(macro,allmac_re):
def expand_macro_attribs(macro, allmac_re):
if macro.key not in finished_macros:
# Get a list of all things that might be macros
l = allmac_re.findall(macro.beh)
for submacro in l:
if not submacro: continue
if not submacro:
continue
if not macros[submacro]:
raise Exception("Couldn't find macro: <%s>" % l)
macro.attribs |= expand_macro_attribs(
macros[submacro], allmac_re)
raise Exception(f"Couldn't find macro: <{l}>")
macro.attribs |= expand_macro_attribs(macros[submacro], allmac_re)
finished_macros.add(macro.key)
return macro.attribs
# When qemu needs an attribute that isn't in the imported files,
# we'll add it here.
def add_qemu_macro_attrib(name, attrib):
macros[name].attribs.add(attrib)
immextre = re.compile(r'f(MUST_)?IMMEXT[(]([UuSsRr])')
immextre = re.compile(r"f(MUST_)?IMMEXT[(]([UuSsRr])")
def is_cond_jump(tag):
if tag == 'J2_rte':
if tag == "J2_rte":
return False
if ('A_HWLOOP0_END' in attribdict[tag] or
'A_HWLOOP1_END' in attribdict[tag]):
if "A_HWLOOP0_END" in attribdict[tag] or "A_HWLOOP1_END" in attribdict[tag]:
return False
return \
re.compile(r"(if.*fBRANCH)|(if.*fJUMPR)").search(semdict[tag]) != None
return re.compile(r"(if.*fBRANCH)|(if.*fJUMPR)").search(semdict[tag]) != None
def is_cond_call(tag):
return re.compile(r"(if.*fCALL)").search(semdict[tag]) != None
def calculate_attribs():
add_qemu_macro_attrib('fREAD_PC', 'A_IMPLICIT_READS_PC')
add_qemu_macro_attrib('fTRAP', 'A_IMPLICIT_READS_PC')
add_qemu_macro_attrib('fWRITE_P0', 'A_WRITES_PRED_REG')
add_qemu_macro_attrib('fWRITE_P1', 'A_WRITES_PRED_REG')
add_qemu_macro_attrib('fWRITE_P2', 'A_WRITES_PRED_REG')
add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG')
add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR')
add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR')
add_qemu_macro_attrib('fLOAD', 'A_SCALAR_LOAD')
add_qemu_macro_attrib('fSTORE', 'A_SCALAR_STORE')
add_qemu_macro_attrib("fREAD_PC", "A_IMPLICIT_READS_PC")
add_qemu_macro_attrib("fTRAP", "A_IMPLICIT_READS_PC")
add_qemu_macro_attrib("fWRITE_P0", "A_WRITES_PRED_REG")
add_qemu_macro_attrib("fWRITE_P1", "A_WRITES_PRED_REG")
add_qemu_macro_attrib("fWRITE_P2", "A_WRITES_PRED_REG")
add_qemu_macro_attrib("fWRITE_P3", "A_WRITES_PRED_REG")
add_qemu_macro_attrib("fSET_OVERFLOW", "A_IMPLICIT_WRITES_USR")
add_qemu_macro_attrib("fSET_LPCFG", "A_IMPLICIT_WRITES_USR")
add_qemu_macro_attrib("fLOAD", "A_SCALAR_LOAD")
add_qemu_macro_attrib("fSTORE", "A_SCALAR_STORE")
# Recurse down macros, find attributes from sub-macros
macroValues = list(macros.values())
allmacros_restr = "|".join(set([ m.re.pattern for m in macroValues ]))
allmacros_restr = "|".join(set([m.re.pattern for m in macroValues]))
allmacros_re = re.compile(allmacros_restr)
for macro in macroValues:
expand_macro_attribs(macro,allmacros_re)
expand_macro_attribs(macro, allmacros_re)
# Append attributes to all instructions
for tag in tags:
for macname in allmacros_re.findall(semdict[tag]):
if not macname: continue
if not macname:
continue
macro = macros[macname]
attribdict[tag] |= set(macro.attribs)
# Figure out which instructions write predicate registers
@@ -110,31 +117,34 @@ def calculate_attribs():
regs = tagregs[tag]
for regtype, regid, toss, numregs in regs:
if regtype == "P" and is_written(regid):
attribdict[tag].add('A_WRITES_PRED_REG')
attribdict[tag].add("A_WRITES_PRED_REG")
# Mark conditional jumps and calls
# Not all instructions are properly marked with A_CONDEXEC
for tag in tags:
if is_cond_jump(tag) or is_cond_call(tag):
attribdict[tag].add('A_CONDEXEC')
attribdict[tag].add("A_CONDEXEC")
def SEMANTICS(tag, beh, sem):
#print tag,beh,sem
# print tag,beh,sem
behdict[tag] = beh
semdict[tag] = sem
attribdict[tag] = set()
tags.append(tag) # dicts have no order, this is for order
tags.append(tag) # dicts have no order, this is for order
def ATTRIBUTES(tag, attribstring):
attribstring = \
attribstring.replace("ATTRIBS","").replace("(","").replace(")","")
attribstring = attribstring.replace("ATTRIBS", "").replace("(", "").replace(")", "")
if not attribstring:
return
attribs = attribstring.split(",")
for attrib in attribs:
attribdict[tag].add(attrib.strip())
class Macro(object):
__slots__ = ['key','name', 'beh', 'attribs', 're']
__slots__ = ["key", "name", "beh", "attribs", "re"]
def __init__(self, name, beh, attribs):
self.key = name
self.name = name
@@ -142,20 +152,24 @@ class Macro(object):
self.attribs = set(attribs)
self.re = re.compile("\\b" + name + "\\b")
def MACROATTRIB(macname,beh,attribstring):
attribstring = attribstring.replace("(","").replace(")","")
def MACROATTRIB(macname, beh, attribstring):
attribstring = attribstring.replace("(", "").replace(")", "")
if attribstring:
attribs = attribstring.split(",")
else:
attribs = []
macros[macname] = Macro(macname,beh,attribs)
macros[macname] = Macro(macname, beh, attribs)
def compute_tag_regs(tag):
return uniquify(regre.findall(behdict[tag]))
def compute_tag_immediates(tag):
return uniquify(immre.findall(behdict[tag]))
##
## tagregs is the main data structure we'll use
## tagregs[tag] will contain the registers used by an instruction
@@ -180,89 +194,113 @@ def compute_tag_immediates(tag):
def get_tagregs():
return dict(zip(tags, list(map(compute_tag_regs, tags))))
def get_tagimms():
return dict(zip(tags, list(map(compute_tag_immediates, tags))))
def is_pair(regid):
return len(regid) == 2
def is_single(regid):
return len(regid) == 1
def is_written(regid):
return regid[0] in "dexy"
def is_writeonly(regid):
return regid[0] in "de"
def is_read(regid):
return regid[0] in "stuvwxy"
def is_readwrite(regid):
return regid[0] in "xy"
def is_scalar_reg(regtype):
return regtype in "RPC"
def is_hvx_reg(regtype):
return regtype in "VQ"
def is_old_val(regtype, regid, tag):
return regtype+regid+'V' in semdict[tag]
return regtype + regid + "V" in semdict[tag]
def is_new_val(regtype, regid, tag):
return regtype+regid+'N' in semdict[tag]
return regtype + regid + "N" in semdict[tag]
def need_slot(tag):
if (('A_CONDEXEC' in attribdict[tag] and
'A_JUMP' not in attribdict[tag]) or
'A_STORE' in attribdict[tag] or
'A_LOAD' in attribdict[tag]):
if (
("A_CONDEXEC" in attribdict[tag] and "A_JUMP" not in attribdict[tag])
or "A_STORE" in attribdict[tag]
or "A_LOAD" in attribdict[tag]
):
return 1
else:
return 0
def need_part1(tag):
return re.compile(r"fPART1").search(semdict[tag])
def need_ea(tag):
return re.compile(r"\bEA\b").search(semdict[tag])
def need_PC(tag):
return 'A_IMPLICIT_READS_PC' in attribdict[tag]
return "A_IMPLICIT_READS_PC" in attribdict[tag]
def helper_needs_next_PC(tag):
return 'A_CALL' in attribdict[tag]
return "A_CALL" in attribdict[tag]
def need_pkt_has_multi_cof(tag):
return 'A_COF' in attribdict[tag]
return "A_COF" in attribdict[tag]
def need_condexec_reg(tag, regs):
if 'A_CONDEXEC' in attribdict[tag]:
if "A_CONDEXEC" in attribdict[tag]:
for regtype, regid, toss, numregs in regs:
if is_writeonly(regid) and not is_hvx_reg(regtype):
return True
return False
def skip_qemu_helper(tag):
return tag in overrides.keys()
def is_tmp_result(tag):
return ('A_CVI_TMP' in attribdict[tag] or
'A_CVI_TMP_DST' in attribdict[tag])
return "A_CVI_TMP" in attribdict[tag] or "A_CVI_TMP_DST" in attribdict[tag]
def is_new_result(tag):
return ('A_CVI_NEW' in attribdict[tag])
return "A_CVI_NEW" in attribdict[tag]
def is_idef_parser_enabled(tag):
return tag in idef_parser_enabled
def imm_name(immlett):
return "%siV" % immlett
return f"{immlett}iV"
def read_semantics_file(name):
eval_line = ""
for line in open(name, 'rt').readlines():
for line in open(name, "rt").readlines():
if not line.startswith("#"):
eval_line += line
if line.endswith("\\\n"):
@@ -271,24 +309,29 @@ def read_semantics_file(name):
eval(eval_line.strip())
eval_line = ""
def read_attribs_file(name):
attribre = re.compile(r'DEF_ATTRIB\(([A-Za-z0-9_]+), ([^,]*), ' +
r'"([A-Za-z0-9_\.]*)", "([A-Za-z0-9_\.]*)"\)')
for line in open(name, 'rt').readlines():
attribre = re.compile(
r"DEF_ATTRIB\(([A-Za-z0-9_]+), ([^,]*), "
+ r'"([A-Za-z0-9_\.]*)", "([A-Za-z0-9_\.]*)"\)'
)
for line in open(name, "rt").readlines():
if not attribre.match(line):
continue
(attrib_base,descr,rreg,wreg) = attribre.findall(line)[0]
attrib_base = 'A_' + attrib_base
attribinfo[attrib_base] = {'rreg':rreg, 'wreg':wreg, 'descr':descr}
(attrib_base, descr, rreg, wreg) = attribre.findall(line)[0]
attrib_base = "A_" + attrib_base
attribinfo[attrib_base] = {"rreg": rreg, "wreg": wreg, "descr": descr}
def read_overrides_file(name):
overridere = re.compile("#define fGEN_TCG_([A-Za-z0-9_]+)\(.*")
for line in open(name, 'rt').readlines():
for line in open(name, "rt").readlines():
if not overridere.match(line):
continue
tag = overridere.findall(line)[0]
overrides[tag] = True
def read_idef_parser_enabled_file(name):
global idef_parser_enabled
with open(name, "r") as idef_parser_enabled_file:
target/hexagon/idef-parser/idef-parser.y
+1 -1
View File
@@ -362,7 +362,7 @@ assign_statement : lvalue '=' rvalue
"Assignment side-effect not modeled!");
$3 = gen_rvalue_truncate(c, &@1, &$3);
$3 = rvalue_materialize(c, &@1, &$3);
OUT(c, &@1, "SET_USR_FIELD(USR_LPCFG, ", &$3, ");\n");
OUT(c, &@1, "gen_set_usr_field(ctx, USR_LPCFG, ", &$3, ");\n");
}
| DEPOSIT '(' rvalue ',' rvalue ',' rvalue ')'
{
target/hexagon/idef-parser/parser-helpers.c
+3 -2
View File
@@ -1640,7 +1640,8 @@ void gen_addsat64(Context *c,
{
HexValue op1_m = rvalue_materialize(c, locp, op1);
HexValue op2_m = rvalue_materialize(c, locp, op2);
OUT(c, locp, "gen_add_sat_i64(", dst, ", ", &op1_m, ", ", &op2_m, ");\n");
OUT(c, locp, "gen_add_sat_i64(ctx, ", dst, ", ", &op1_m, ", ",
&op2_m, ");\n");
}
void gen_inst(Context *c, GString *iname)
@@ -1971,7 +1972,7 @@ HexValue gen_rvalue_sat(Context *c, YYLTYPE *locp, HexSat *sat,
OUT(c, locp, "gen_sat", unsigned_str, "_", bit_suffix, "_ovfl(");
OUT(c, locp, &ovfl, ", ", &res, ", ", value, ", ", &width->imm.value,
");\n");
OUT(c, locp, "gen_set_usr_field_if(USR_OVF,", &ovfl, ");\n");
OUT(c, locp, "gen_set_usr_field_if(ctx, USR_OVF,", &ovfl, ");\n");
return res;
}
target/hexagon/macros.h
+25 -64
View File
@@ -22,16 +22,6 @@
#include "hex_regs.h"
#include "reg_fields.h"
#ifdef QEMU_GENERATE
#define READ_REG(dest, NUM) gen_read_reg(dest, NUM)
#else
#define READ_REG(NUM) (env->gpr[(NUM)])
#define READ_PREG(NUM) (env->pred[NUM])
#define WRITE_RREG(NUM, VAL) log_reg_write(env, NUM, VAL, slot)
#define WRITE_PREG(NUM, VAL) log_pred_write(env, NUM, VAL)
#endif
#define PCALIGN 4
#define PCALIGN_MASK (PCALIGN - 1)
@@ -48,14 +38,6 @@
#define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int)
#define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv)
#define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64)
#define SET_USR_FIELD_FUNC(X) \
__builtin_choose_expr(TYPE_INT(X), \
gen_set_usr_fieldi, \
__builtin_choose_expr(TYPE_TCGV(X), \
gen_set_usr_field, (void)0))
#define SET_USR_FIELD(FIELD, VAL) \
SET_USR_FIELD_FUNC(VAL)(FIELD, VAL)
#else
#define GET_USR_FIELD(FIELD) \
fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
@@ -361,37 +343,30 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
tcg_gen_shli_tl(result, result, shift);
return result;
}
#define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT))
#else
#define fREAD_IREG(VAL) \
(fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f)))
#endif
#define fREAD_LR() (READ_REG(HEX_REG_LR))
#define fREAD_LR() (env->gpr[HEX_REG_LR])
#define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A)
#define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A)
#define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A)
#define fWRITE_LR(A) log_reg_write(env, HEX_REG_LR, A)
#define fWRITE_FP(A) log_reg_write(env, HEX_REG_FP, A)
#define fWRITE_SP(A) log_reg_write(env, HEX_REG_SP, A)
#define fREAD_SP() (READ_REG(HEX_REG_SP))
#define fREAD_LC0 (READ_REG(HEX_REG_LC0))
#define fREAD_LC1 (READ_REG(HEX_REG_LC1))
#define fREAD_SA0 (READ_REG(HEX_REG_SA0))
#define fREAD_SA1 (READ_REG(HEX_REG_SA1))
#define fREAD_FP() (READ_REG(HEX_REG_FP))
#define fREAD_SP() (env->gpr[HEX_REG_SP])
#define fREAD_LC0 (env->gpr[HEX_REG_LC0])
#define fREAD_LC1 (env->gpr[HEX_REG_LC1])
#define fREAD_SA0 (env->gpr[HEX_REG_SA0])
#define fREAD_SA1 (env->gpr[HEX_REG_SA1])
#define fREAD_FP() (env->gpr[HEX_REG_FP])
#ifdef FIXME
/* Figure out how to get insn->extension_valid to helper */
#define fREAD_GP() \
(insn->extension_valid ? 0 : READ_REG(HEX_REG_GP))
(insn->extension_valid ? 0 : env->gpr[HEX_REG_GP])
#else
#define fREAD_GP() READ_REG(HEX_REG_GP)
#define fREAD_GP() (env->gpr[HEX_REG_GP])
#endif
#define fREAD_PC() (PC)
#define fREAD_NPC() (next_PC & (0xfffffffe))
#define fREAD_P0() (READ_PREG(0))
#define fREAD_P3() (READ_PREG(3))
#define fREAD_P0() (env->pred[0])
#define fCHECK_PCALIGN(A)
@@ -402,24 +377,22 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
#define fHINTJR(TARGET) { /* Not modelled in qemu */}
#define fWRITE_LOOP_REGS0(START, COUNT) \
do { \
WRITE_RREG(HEX_REG_LC0, COUNT); \
WRITE_RREG(HEX_REG_SA0, START); \
log_reg_write(env, HEX_REG_LC0, COUNT); \
log_reg_write(env, HEX_REG_SA0, START); \
} while (0)
#define fWRITE_LOOP_REGS1(START, COUNT) \
do { \
WRITE_RREG(HEX_REG_LC1, COUNT); \
WRITE_RREG(HEX_REG_SA1, START);\
log_reg_write(env, HEX_REG_LC1, COUNT); \
log_reg_write(env, HEX_REG_SA1, START);\
} while (0)
#define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL)
#define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL)
#define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
#define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
#define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
#define fWRITE_P0(VAL) WRITE_PREG(0, VAL)
#define fWRITE_P1(VAL) WRITE_PREG(1, VAL)
#define fWRITE_P2(VAL) WRITE_PREG(2, VAL)
#define fWRITE_P3(VAL) WRITE_PREG(3, VAL)
#define fWRITE_P0(VAL) log_pred_write(env, 0, VAL)
#define fWRITE_P1(VAL) log_pred_write(env, 1, VAL)
#define fWRITE_P2(VAL) log_pred_write(env, 2, VAL)
#define fWRITE_P3(VAL) log_pred_write(env, 3, VAL)
#define fPART1(WORK) if (part1) { WORK; return; }
#define fCAST4u(A) ((uint32_t)(A))
#define fCAST4s(A) ((int32_t)(A))
@@ -576,7 +549,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
#define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
#define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY)
#define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY])
#define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
#define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
@@ -686,22 +659,10 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
reg_field_info[FIELD].width, \
reg_field_info[FIELD].offset)
#define fGET_FIELD(VAL, FIELD)
#define fSET_FIELD(VAL, FIELD, NEWVAL)
#define fBARRIER()
#define fSYNCH()
#define fISYNC()
#define fDCFETCH(REG) \
do { (void)REG; } while (0) /* Nothing to do in qemu */
#define fICINVA(REG) \
do { (void)REG; } while (0) /* Nothing to do in qemu */
#define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
#define fDCCLEANA(REG) \
do { (void)REG; } while (0) /* Nothing to do in qemu */
#define fDCCLEANINVA(REG) \
do { (void)REG; } while (0) /* Nothing to do in qemu */
#define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
#ifdef QEMU_GENERATE
#define fDCZEROA(REG) tcg_gen_mov_tl(hex_dczero_addr, (REG))
#endif
#define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
STRBITNUM) /* Nothing */

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