mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Remove Sun4c, Sun4d and a few CPUs
Sun4c and Sun4d architectures and related CPUs are not fully implemented (especially Sun4c MMU) and there has been no interest for them. Likewise, a few CPUs (Cypress, Ross etc) are only half implemented. Remove the machines and CPUs, they can be re-added if needed later. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
@@ -7,7 +7,7 @@ common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o
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common-obj-$(CONFIG_IMX) += imx_avic.o
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common-obj-$(CONFIG_LM32) += lm32_pic.o
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common-obj-$(CONFIG_REALVIEW) += realview_gic.o
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common-obj-$(CONFIG_SLAVIO) += sbi.o slavio_intctl.o sun4c_intctl.o
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common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o
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common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
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-156
@@ -1,156 +0,0 @@
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/*
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* QEMU Sparc SBI interrupt controller emulation
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*
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* Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
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||||
*
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||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
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||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h"
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...) \
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do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define MAX_CPUS 16
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#define SBI_NREGS 16
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typedef struct SBIState {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t regs[SBI_NREGS];
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uint32_t intreg_pending[MAX_CPUS];
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qemu_irq cpu_irqs[MAX_CPUS];
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uint32_t pil_out[MAX_CPUS];
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} SBIState;
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#define SBI_SIZE (SBI_NREGS * 4)
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static void sbi_set_irq(void *opaque, int irq, int level)
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{
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}
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static uint64_t sbi_mem_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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SBIState *s = opaque;
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uint32_t saddr, ret;
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saddr = addr >> 2;
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switch (saddr) {
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default:
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ret = s->regs[saddr];
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break;
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}
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DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
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return ret;
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}
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static void sbi_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned dize)
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{
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SBIState *s = opaque;
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uint32_t saddr;
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saddr = addr >> 2;
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DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, (int)val);
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switch (saddr) {
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default:
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s->regs[saddr] = val;
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break;
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}
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}
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static const MemoryRegionOps sbi_mem_ops = {
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.read = sbi_mem_read,
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.write = sbi_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const VMStateDescription vmstate_sbi = {
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.name ="sbi",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS),
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VMSTATE_END_OF_LIST()
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}
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};
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static void sbi_reset(DeviceState *d)
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{
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SBIState *s = container_of(d, SBIState, busdev.qdev);
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unsigned int i;
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for (i = 0; i < MAX_CPUS; i++) {
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s->intreg_pending[i] = 0;
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}
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}
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static int sbi_init1(SysBusDevice *dev)
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{
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SBIState *s = FROM_SYSBUS(SBIState, dev);
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unsigned int i;
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qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS);
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for (i = 0; i < MAX_CPUS; i++) {
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sysbus_init_irq(dev, &s->cpu_irqs[i]);
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}
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memory_region_init_io(&s->iomem, &sbi_mem_ops, s, "sbi", SBI_SIZE);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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}
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static void sbi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = sbi_init1;
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dc->reset = sbi_reset;
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dc->vmsd = &vmstate_sbi;
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}
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static const TypeInfo sbi_info = {
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.name = "sbi",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SBIState),
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.class_init = sbi_class_init,
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};
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static void sbi_register_types(void)
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{
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type_register_static(&sbi_info);
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}
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type_init(sbi_register_types)
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@@ -1,208 +0,0 @@
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/*
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* QEMU Sparc Sun4c interrupt controller emulation
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*
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* Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
|
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* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
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*
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||||
* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h"
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#include "hw/sparc/sun4m.h"
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#include "monitor/monitor.h"
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#include "hw/sysbus.h"
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//#define DEBUG_IRQ_COUNT
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...) \
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do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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/*
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* Registers of interrupt controller in sun4c.
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*
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*/
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#define MAX_PILS 16
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typedef struct Sun4c_INTCTLState {
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SysBusDevice busdev;
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MemoryRegion iomem;
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#ifdef DEBUG_IRQ_COUNT
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uint64_t irq_count;
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#endif
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qemu_irq cpu_irqs[MAX_PILS];
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const uint32_t *intbit_to_level;
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uint32_t pil_out;
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uint8_t reg;
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uint8_t pending;
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} Sun4c_INTCTLState;
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#define INTCTL_SIZE 1
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static void sun4c_check_interrupts(void *opaque);
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static uint64_t sun4c_intctl_mem_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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Sun4c_INTCTLState *s = opaque;
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uint32_t ret;
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ret = s->reg;
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DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
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return ret;
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}
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static void sun4c_intctl_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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Sun4c_INTCTLState *s = opaque;
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DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, (unsigned)val);
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val &= 0xbf;
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s->reg = val;
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sun4c_check_interrupts(s);
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}
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static const MemoryRegionOps sun4c_intctl_mem_ops = {
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.read = sun4c_intctl_mem_read,
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.write = sun4c_intctl_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
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static void sun4c_check_interrupts(void *opaque)
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{
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Sun4c_INTCTLState *s = opaque;
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uint32_t pil_pending;
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unsigned int i;
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pil_pending = 0;
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if (s->pending && !(s->reg & 0x80000000)) {
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for (i = 0; i < 8; i++) {
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if (s->pending & (1 << i))
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pil_pending |= 1 << intbit_to_level[i];
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}
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}
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for (i = 0; i < MAX_PILS; i++) {
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if (pil_pending & (1 << i)) {
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if (!(s->pil_out & (1 << i)))
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qemu_irq_raise(s->cpu_irqs[i]);
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} else {
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if (s->pil_out & (1 << i))
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qemu_irq_lower(s->cpu_irqs[i]);
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}
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}
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s->pil_out = pil_pending;
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}
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/*
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* "irq" here is the bit number in the system interrupt register
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*/
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static void sun4c_set_irq(void *opaque, int irq, int level)
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{
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Sun4c_INTCTLState *s = opaque;
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uint32_t mask = 1 << irq;
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uint32_t pil = intbit_to_level[irq];
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DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
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level);
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if (pil > 0) {
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if (level) {
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#ifdef DEBUG_IRQ_COUNT
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s->irq_count++;
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#endif
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s->pending |= mask;
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} else {
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s->pending &= ~mask;
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}
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sun4c_check_interrupts(s);
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}
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}
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static const VMStateDescription vmstate_sun4c_intctl = {
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.name ="sun4c_intctl",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT8(reg, Sun4c_INTCTLState),
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VMSTATE_UINT8(pending, Sun4c_INTCTLState),
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VMSTATE_END_OF_LIST()
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}
|
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};
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static void sun4c_intctl_reset(DeviceState *d)
|
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{
|
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Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev);
|
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|
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s->reg = 1;
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s->pending = 0;
|
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}
|
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static int sun4c_intctl_init1(SysBusDevice *dev)
|
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{
|
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Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
|
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unsigned int i;
|
||||
|
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memory_region_init_io(&s->iomem, &sun4c_intctl_mem_ops, s,
|
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"intctl", INTCTL_SIZE);
|
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sysbus_init_mmio(dev, &s->iomem);
|
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qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
|
||||
|
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for (i = 0; i < MAX_PILS; i++) {
|
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sysbus_init_irq(dev, &s->cpu_irqs[i]);
|
||||
}
|
||||
|
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return 0;
|
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}
|
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|
||||
static void sun4c_intctl_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||||
|
||||
k->init = sun4c_intctl_init1;
|
||||
dc->reset = sun4c_intctl_reset;
|
||||
dc->vmsd = &vmstate_sun4c_intctl;
|
||||
}
|
||||
|
||||
static const TypeInfo sun4c_intctl_info = {
|
||||
.name = "sun4c_intctl",
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(Sun4c_INTCTLState),
|
||||
.class_init = sun4c_intctl_class_init,
|
||||
};
|
||||
|
||||
static void sun4c_intctl_register_types(void)
|
||||
{
|
||||
type_register_static(&sun4c_intctl_info);
|
||||
}
|
||||
|
||||
type_init(sun4c_intctl_register_types)
|
||||
+2
-461
File diff suppressed because it is too large
Load Diff
+3
-7
@@ -1958,15 +1958,11 @@ SPARCbook
|
||||
The emulation is somewhat complete. SMP up to 16 CPUs is supported,
|
||||
but Linux limits the number of usable CPUs to 4.
|
||||
|
||||
It's also possible to simulate a SPARCstation 2 (sun4c architecture),
|
||||
SPARCserver 1000, or SPARCcenter 2000 (sun4d architecture), but these
|
||||
emulators are not usable yet.
|
||||
|
||||
QEMU emulates the following sun4m/sun4c/sun4d peripherals:
|
||||
QEMU emulates the following sun4m peripherals:
|
||||
|
||||
@itemize @minus
|
||||
@item
|
||||
IOMMU or IO-UNITs
|
||||
IOMMU
|
||||
@item
|
||||
TCX Frame buffer
|
||||
@item
|
||||
@@ -2019,7 +2015,7 @@ qemu-system-sparc -prom-env 'auto-boot?=false' \
|
||||
-prom-env 'boot-device=sd(0,2,0):d' -prom-env 'boot-args=linux single'
|
||||
@end example
|
||||
|
||||
@item -M [SS-4|SS-5|SS-10|SS-20|SS-600MP|LX|Voyager|SPARCClassic] [|SPARCbook|SS-2|SS-1000|SS-2000]
|
||||
@item -M [SS-4|SS-5|SS-10|SS-20|SS-600MP|LX|Voyager|SPARCClassic] [|SPARCbook]
|
||||
|
||||
Set the emulated machine type. Default is SS-5.
|
||||
|
||||
|
||||
@@ -291,19 +291,6 @@ static const sparc_def_t sparc_defs[] = {
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
#else
|
||||
{
|
||||
.name = "Fujitsu MB86900",
|
||||
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */
|
||||
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
||||
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 7,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Fujitsu MB86904",
|
||||
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
|
||||
@@ -330,48 +317,6 @@ static const sparc_def_t sparc_defs[] = {
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "LSI L64811",
|
||||
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */
|
||||
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
|
||||
.mmu_version = 0x10 << 24,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Cypress CY7C601",
|
||||
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */
|
||||
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
|
||||
.mmu_version = 0x10 << 24,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Cypress CY7C611",
|
||||
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */
|
||||
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
|
||||
.mmu_version = 0x10 << 24,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "TI MicroSparc I",
|
||||
.iu_version = 0x41000000,
|
||||
@@ -494,73 +439,6 @@ static const sparc_def_t sparc_defs[] = {
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Ross RT625",
|
||||
.iu_version = 0x1e000000,
|
||||
.fpu_version = 1 << 17,
|
||||
.mmu_version = 0x1e000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Ross RT620",
|
||||
.iu_version = 0x1f000000,
|
||||
.fpu_version = 1 << 17,
|
||||
.mmu_version = 0x1f000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "BIT B5010",
|
||||
.iu_version = 0x20000000,
|
||||
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
|
||||
.mmu_version = 0x20000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Matsushita MN10501",
|
||||
.iu_version = 0x50000000,
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x50000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Weitek W8601",
|
||||
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */
|
||||
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
|
||||
.mmu_version = 0x10 << 24,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "LEON2",
|
||||
.iu_version = 0xf2000000,
|
||||
|
||||
Reference in New Issue
Block a user