MMX/SSE support

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1205 c046a42c-6fe2-441c-8c8c-71466251a162

Changelog

@@ -11,6 +11,7 @@ version 0.6.2:
   - added generic 64 bit target support
   - initial x86_64 target support
   - initial APIC support
+  - MMX/SSE/SSE2/PNI support
 
 version 0.6.1:
 

Makefile.target

@@ -392,7 +392,7 @@ helper.o: helper.c
 	$(CC) $(HELPER_CFLAGS) $(DEFINES) -c -o $@ $<
 
 ifeq ($(TARGET_BASE_ARCH), i386)
-op.o: op.c opreg_template.h ops_template.h ops_template_mem.h ops_mem.h
+op.o: op.c opreg_template.h ops_template.h ops_template_mem.h ops_mem.h ops_sse.h
 endif
 
 ifeq ($(TARGET_ARCH), arm)

linux-user/main.c

@@ -1052,8 +1052,8 @@ int main(int argc, char **argv)
     cpu_x86_set_cpl(env, 3);
 
     env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
-    env->hflags |= HF_PE_MASK;
-
+    env->hflags |= HF_PE_MASK | HF_OSFXSR_MASK;
+    
     /* flags setup : we activate the IRQs by default as in user mode */
     env->eflags |= IF_MASK;
     

target-i386/cpu.h

@@ -135,6 +135,7 @@
 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
+#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
 #define HF_VM_SHIFT         17 /* must be same as eflags */
 
 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
@@ -150,6 +151,7 @@
 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
+#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 
 #define CR0_PE_MASK  (1 << 0)
 #define CR0_MP_MASK  (1 << 1)
@@ -340,10 +342,12 @@ typedef struct SegmentCache {
 } SegmentCache;
 
 typedef union {
-        uint8_t _b[16];
-        uint16_t _w[8];
-        uint32_t _l[4];
-        uint64_t _q[2];
+    uint8_t _b[16];
+    uint16_t _w[8];
+    uint32_t _l[4];
+    uint64_t _q[2];
+    float _s[4];
+    double _d[2];
 } XMMReg;
 
 typedef union {
@@ -357,7 +361,9 @@ typedef union {
 #define XMM_B(n) _b[15 - (n)]
 #define XMM_W(n) _w[7 - (n)]
 #define XMM_L(n) _l[3 - (n)]
+#define XMM_S(n) _s[3 - (n)]
 #define XMM_Q(n) _q[1 - (n)]
+#define XMM_D(n) _d[1 - (n)]
 
 #define MMX_B(n) _b[7 - (n)]
 #define MMX_W(n) _w[3 - (n)]
@@ -366,12 +372,15 @@ typedef union {
 #define XMM_B(n) _b[n]
 #define XMM_W(n) _w[n]
 #define XMM_L(n) _l[n]
+#define XMM_S(n) _s[n]
 #define XMM_Q(n) _q[n]
+#define XMM_D(n) _d[n]
 
 #define MMX_B(n) _b[n]
 #define MMX_W(n) _w[n]
 #define MMX_L(n) _l[n]
 #endif
+#define MMX_Q(n) q
 
 #ifdef TARGET_X86_64
 #define CPU_NB_REGS 16
@@ -404,7 +413,14 @@ typedef struct CPUX86State {
     unsigned int fpus;
     unsigned int fpuc;
     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
-    CPU86_LDouble fpregs[8];
+    union {
+#ifdef USE_X86LDOUBLE
+        CPU86_LDouble d __attribute__((aligned(16)));
+#else
+        CPU86_LDouble d;
+#endif
+        MMXReg mmx;
+    } fpregs[8];
 
     /* emulator internal variables */
     CPU86_LDouble ft0;
@@ -421,9 +437,11 @@ typedef struct CPUX86State {
     SegmentCache tr;
     SegmentCache gdt; /* only base and limit are used */
     SegmentCache idt; /* only base and limit are used */
-    
+
+    uint32_t mxcsr;
     XMMReg xmm_regs[CPU_NB_REGS];
     XMMReg xmm_t0;
+    MMXReg mmx_t0;
 
     /* sysenter registers */
     uint32_t sysenter_cs;

target-i386/exec.h

@@ -131,8 +131,8 @@ extern int loglevel;
 
 /* float macros */
 #define FT0    (env->ft0)
-#define ST0    (env->fpregs[env->fpstt])
-#define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7])
+#define ST0    (env->fpregs[env->fpstt].d)
+#define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
 #define ST1    ST(1)
 
 #ifdef USE_FP_CONVERT
@@ -459,7 +459,7 @@ static inline CPU86_LDouble helper_fldt(target_ulong ptr)
     return temp.d;
 }
 
-static inline void helper_fstt(CPU86_LDouble f, uint8_t *ptr)
+static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
 {
     CPU86_LDoubleU temp;
     int e;
@@ -557,6 +557,9 @@ void helper_fxsave(target_ulong ptr, int data64);
 void helper_fxrstor(target_ulong ptr, int data64);
 void restore_native_fp_state(CPUState *env);
 void save_native_fp_state(CPUState *env);
+float approx_rsqrt(float a);
+float approx_rcp(float a);
+int fpu_isnan(double a);
 
 extern const uint8_t parity_table[256];
 extern const uint8_t rclw_table[32];

target-i386/helper.c

@@ -2444,7 +2444,7 @@ void helper_fldt_ST0_A0(void)
 {
     int new_fpstt;
     new_fpstt = (env->fpstt - 1) & 7;
-    env->fpregs[new_fpstt] = helper_fldt(A0);
+    env->fpregs[new_fpstt].d = helper_fldt(A0);
     env->fpstt = new_fpstt;
     env->fptags[new_fpstt] = 0; /* validate stack entry */
 }
@@ -2804,9 +2804,10 @@ void helper_fstenv(target_ulong ptr, int data32)
 	if (env->fptags[i]) {
             fptag |= 3;
 	} else {
-            tmp.d = env->fpregs[i];
+            tmp.d = env->fpregs[i].d;
             exp = EXPD(tmp);
             mant = MANTD(tmp);
+            printf("mant=%llx exp=%x\n", mant, exp);
             if (exp == 0 && mant == 0) {
                 /* zero */
 	        fptag |= 1;
@@ -2930,7 +2931,7 @@ void helper_fxsave(target_ulong ptr, int data64)
     
     if (env->cr[4] & CR4_OSFXSR_MASK) {
         /* XXX: finish it */
-        stl(ptr + 0x18, 0); /* mxcsr */
+        stl(ptr + 0x18, env->mxcsr); /* mxcsr */
         stl(ptr + 0x1c, 0); /* mxcsr_mask */
         nb_xmm_regs = 8 << data64;
         addr = ptr + 0xa0;
@@ -2967,7 +2968,7 @@ void helper_fxrstor(target_ulong ptr, int data64)
 
     if (env->cr[4] & CR4_OSFXSR_MASK) {
         /* XXX: finish it, endianness */
-        //ldl(ptr + 0x18);
+        env->mxcsr = ldl(ptr + 0x18);
         //ldl(ptr + 0x1c);
         nb_xmm_regs = 8 << data64;
         addr = ptr + 0xa0;
@@ -3209,6 +3210,23 @@ void helper_idivq_EAX_T0(void)
 
 #endif
 
+/* XXX: do it */
+int fpu_isnan(double a)
+{
+    return 0;
+}
+
+float approx_rsqrt(float a)
+{
+    return 1.0 / sqrt(a);
+}
+
+float approx_rcp(float a)
+{
+    return 1.0 / a;
+}
+
+
 #if !defined(CONFIG_USER_ONLY) 
 
 #define MMUSUFFIX _mmu

target-i386/helper2.c

@@ -158,6 +158,8 @@ void cpu_reset(CPUX86State *env)
     for(i = 0;i < 8; i++)
         env->fptags[i] = 1;
     env->fpuc = 0x37f;
+
+    env->mxcsr = 0x1f80;
 }
 
 void cpu_x86_close(CPUX86State *env)
@@ -376,15 +378,15 @@ void cpu_dump_state(CPUState *env, FILE *f,
     }
     if (flags & X86_DUMP_FPU) {
         cpu_fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n", 
-                (double)env->fpregs[0], 
-                (double)env->fpregs[1], 
-                (double)env->fpregs[2], 
-                (double)env->fpregs[3]);
+                (double)env->fpregs[0].d, 
+                (double)env->fpregs[1].d, 
+                (double)env->fpregs[2].d, 
+                (double)env->fpregs[3].d);
         cpu_fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n", 
-                (double)env->fpregs[4], 
-                (double)env->fpregs[5], 
-                (double)env->fpregs[7], 
-                (double)env->fpregs[8]);
+                (double)env->fpregs[4].d, 
+                (double)env->fpregs[5].d, 
+                (double)env->fpregs[7].d, 
+                (double)env->fpregs[8].d);
     }
 }
 
@@ -471,6 +473,14 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
         (env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
         tlb_flush(env, 1);
     }
+    /* SSE handling */
+    if (!(env->cpuid_features & CPUID_SSE))
+        new_cr4 &= ~CR4_OSFXSR_MASK;
+    if (new_cr4 & CR4_OSFXSR_MASK)
+        env->hflags |= HF_OSFXSR_MASK;
+    else
+        env->hflags &= ~HF_OSFXSR_MASK;
+
     env->cr[4] = new_cr4;
 }
 
@@ -800,7 +810,7 @@ void restore_native_fp_state(CPUState *env)
     fp->fptag = fptag;
     j = env->fpstt;
     for(i = 0;i < 8; i++) {
-        memcpy(&fp->fpregs1[i * 10], &env->fpregs[j], 10);
+        memcpy(&fp->fpregs1[i * 10], &env->fpregs[j].d, 10);
         j = (j + 1) & 7;
     }
     asm volatile ("frstor %0" : "=m" (*fp));
@@ -824,7 +834,7 @@ void save_native_fp_state(CPUState *env)
     }
     j = env->fpstt;
     for(i = 0;i < 8; i++) {
-        memcpy(&env->fpregs[j], &fp->fpregs1[i * 10], 10);
+        memcpy(&env->fpregs[j].d, &fp->fpregs1[i * 10], 10);
         j = (j + 1) & 7;
     }
     /* we must restore the default rounding state */

target-i386/op.c

@@ -752,11 +752,6 @@ void OPPROTO op_movswl_T0_T0(void)
     T0 = (int16_t)T0;
 }
 
-void OPPROTO op_movslq_T0_T0(void)
-{
-    T0 = (int32_t)T0;
-}
-
 void OPPROTO op_movzwl_T0_T0(void)
 {
     T0 = (uint16_t)T0;
@@ -768,6 +763,11 @@ void OPPROTO op_movswl_EAX_AX(void)
 }
 
 #ifdef TARGET_X86_64
+void OPPROTO op_movslq_T0_T0(void)
+{
+    T0 = (int32_t)T0;
+}
+
 void OPPROTO op_movslq_RAX_EAX(void)
 {
     EAX = (int32_t)EAX;
@@ -1695,9 +1695,9 @@ void OPPROTO op_flds_ST0_A0(void)
     new_fpstt = (env->fpstt - 1) & 7;
 #ifdef USE_FP_CONVERT
     FP_CONVERT.i32 = ldl(A0);
-    env->fpregs[new_fpstt] = FP_CONVERT.f;
+    env->fpregs[new_fpstt].d = FP_CONVERT.f;
 #else
-    env->fpregs[new_fpstt] = ldfl(A0);
+    env->fpregs[new_fpstt].d = ldfl(A0);
 #endif
     env->fpstt = new_fpstt;
     env->fptags[new_fpstt] = 0; /* validate stack entry */
@@ -1709,9 +1709,9 @@ void OPPROTO op_fldl_ST0_A0(void)
     new_fpstt = (env->fpstt - 1) & 7;
 #ifdef USE_FP_CONVERT
     FP_CONVERT.i64 = ldq(A0);
-    env->fpregs[new_fpstt] = FP_CONVERT.d;
+    env->fpregs[new_fpstt].d = FP_CONVERT.d;
 #else
-    env->fpregs[new_fpstt] = ldfq(A0);
+    env->fpregs[new_fpstt].d = ldfq(A0);
 #endif
     env->fpstt = new_fpstt;
     env->fptags[new_fpstt] = 0; /* validate stack entry */
@@ -1729,7 +1729,7 @@ void helper_fild_ST0_A0(void)
 {
     int new_fpstt;
     new_fpstt = (env->fpstt - 1) & 7;
-    env->fpregs[new_fpstt] = (CPU86_LDouble)ldsw(A0);
+    env->fpregs[new_fpstt].d = (CPU86_LDouble)ldsw(A0);
     env->fpstt = new_fpstt;
     env->fptags[new_fpstt] = 0; /* validate stack entry */
 }
@@ -1738,7 +1738,7 @@ void helper_fildl_ST0_A0(void)
 {
     int new_fpstt;
     new_fpstt = (env->fpstt - 1) & 7;
-    env->fpregs[new_fpstt] = (CPU86_LDouble)((int32_t)ldl(A0));
+    env->fpregs[new_fpstt].d = (CPU86_LDouble)((int32_t)ldl(A0));
     env->fpstt = new_fpstt;
     env->fptags[new_fpstt] = 0; /* validate stack entry */
 }
@@ -1747,7 +1747,7 @@ void helper_fildll_ST0_A0(void)
 {
     int new_fpstt;
     new_fpstt = (env->fpstt - 1) & 7;
-    env->fpregs[new_fpstt] = (CPU86_LDouble)((int64_t)ldq(A0));
+    env->fpregs[new_fpstt].d = (CPU86_LDouble)((int64_t)ldq(A0));
     env->fpstt = new_fpstt;
     env->fptags[new_fpstt] = 0; /* validate stack entry */
 }
@@ -1775,9 +1775,9 @@ void OPPROTO op_fild_ST0_A0(void)
     new_fpstt = (env->fpstt - 1) & 7;
 #ifdef USE_FP_CONVERT
     FP_CONVERT.i32 = ldsw(A0);
-    env->fpregs[new_fpstt] = (CPU86_LDouble)FP_CONVERT.i32;
+    env->fpregs[new_fpstt].d = (CPU86_LDouble)FP_CONVERT.i32;
 #else
-    env->fpregs[new_fpstt] = (CPU86_LDouble)ldsw(A0);
+    env->fpregs[new_fpstt].d = (CPU86_LDouble)ldsw(A0);
 #endif
     env->fpstt = new_fpstt;
     env->fptags[new_fpstt] = 0; /* validate stack entry */
@@ -1789,9 +1789,9 @@ void OPPROTO op_fildl_ST0_A0(void)
     new_fpstt = (env->fpstt - 1) & 7;
 #ifdef USE_FP_CONVERT
     FP_CONVERT.i32 = (int32_t) ldl(A0);
-    env->fpregs[new_fpstt] = (CPU86_LDouble)FP_CONVERT.i32;
+    env->fpregs[new_fpstt].d = (CPU86_LDouble)FP_CONVERT.i32;
 #else
-    env->fpregs[new_fpstt] = (CPU86_LDouble)((int32_t)ldl(A0));
+    env->fpregs[new_fpstt].d = (CPU86_LDouble)((int32_t)ldl(A0));
 #endif
     env->fpstt = new_fpstt;
     env->fptags[new_fpstt] = 0; /* validate stack entry */
@@ -1803,9 +1803,9 @@ void OPPROTO op_fildll_ST0_A0(void)
     new_fpstt = (env->fpstt - 1) & 7;
 #ifdef USE_FP_CONVERT
     FP_CONVERT.i64 = (int64_t) ldq(A0);
-    env->fpregs[new_fpstt] = (CPU86_LDouble)FP_CONVERT.i64;
+    env->fpregs[new_fpstt].d = (CPU86_LDouble)FP_CONVERT.i64;
 #else
-    env->fpregs[new_fpstt] = (CPU86_LDouble)((int64_t)ldq(A0));
+    env->fpregs[new_fpstt].d = (CPU86_LDouble)((int64_t)ldq(A0));
 #endif
     env->fpstt = new_fpstt;
     env->fptags[new_fpstt] = 0; /* validate stack entry */
@@ -2322,6 +2322,29 @@ void OPPROTO op_movo(void)
     memcpy16(d, s);
 }
 
+void OPPROTO op_movq(void)
+{
+    uint64_t *d, *s;
+    d = (uint64_t *)((char *)env + PARAM1);
+    s = (uint64_t *)((char *)env + PARAM2);
+    *d = *s;
+}
+
+void OPPROTO op_movl(void)
+{
+    uint32_t *d, *s;
+    d = (uint32_t *)((char *)env + PARAM1);
+    s = (uint32_t *)((char *)env + PARAM2);
+    *d = *s;
+}
+
+void OPPROTO op_movq_env_0(void)
+{
+    uint64_t *d;
+    d = (uint64_t *)((char *)env + PARAM1);
+    *d = 0;
+}
+
 void OPPROTO op_fxsave_A0(void)
 {
     helper_fxsave(A0, PARAM1);
@@ -2331,3 +2354,24 @@ void OPPROTO op_fxrstor_A0(void)
 {
     helper_fxrstor(A0, PARAM1);
 }
+
+/* XXX: optimize by storing fptt and fptags in the static cpu state */
+void OPPROTO op_enter_mmx(void)
+{
+    env->fpstt = 0;
+    *(uint32_t *)(env->fptags) = 0;
+    *(uint32_t *)(env->fptags + 4) = 0;
+}
+
+void OPPROTO op_emms(void)
+{
+    /* set to empty state */
+    *(uint32_t *)(env->fptags) = 0x01010101;
+    *(uint32_t *)(env->fptags + 4) = 0x01010101;
+}
+
+#define SHIFT 0
+#include "ops_sse.h"
+
+#define SHIFT 1
+#include "ops_sse.h"

target-i386/ops_mem.h

@@ -80,7 +80,21 @@ void OPPROTO glue(glue(op_stl, MEMSUFFIX), _T1_A0)(void)
     glue(stl, MEMSUFFIX)(A0, T1);
 }
 
-/* SSE support */
+/* SSE/MMX support */
+void OPPROTO glue(glue(op_ldq, MEMSUFFIX), _env_A0)(void)
+{
+    uint64_t *p;
+    p = (uint64_t *)((char *)env + PARAM1);
+    *p = glue(ldq, MEMSUFFIX)(A0);
+}
+
+void OPPROTO glue(glue(op_stq, MEMSUFFIX), _env_A0)(void)
+{
+    uint64_t *p;
+    p = (uint64_t *)((char *)env + PARAM1);
+    glue(stq, MEMSUFFIX)(A0, *p);
+}
+
 void OPPROTO glue(glue(op_ldo, MEMSUFFIX), _env_A0)(void)
 {
     XMMReg *p;

vl.c

@@ -2082,15 +2082,14 @@ static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
 void cpu_save(QEMUFile *f, void *opaque)
 {
     CPUState *env = opaque;
-    uint16_t fptag, fpus, fpuc;
+    uint16_t fptag, fpus, fpuc, fpregs_format;
     uint32_t hflags;
     int i;
-
+    
     for(i = 0; i < CPU_NB_REGS; i++)
         qemu_put_betls(f, &env->regs[i]);
     qemu_put_betls(f, &env->eip);
     qemu_put_betls(f, &env->eflags);
-    qemu_put_betl(f, 0); /* XXX: suppress that */
     hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
     qemu_put_be32s(f, &hflags);
     
@@ -2098,23 +2097,37 @@ void cpu_save(QEMUFile *f, void *opaque)
     fpuc = env->fpuc;
     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
     fptag = 0;
-    for (i=7; i>=0; i--) {
-	fptag <<= 2;
-	if (env->fptags[i]) {
-            fptag |= 3;
-        }
+    for(i = 0; i < 8; i++) {
+        fptag |= ((!env->fptags[i]) << i);
     }
     
     qemu_put_be16s(f, &fpuc);
     qemu_put_be16s(f, &fpus);
     qemu_put_be16s(f, &fptag);
 
+#ifdef USE_X86LDOUBLE
+    fpregs_format = 0;
+#else
+    fpregs_format = 1;
+#endif
+    qemu_put_be16s(f, &fpregs_format);
+    
     for(i = 0; i < 8; i++) {
         uint64_t mant;
         uint16_t exp;
-        cpu_get_fp80(&mant, &exp, env->fpregs[i]);
+#ifdef USE_X86LDOUBLE
+        /* we save the real CPU data (in case of MMX usage only 'mant'
+           contains the MMX register */
+        cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
         qemu_put_be64(f, mant);
         qemu_put_be16(f, exp);
+#else
+        /* if we use doubles for float emulation, we save the doubles to
+           avoid losing information in case of MMX usage. It can give
+           problems if the image is restored on a CPU where long
+           doubles are used instead. */
+        qemu_put_be64(f, env->fpregs[i].xmm.MMX_Q(0));
+#endif
     }
 
     for(i = 0; i < 6; i++)
@@ -2139,12 +2152,14 @@ void cpu_save(QEMUFile *f, void *opaque)
     /* MMU */
     qemu_put_be32s(f, &env->a20_mask);
 
-#ifdef TARGET_X86_64
+    /* XMM */
+    qemu_put_be32s(f, &env->mxcsr);
     for(i = 0; i < CPU_NB_REGS; i++) {
         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
     }
 
+#ifdef TARGET_X86_64
     qemu_put_be64s(f, &env->efer);
     qemu_put_be64s(f, &env->star);
     qemu_put_be64s(f, &env->lstar);
@@ -2154,40 +2169,97 @@ void cpu_save(QEMUFile *f, void *opaque)
 #endif
 }
 
+/* XXX: add that in a FPU generic layer */
+union x86_longdouble {
+    uint64_t mant;
+    uint16_t exp;
+};
+
+#define MANTD1(fp)	(fp & ((1LL << 52) - 1))
+#define EXPBIAS1 1023
+#define EXPD1(fp)	((fp >> 52) & 0x7FF)
+#define SIGND1(fp)	((fp >> 32) & 0x80000000)
+
+static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
+{
+    int e;
+    /* mantissa */
+    p->mant = (MANTD1(temp) << 11) | (1LL << 63);
+    /* exponent + sign */
+    e = EXPD1(temp) - EXPBIAS1 + 16383;
+    e |= SIGND1(temp) >> 16;
+    p->exp = e;
+}
+
 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 {
     CPUState *env = opaque;
-    int i;
+    int i, guess_mmx;
     uint32_t hflags;
-    uint16_t fpus, fpuc, fptag;
+    uint16_t fpus, fpuc, fptag, fpregs_format;
 
-    if (version_id != 2)
+    if (version_id != 3)
         return -EINVAL;
     for(i = 0; i < CPU_NB_REGS; i++)
         qemu_get_betls(f, &env->regs[i]);
     qemu_get_betls(f, &env->eip);
     qemu_get_betls(f, &env->eflags);
-    qemu_get_betl(f); /* XXX: suppress that */
     qemu_get_be32s(f, &hflags);
 
     qemu_get_be16s(f, &fpuc);
     qemu_get_be16s(f, &fpus);
     qemu_get_be16s(f, &fptag);
-
+    qemu_get_be16s(f, &fpregs_format);
+    
+    /* NOTE: we cannot always restore the FPU state if the image come
+       from a host with a different 'USE_X86LDOUBLE' define. We guess
+       if we are in an MMX state to restore correctly in that case. */
+    guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
     for(i = 0; i < 8; i++) {
         uint64_t mant;
         uint16_t exp;
-        mant = qemu_get_be64(f);
-        exp = qemu_get_be16(f);
-        env->fpregs[i] = cpu_set_fp80(mant, exp);
+        union x86_longdouble *p;
+        
+        switch(fpregs_format) {
+        case 0:
+            mant = qemu_get_be64(f);
+            exp = qemu_get_be16(f);
+#ifdef USE_X86LDOUBLE
+            env->fpregs[i].d = cpu_set_fp80(mant, exp);
+#else
+            /* difficult case */
+            if (guess_mmx)
+                env->fpregs[i].xmm.MMX_Q(0) = mant;
+            else
+                env->fpregs[i].d = cpu_set_fp80(mant, exp);
+#endif
+            break;
+        case 1:
+            mant = qemu_get_be64(f);
+#ifdef USE_X86LDOUBLE
+            /* difficult case */
+            p = (void *)&env->fpregs[i];
+            if (guess_mmx) {
+                p->mant = mant;
+                p->exp = 0xffff;
+            } else {
+                fp64_to_fp80(p, mant);
+            }
+#else
+            env->fpregs[i].xmm.MMX_Q(0) = mant;
+#endif            
+            break;
+        default:
+            return -EINVAL;
+        }
     }
 
     env->fpuc = fpuc;
     env->fpstt = (fpus >> 11) & 7;
     env->fpus = fpus & ~0x3800;
+    fptag ^= 0xff;
     for(i = 0; i < 8; i++) {
-        env->fptags[i] = ((fptag & 3) == 3);
-        fptag >>= 2;
+        env->fptags[i] = (fptag >> i) & 1;
     }
     
     for(i = 0; i < 6; i++)
@@ -2212,12 +2284,13 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     /* MMU */
     qemu_get_be32s(f, &env->a20_mask);
 
-#ifdef TARGET_X86_64
+    qemu_get_be32s(f, &env->mxcsr);
     for(i = 0; i < CPU_NB_REGS; i++) {
         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
     }
 
+#ifdef TARGET_X86_64
     qemu_get_be64s(f, &env->efer);
     qemu_get_be64s(f, &env->star);
     qemu_get_be64s(f, &env->lstar);
@@ -3433,7 +3506,7 @@ int main(int argc, char **argv)
     cpu_single_env = env;
 
     register_savevm("timer", 0, 1, timer_save, timer_load, env);
-    register_savevm("cpu", 0, 2, cpu_save, cpu_load, env);
+    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
     register_savevm("ram", 0, 1, ram_save, ram_load, NULL);
     qemu_register_reset(main_cpu_reset, global_env);