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ppc/xive: Add xive_tctx_pipr_set() helper function

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Have xive_tctx_notify() also set the new PIPR value and rename it to
xive_tctx_pipr_set(). This can replace the last xive_tctx_pipr_update()
caller because it does not need to update IPB (it already sets it).

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Michael Kowal <kowal@linux.ibm.com>
Tested-by: Gautam Menghani <gautam@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-36-npiggin@gmail.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Nicholas Piggin
2025-07-21 08:03:53 +02:00
committed by Cédric Le Goater
parent cf454eaa96
commit 64a18e0c37
3 changed files with 20 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/intc/xive.c
+11 -28
View File
@@ -125,12 +125,16 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring)
return ((uint64_t)nsr << 8) | sig_regs[TM_CPPR];
}
void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level)
/* Change PIPR and calculate NSR and irq based on PIPR, CPPR, group */
void xive_tctx_pipr_set(XiveTCTX *tctx, uint8_t ring, uint8_t pipr,
uint8_t group_level)
{
uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
uint8_t *regs = &tctx->regs[ring];
if (sig_regs[TM_PIPR] < sig_regs[TM_CPPR]) {
sig_regs[TM_PIPR] = pipr;
if (pipr < sig_regs[TM_CPPR]) {
switch (ring) {
case TM_QW1_OS:
sig_regs[TM_NSR] = TM_QW1_NSR_EO | (group_level & 0x3F);
@@ -145,7 +149,7 @@ void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level)
g_assert_not_reached();
}
trace_xive_tctx_notify(tctx->cs->cpu_index, ring,
regs[TM_IPB], sig_regs[TM_PIPR],
regs[TM_IPB], pipr,
sig_regs[TM_CPPR], sig_regs[TM_NSR]);
qemu_irq_raise(xive_tctx_output(tctx, ring));
} else {
@@ -213,29 +217,10 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
}
}
sig_regs[TM_PIPR] = pipr_min;
/* CPPR has changed, check if we need to raise a pending exception */
xive_tctx_notify(tctx, ring_min, 0);
/* CPPR has changed, this may present or preclude a pending exception */
xive_tctx_pipr_set(tctx, ring_min, pipr_min, 0);
}
void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
uint8_t group_level)
{
uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
uint8_t *regs = &tctx->regs[ring];
if (group_level == 0) {
/* VP-specific */
regs[TM_IPB] |= xive_priority_to_ipb(priority);
sig_regs[TM_PIPR] = xive_ipb_to_pipr(regs[TM_IPB]);
} else {
/* VP-group */
sig_regs[TM_PIPR] = xive_priority_to_pipr(priority);
}
xive_tctx_notify(tctx, ring, group_level);
}
static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX *tctx, uint8_t ring)
{
uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
@@ -244,8 +229,7 @@ static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX *tctx, uint8_t ring)
/* Does not support a presented group interrupt */
g_assert(!xive_nsr_indicates_group_exception(ring, sig_regs[TM_NSR]));
sig_regs[TM_PIPR] = xive_ipb_to_pipr(regs[TM_IPB]);
xive_tctx_notify(tctx, ring, 0);
xive_tctx_pipr_set(tctx, ring, xive_ipb_to_pipr(regs[TM_IPB]), 0);
}
void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
@@ -264,8 +248,7 @@ void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
}
g_assert(pipr <= xive_ipb_to_pipr(regs[TM_IPB]));
g_assert(pipr < sig_regs[TM_PIPR]);
sig_regs[TM_PIPR] = pipr;
xive_tctx_notify(tctx, ring, group_level);
xive_tctx_pipr_set(tctx, ring, pipr, group_level);
}
/*
hw/intc/xive2.c
+7 -9
View File
@@ -966,10 +966,10 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
}
/*
* Compute the PIPR based on the restored state.
* Set the PIPR/NSR based on the restored state.
* It will raise the External interrupt signal if needed.
*/
xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level);
xive_tctx_pipr_set(tctx, TM_QW1_OS, backlog_prio, backlog_level);
}
/*
@@ -1144,8 +1144,7 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
}
/* interrupt is VP directed, pending in IPB */
sig_regs[TM_PIPR] = cppr;
xive_tctx_notify(tctx, ring, 0); /* Ensure interrupt is cleared */
xive_tctx_pipr_set(tctx, ring, cppr, 0);
return;
} else {
/* CPPR was lowered, but still above PIPR. No action needed. */
@@ -1255,11 +1254,10 @@ again:
pipr_min = backlog_prio;
}
/* PIPR should not be set to a value greater than CPPR */
sig_regs[TM_PIPR] = (pipr_min > cppr) ? cppr : pipr_min;
/* CPPR has changed, check if we need to raise a pending exception */
xive_tctx_notify(tctx, ring_min, group_level);
if (pipr_min > cppr) {
pipr_min = cppr;
}
xive_tctx_pipr_set(tctx, ring_min, pipr_min, group_level);
}
void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
include/hw/ppc/xive.h
+2 -3
View File
@@ -584,12 +584,11 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf);
Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx);
void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
uint8_t group_level);
void xive_tctx_pipr_set(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
uint8_t group_level);
void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
uint8_t group_level);
void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring);
void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level);
uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring);
/*