mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into staging
Misc HW patch queue - Deprecate a pair of untested microblaze big-endian machines (Philippe) - Arch-agnostic CPU topology checks at machine level (Zhao) - Cleanups on PPC E500 (Bernhard) - Various conversions to DEFINE_TYPES() macro (Bernhard) - Fix RISC-V _pext_u64() name clashing (Pierrick) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmcqqycACgkQ4+MsLN6t # wN7TfhAAkAjpWxFGptNw28LPpnZY/NTGKyXQrIEHu3XnJsZ28c/KZeCAYUUC6/q7 # tAnBMb5GIn2VTyt+ElORseFtHStThoR8WMrcQSlGvCZei9lRNKCW0pVIEUgLZEtT # u8lChpaVAn8gXb885xlaCBBP4SuFHEpASSfWy0mYDIqZL3oRhr9AQ/KwzHFqenbK # Uva4BCWRVnYju6MhfA/pmVP011SUTdCu/fsBTIJT3Xn7Sp7fRNShIzt+1rbmPnR2 # hhRl5bMKUgDUjX5GxeP0LOj/XdX9svlqL42imNQT5FFUMIR6qbrwj4U841mt0uuI # FcthAoILvA2XUJoTESq0iXUoN4FQLtc01onY6k06EoZAnn8WRZRp2dNdu8fYmHMX # y3pcXBK6wEhBVZ2DcGVf1txmieUc4TZohOridU1Xfckp+XVl6J3LtTKJIE56Eh68 # S9OJW1Sz2Io/8FJFvKStX0bhV0nBUyUXmi5PjV4vurS6Gy1aVodiiq3ls6baX05z # /Y8DJGpPByA+GI2prdwq9oTIhEIU2bJDDz32NkwHM99SE25h+iyh21Ap5Ojkegm7 # 1squIskxX3QLtEMxBCe+XIKzEZ51kzNZxmLXvCFW5YetypNdhyULqH/UDWt7hIDN # BSh2w1g/lSw9n6DtEN3rURYAR/uV7/7IMEP8Td2wvcDX4o95Fkw= # =q0cF # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 23:32:55 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20241105' of https://github.com/philmd/qemu: (29 commits) hw/riscv/iommu: fix build error with clang hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro hw/rtc/ds1338: Prefer DEFINE_TYPES() macro hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro hw/sd/sdhci: Prefer DEFINE_TYPES() macro hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro hw/net/fsl_etsec/miim: Reuse MII constants hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access hw/ppc/mpc8544_guts: Populate POR PLL ratio status register hw/ppc/e500: Add missing device tree properties to i2c controller node hw/ppc/e500: Remove unused "irqs" parameter hw/ppc/e500: Prefer QOM cast hw/core: Add a helper to check the cache topology level hw/core: Check smp cache topology support for machine ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
@@ -2,5 +2,3 @@
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# Boards are selected by default, uncomment to keep out of the build.
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# CONFIG_PETALOGIX_S3ADSP1800=n
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# CONFIG_PETALOGIX_ML605=n
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# CONFIG_XLNX_ZYNQMP_PMU=n
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@@ -1,3 +1,6 @@
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# Default configuration for microblazeel-softmmu
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include ../microblaze-softmmu/default.mak
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# Boards are selected by default, uncomment to keep out of the build.
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# CONFIG_PETALOGIX_S3ADSP1800=n
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# CONFIG_PETALOGIX_ML605=n
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# CONFIG_XLNX_ZYNQMP_PMU=n
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@@ -271,6 +271,12 @@ BMC and a witherspoon like OpenPOWER system. It was used for bring up
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of the AST2600 SoC in labs. It can be easily replaced by the
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``rainier-bmc`` machine which is a real product.
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Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2)
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''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
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Both ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` were added for little endian
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CPUs. Big endian support is not tested.
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Backend options
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---------------
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+8
-13
@@ -47,7 +47,6 @@
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#include "qemu/bitops.h"
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#include "qemu/host-utils.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/option.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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@@ -947,20 +946,16 @@ static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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}
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static const TypeInfo pflash_cfi01_info = {
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.name = TYPE_PFLASH_CFI01,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PFlashCFI01),
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.class_init = pflash_cfi01_class_init,
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static const TypeInfo pflash_cfi01_types[] = {
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{
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.name = TYPE_PFLASH_CFI01,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PFlashCFI01),
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.class_init = pflash_cfi01_class_init,
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},
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};
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static void pflash_cfi01_register_types(void)
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{
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type_register_static(&pflash_cfi01_info);
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}
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type_init(pflash_cfi01_register_types)
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DEFINE_TYPES(pflash_cfi01_types)
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PFlashCFI01 *pflash_cfi01_register(hwaddr base,
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const char *name,
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@@ -261,6 +261,72 @@ void machine_parse_smp_config(MachineState *ms,
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}
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}
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static bool machine_check_topo_support(MachineState *ms,
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CpuTopologyLevel topo,
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Error **errp)
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{
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MachineClass *mc = MACHINE_GET_CLASS(ms);
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if ((topo == CPU_TOPOLOGY_LEVEL_MODULE && !mc->smp_props.modules_supported) ||
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(topo == CPU_TOPOLOGY_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) ||
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(topo == CPU_TOPOLOGY_LEVEL_DIE && !mc->smp_props.dies_supported) ||
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(topo == CPU_TOPOLOGY_LEVEL_BOOK && !mc->smp_props.books_supported) ||
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(topo == CPU_TOPOLOGY_LEVEL_DRAWER && !mc->smp_props.drawers_supported)) {
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error_setg(errp,
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"Invalid topology level: %s. "
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"The topology level is not supported by this machine",
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CpuTopologyLevel_str(topo));
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return false;
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}
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return true;
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}
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bool machine_parse_smp_cache(MachineState *ms,
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const SmpCachePropertiesList *caches,
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Error **errp)
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{
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MachineClass *mc = MACHINE_GET_CLASS(ms);
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const SmpCachePropertiesList *node;
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DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX);
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for (node = caches; node; node = node->next) {
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/* Prohibit users from repeating settings. */
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if (test_bit(node->value->cache, caches_bitmap)) {
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error_setg(errp,
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"Invalid cache properties: %s. "
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"The cache properties are duplicated",
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CacheLevelAndType_str(node->value->cache));
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return false;
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}
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machine_set_cache_topo_level(ms, node->value->cache,
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node->value->topology);
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set_bit(node->value->cache, caches_bitmap);
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}
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for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) {
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const SmpCacheProperties *props = &ms->smp_cache.props[i];
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/*
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* Reject non "default" topology level if the cache isn't
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* supported by the machine.
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*/
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if (props->topology != CPU_TOPOLOGY_LEVEL_DEFAULT &&
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!mc->smp_props.cache_supported[props->cache]) {
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error_setg(errp,
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"%s cache topology not supported by this machine",
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CacheLevelAndType_str(node->value->cache));
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return false;
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}
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if (!machine_check_topo_support(ms, props->topology, errp)) {
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return false;
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}
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}
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return true;
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}
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unsigned int machine_topo_get_cores_per_socket(const MachineState *ms)
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{
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return ms->smp.cores * ms->smp.modules * ms->smp.clusters * ms->smp.dies;
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@@ -270,3 +336,63 @@ unsigned int machine_topo_get_threads_per_socket(const MachineState *ms)
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{
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return ms->smp.threads * machine_topo_get_cores_per_socket(ms);
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}
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CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms,
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CacheLevelAndType cache)
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{
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return ms->smp_cache.props[cache].topology;
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}
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void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
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CpuTopologyLevel level)
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{
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ms->smp_cache.props[cache].topology = level;
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}
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/*
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* When both cache1 and cache2 are configured with specific topology levels
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* (not default level), is cache1's topology level higher than cache2?
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*/
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static bool smp_cache_topo_cmp(const SmpCache *smp_cache,
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CacheLevelAndType cache1,
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CacheLevelAndType cache2)
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{
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/*
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* Before comparing, the "default" topology level should be replaced
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* with the specific level.
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*/
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assert(smp_cache->props[cache1].topology != CPU_TOPOLOGY_LEVEL_DEFAULT);
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return smp_cache->props[cache1].topology > smp_cache->props[cache2].topology;
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}
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/*
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* Currently, we have no way to expose the arch-specific default cache model
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* because the cache model is sometimes related to the CPU model (e.g., i386).
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*
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* We can only check the correctness of the cache topology after the arch loads
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* the user-configured cache model from MachineState and consumes the special
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* "default" level by replacing it with the specific level.
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*/
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bool machine_check_smp_cache(const MachineState *ms, Error **errp)
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{
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if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1D,
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CACHE_LEVEL_AND_TYPE_L2) ||
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smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1I,
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CACHE_LEVEL_AND_TYPE_L2)) {
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error_setg(errp,
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"Invalid smp cache topology. "
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"L2 cache topology level shouldn't be lower than L1 cache");
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return false;
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}
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if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L2,
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CACHE_LEVEL_AND_TYPE_L3)) {
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error_setg(errp,
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"Invalid smp cache topology. "
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"L3 cache topology level shouldn't be lower than L2 cache");
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return false;
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}
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return true;
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}
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@@ -11,10 +11,12 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/accel.h"
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#include "sysemu/replay.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "qapi/qapi-visit-machine.h"
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#include "qemu/madvise.h"
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@@ -907,6 +909,40 @@ static void machine_set_smp(Object *obj, Visitor *v, const char *name,
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machine_parse_smp_config(ms, config, errp);
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}
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static void machine_get_smp_cache(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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MachineState *ms = MACHINE(obj);
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SmpCache *cache = &ms->smp_cache;
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SmpCachePropertiesList *head = NULL;
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SmpCachePropertiesList **tail = &head;
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for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) {
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SmpCacheProperties *node = g_new(SmpCacheProperties, 1);
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node->cache = cache->props[i].cache;
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node->topology = cache->props[i].topology;
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QAPI_LIST_APPEND(tail, node);
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}
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visit_type_SmpCachePropertiesList(v, name, &head, errp);
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qapi_free_SmpCachePropertiesList(head);
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}
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static void machine_set_smp_cache(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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MachineState *ms = MACHINE(obj);
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SmpCachePropertiesList *caches;
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if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) {
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return;
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}
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machine_parse_smp_cache(ms, caches, errp);
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qapi_free_SmpCachePropertiesList(caches);
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}
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static void machine_get_boot(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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@@ -1067,6 +1103,11 @@ static void machine_class_init(ObjectClass *oc, void *data)
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object_class_property_set_description(oc, "smp",
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"CPU topology");
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object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper",
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machine_get_smp_cache, machine_set_smp_cache, NULL, NULL);
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object_class_property_set_description(oc, "smp-cache",
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"Cache properties list for SMP machine");
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object_class_property_add(oc, "phandle-start", "int",
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machine_get_phandle_start, machine_set_phandle_start,
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NULL, NULL);
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@@ -1205,6 +1246,11 @@ static void machine_initfn(Object *obj)
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ms->smp.cores = 1;
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ms->smp.threads = 1;
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for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) {
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ms->smp_cache.props[i].cache = (CacheLevelAndType)i;
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ms->smp_cache.props[i].topology = CPU_TOPOLOGY_LEVEL_DEFAULT;
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}
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machine_copy_boot_config(ms, &(BootConfiguration){ 0 });
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}
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|
||||
|
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+9
-13
@@ -23,7 +23,6 @@
|
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#include "hw/irq.h"
|
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#include "hw/sysbus.h"
|
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#include "migration/vmstate.h"
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#include "qemu/module.h"
|
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#include "qom/object.h"
|
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|
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#define TYPE_MPC8XXX_GPIO "mpc8xxx_gpio"
|
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@@ -208,17 +207,14 @@ static void mpc8xxx_gpio_class_init(ObjectClass *klass, void *data)
|
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device_class_set_legacy_reset(dc, mpc8xxx_gpio_reset);
|
||||
}
|
||||
|
||||
static const TypeInfo mpc8xxx_gpio_info = {
|
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.name = TYPE_MPC8XXX_GPIO,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(MPC8XXXGPIOState),
|
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.instance_init = mpc8xxx_gpio_initfn,
|
||||
.class_init = mpc8xxx_gpio_class_init,
|
||||
static const TypeInfo mpc8xxx_gpio_types[] = {
|
||||
{
|
||||
.name = TYPE_MPC8XXX_GPIO,
|
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.parent = TYPE_SYS_BUS_DEVICE,
|
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.instance_size = sizeof(MPC8XXXGPIOState),
|
||||
.instance_init = mpc8xxx_gpio_initfn,
|
||||
.class_init = mpc8xxx_gpio_class_init,
|
||||
},
|
||||
};
|
||||
|
||||
static void mpc8xxx_gpio_register_types(void)
|
||||
{
|
||||
type_register_static(&mpc8xxx_gpio_info);
|
||||
}
|
||||
|
||||
type_init(mpc8xxx_gpio_register_types)
|
||||
DEFINE_TYPES(mpc8xxx_gpio_types)
|
||||
|
||||
+13
-16
@@ -20,10 +20,10 @@
|
||||
#include "qemu/osdep.h"
|
||||
#include "hw/i2c/i2c.h"
|
||||
#include "hw/irq.h"
|
||||
#include "qemu/module.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "qom/object.h"
|
||||
#include "trace.h"
|
||||
|
||||
/* #define DEBUG_I2C */
|
||||
|
||||
@@ -224,8 +224,8 @@ static uint64_t mpc_i2c_read(void *opaque, hwaddr addr, unsigned size)
|
||||
break;
|
||||
}
|
||||
|
||||
DPRINTF("%s: addr " HWADDR_FMT_plx " %02" PRIx32 "\n", __func__,
|
||||
addr, value);
|
||||
trace_mpc_i2c_read(addr, value);
|
||||
|
||||
return (uint64_t)value;
|
||||
}
|
||||
|
||||
@@ -234,8 +234,8 @@ static void mpc_i2c_write(void *opaque, hwaddr addr,
|
||||
{
|
||||
MPCI2CState *s = opaque;
|
||||
|
||||
DPRINTF("%s: addr " HWADDR_FMT_plx " val %08" PRIx64 "\n", __func__,
|
||||
addr, value);
|
||||
trace_mpc_i2c_write(addr, value);
|
||||
|
||||
switch (addr) {
|
||||
case MPC_I2C_ADR:
|
||||
s->adr = value & CADR_MASK;
|
||||
@@ -344,16 +344,13 @@ static void mpc_i2c_class_init(ObjectClass *klass, void *data)
|
||||
dc->desc = "MPC I2C Controller";
|
||||
}
|
||||
|
||||
static const TypeInfo mpc_i2c_type_info = {
|
||||
.name = TYPE_MPC_I2C,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(MPCI2CState),
|
||||
.class_init = mpc_i2c_class_init,
|
||||
static const TypeInfo mpc_i2c_types[] = {
|
||||
{
|
||||
.name = TYPE_MPC_I2C,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(MPCI2CState),
|
||||
.class_init = mpc_i2c_class_init,
|
||||
},
|
||||
};
|
||||
|
||||
static void mpc_i2c_register_types(void)
|
||||
{
|
||||
type_register_static(&mpc_i2c_type_info);
|
||||
}
|
||||
|
||||
type_init(mpc_i2c_register_types)
|
||||
DEFINE_TYPES(mpc_i2c_types)
|
||||
|
||||
+8
-11
@@ -151,19 +151,16 @@ static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data)
|
||||
dc->user_creatable = false;
|
||||
}
|
||||
|
||||
static const TypeInfo smbus_eeprom_info = {
|
||||
.name = TYPE_SMBUS_EEPROM,
|
||||
.parent = TYPE_SMBUS_DEVICE,
|
||||
.instance_size = sizeof(SMBusEEPROMDevice),
|
||||
.class_init = smbus_eeprom_class_initfn,
|
||||
static const TypeInfo smbus_eeprom_types[] = {
|
||||
{
|
||||
.name = TYPE_SMBUS_EEPROM,
|
||||
.parent = TYPE_SMBUS_DEVICE,
|
||||
.instance_size = sizeof(SMBusEEPROMDevice),
|
||||
.class_init = smbus_eeprom_class_initfn,
|
||||
},
|
||||
};
|
||||
|
||||
static void smbus_eeprom_register_types(void)
|
||||
{
|
||||
type_register_static(&smbus_eeprom_info);
|
||||
}
|
||||
|
||||
type_init(smbus_eeprom_register_types)
|
||||
DEFINE_TYPES(smbus_eeprom_types)
|
||||
|
||||
void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf)
|
||||
{
|
||||
|
||||
@@ -35,6 +35,11 @@ aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t va
|
||||
aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s send %d/%d 0x%02x"
|
||||
aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) "%s recv %d/%d 0x%02x"
|
||||
|
||||
# mpc_i2c.c
|
||||
|
||||
mpc_i2c_read(uint64_t addr, uint32_t value) "[0x%" PRIx64 "] -> 0x%02" PRIx32
|
||||
mpc_i2c_write(uint64_t addr, uint32_t value) "[0x%" PRIx64 "] <- 0x%02" PRIx32
|
||||
|
||||
# npcm7xx_smbus.c
|
||||
|
||||
npcm7xx_smbus_read(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
|
||||
|
||||
@@ -273,12 +273,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
|
||||
|
||||
if (ms->smp.modules > 1) {
|
||||
env->nr_modules = ms->smp.modules;
|
||||
set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo);
|
||||
set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo);
|
||||
}
|
||||
|
||||
if (ms->smp.dies > 1) {
|
||||
env->nr_dies = ms->smp.dies;
|
||||
set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo);
|
||||
set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -90,7 +90,7 @@ petalogix_ml605_init(MachineState *machine)
|
||||
object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort);
|
||||
object_property_set_bool(OBJECT(cpu), "dcache-writeback", true,
|
||||
&error_abort);
|
||||
object_property_set_bool(OBJECT(cpu), "endianness", true, &error_abort);
|
||||
object_property_set_bool(OBJECT(cpu), "little-endian", true, &error_abort);
|
||||
qdev_realize(DEVICE(cpu), NULL, &error_abort);
|
||||
|
||||
/* Attach emulated BRAM through the LMB. */
|
||||
@@ -213,7 +213,12 @@ petalogix_ml605_init(MachineState *machine)
|
||||
|
||||
static void petalogix_ml605_machine_init(MachineClass *mc)
|
||||
{
|
||||
mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian";
|
||||
#if TARGET_BIG_ENDIAN
|
||||
mc->desc = "PetaLogix linux refdesign for xilinx ml605 (big endian)";
|
||||
mc->deprecation_reason = "big endian support is not tested";
|
||||
#else
|
||||
mc->desc = "PetaLogix linux refdesign for xilinx ml605 (little endian)";
|
||||
#endif
|
||||
mc->init = petalogix_ml605_init;
|
||||
}
|
||||
|
||||
|
||||
@@ -55,6 +55,9 @@
|
||||
#define ETHLITE_IRQ 1
|
||||
#define UARTLITE_IRQ 3
|
||||
|
||||
#define TYPE_PETALOGIX_S3ADSP1800_MACHINE \
|
||||
MACHINE_TYPE_NAME("petalogix-s3adsp1800")
|
||||
|
||||
static void
|
||||
petalogix_s3adsp1800_init(MachineState *machine)
|
||||
{
|
||||
@@ -71,6 +74,8 @@ petalogix_s3adsp1800_init(MachineState *machine)
|
||||
|
||||
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
|
||||
object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort);
|
||||
object_property_set_bool(OBJECT(cpu), "little-endian",
|
||||
!TARGET_BIG_ENDIAN, &error_abort);
|
||||
qdev_realize(DEVICE(cpu), NULL, &error_abort);
|
||||
|
||||
/* Attach emulated BRAM through the LMB. */
|
||||
@@ -122,7 +127,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
|
||||
|
||||
create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);
|
||||
create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000);
|
||||
|
||||
microblaze_load_kernel(cpu, ddr_base, ram_size,
|
||||
machine->initrd_filename,
|
||||
@@ -130,11 +135,21 @@ petalogix_s3adsp1800_init(MachineState *machine)
|
||||
NULL);
|
||||
}
|
||||
|
||||
static void petalogix_s3adsp1800_machine_init(MachineClass *mc)
|
||||
static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800";
|
||||
mc->init = petalogix_s3adsp1800_init;
|
||||
mc->is_default = true;
|
||||
}
|
||||
|
||||
DEFINE_MACHINE("petalogix-s3adsp1800", petalogix_s3adsp1800_machine_init)
|
||||
static const TypeInfo petalogix_s3adsp1800_machine_types[] = {
|
||||
{
|
||||
.name = TYPE_PETALOGIX_S3ADSP1800_MACHINE,
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = petalogix_s3adsp1800_machine_class_init,
|
||||
},
|
||||
};
|
||||
|
||||
DEFINE_TYPES(petalogix_s3adsp1800_machine_types)
|
||||
|
||||
@@ -90,7 +90,7 @@ static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
|
||||
object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true,
|
||||
&error_abort);
|
||||
object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abort);
|
||||
object_property_set_bool(OBJECT(&s->cpu), "endianness", true,
|
||||
object_property_set_bool(OBJECT(&s->cpu), "little-endian", true,
|
||||
&error_abort);
|
||||
object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b",
|
||||
&error_abort);
|
||||
@@ -181,9 +181,13 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
|
||||
|
||||
static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
|
||||
{
|
||||
mc->desc = "Xilinx ZynqMP PMU machine";
|
||||
#if TARGET_BIG_ENDIAN
|
||||
mc->desc = "Xilinx ZynqMP PMU machine (big endian)";
|
||||
mc->deprecation_reason = "big endian support is not tested";
|
||||
#else
|
||||
mc->desc = "Xilinx ZynqMP PMU machine (little endian)";
|
||||
#endif
|
||||
mc->init = xlnx_zynqmp_pmu_init;
|
||||
}
|
||||
|
||||
DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
|
||||
|
||||
|
||||
@@ -36,7 +36,6 @@
|
||||
#include "registers.h"
|
||||
#include "qapi/error.h"
|
||||
#include "qemu/log.h"
|
||||
#include "qemu/module.h"
|
||||
|
||||
/* #define HEX_DUMP */
|
||||
/* #define DEBUG_REGISTER */
|
||||
@@ -431,17 +430,14 @@ static void etsec_class_init(ObjectClass *klass, void *data)
|
||||
dc->user_creatable = true;
|
||||
}
|
||||
|
||||
static const TypeInfo etsec_info = {
|
||||
.name = TYPE_ETSEC_COMMON,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(eTSEC),
|
||||
.class_init = etsec_class_init,
|
||||
.instance_init = etsec_instance_init,
|
||||
static const TypeInfo etsec_types[] = {
|
||||
{
|
||||
.name = TYPE_ETSEC_COMMON,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(eTSEC),
|
||||
.class_init = etsec_class_init,
|
||||
.instance_init = etsec_instance_init,
|
||||
},
|
||||
};
|
||||
|
||||
static void etsec_register_types(void)
|
||||
{
|
||||
type_register_static(&etsec_info);
|
||||
}
|
||||
|
||||
type_init(etsec_register_types)
|
||||
DEFINE_TYPES(etsec_types)
|
||||
|
||||
+6
-13
@@ -29,13 +29,6 @@
|
||||
|
||||
/* #define DEBUG_MIIM */
|
||||
|
||||
#define MIIM_CONTROL 0
|
||||
#define MIIM_STATUS 1
|
||||
#define MIIM_PHY_ID_1 2
|
||||
#define MIIM_PHY_ID_2 3
|
||||
#define MIIM_T2_STATUS 10
|
||||
#define MIIM_EXT_STATUS 15
|
||||
|
||||
static void miim_read_cycle(eTSEC *etsec)
|
||||
{
|
||||
uint8_t phy;
|
||||
@@ -47,14 +40,14 @@ static void miim_read_cycle(eTSEC *etsec)
|
||||
addr = etsec->regs[MIIMADD].value & 0x1F;
|
||||
|
||||
switch (addr) {
|
||||
case MIIM_CONTROL:
|
||||
case MII_BMCR:
|
||||
value = etsec->phy_control;
|
||||
break;
|
||||
case MIIM_STATUS:
|
||||
case MII_BMSR:
|
||||
value = etsec->phy_status;
|
||||
break;
|
||||
case MIIM_T2_STATUS:
|
||||
value = 0x1800; /* Local and remote receivers OK */
|
||||
case MII_STAT1000:
|
||||
value = MII_STAT1000_LOK | MII_STAT1000_ROK;
|
||||
break;
|
||||
default:
|
||||
value = 0x0;
|
||||
@@ -84,8 +77,8 @@ static void miim_write_cycle(eTSEC *etsec)
|
||||
#endif
|
||||
|
||||
switch (addr) {
|
||||
case MIIM_CONTROL:
|
||||
etsec->phy_control = value & ~(0x8100);
|
||||
case MII_BMCR:
|
||||
etsec->phy_control = value & ~(MII_BMCR_RESET | MII_BMCR_FD);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
||||
+19
-25
@@ -22,7 +22,6 @@
|
||||
#include "hw/pci/pci_device.h"
|
||||
#include "hw/pci/pci_host.h"
|
||||
#include "qemu/bswap.h"
|
||||
#include "qemu/module.h"
|
||||
#include "hw/pci-host/ppce500.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
@@ -475,7 +474,7 @@ static void e500_pcihost_realize(DeviceState *dev, Error **errp)
|
||||
address_space_init(&s->bm_as, &s->bm, "pci-bm");
|
||||
pci_setup_iommu(b, &ppce500_iommu_ops, s);
|
||||
|
||||
pci_create_simple(b, 0, "e500-host-bridge");
|
||||
pci_create_simple(b, 0, TYPE_PPC_E500_PCI_BRIDGE);
|
||||
|
||||
memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
|
||||
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
|
||||
@@ -508,17 +507,6 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
|
||||
dc->user_creatable = false;
|
||||
}
|
||||
|
||||
static const TypeInfo e500_host_bridge_info = {
|
||||
.name = TYPE_PPC_E500_PCI_BRIDGE,
|
||||
.parent = TYPE_PCI_DEVICE,
|
||||
.instance_size = sizeof(PPCE500PCIBridgeState),
|
||||
.class_init = e500_host_bridge_class_init,
|
||||
.interfaces = (InterfaceInfo[]) {
|
||||
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
||||
{ },
|
||||
},
|
||||
};
|
||||
|
||||
static Property pcihost_properties[] = {
|
||||
DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
|
||||
DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
|
||||
@@ -535,17 +523,23 @@ static void e500_pcihost_class_init(ObjectClass *klass, void *data)
|
||||
dc->vmsd = &vmstate_ppce500_pci;
|
||||
}
|
||||
|
||||
static const TypeInfo e500_pcihost_info = {
|
||||
.name = TYPE_PPC_E500_PCI_HOST_BRIDGE,
|
||||
.parent = TYPE_PCI_HOST_BRIDGE,
|
||||
.instance_size = sizeof(PPCE500PCIState),
|
||||
.class_init = e500_pcihost_class_init,
|
||||
static const TypeInfo e500_pci_types[] = {
|
||||
{
|
||||
.name = TYPE_PPC_E500_PCI_BRIDGE,
|
||||
.parent = TYPE_PCI_DEVICE,
|
||||
.instance_size = sizeof(PPCE500PCIBridgeState),
|
||||
.class_init = e500_host_bridge_class_init,
|
||||
.interfaces = (InterfaceInfo[]) {
|
||||
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
||||
{ },
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = TYPE_PPC_E500_PCI_HOST_BRIDGE,
|
||||
.parent = TYPE_PCI_HOST_BRIDGE,
|
||||
.instance_size = sizeof(PPCE500PCIState),
|
||||
.class_init = e500_pcihost_class_init,
|
||||
},
|
||||
};
|
||||
|
||||
static void e500_pci_register_types(void)
|
||||
{
|
||||
type_register_static(&e500_pcihost_info);
|
||||
type_register_static(&e500_host_bridge_info);
|
||||
}
|
||||
|
||||
type_init(e500_pci_register_types)
|
||||
DEFINE_TYPES(e500_pci_types)
|
||||
|
||||
+6
-4
@@ -203,6 +203,8 @@ static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
|
||||
qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0);
|
||||
qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2);
|
||||
qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic);
|
||||
qemu_fdt_setprop_cell(fdt, i2c, "#size-cells", 0);
|
||||
qemu_fdt_setprop_cell(fdt, i2c, "#address-cells", 1);
|
||||
qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c);
|
||||
|
||||
g_free(i2c);
|
||||
@@ -829,7 +831,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
|
||||
}
|
||||
|
||||
static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
|
||||
IrqLines *irqs, Error **errp)
|
||||
Error **errp)
|
||||
{
|
||||
#ifdef CONFIG_KVM
|
||||
DeviceState *dev;
|
||||
@@ -869,7 +871,7 @@ static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
|
||||
Error *err = NULL;
|
||||
|
||||
if (kvm_kernel_irqchip_allowed()) {
|
||||
dev = ppce500_init_mpic_kvm(pmc, irqs, &err);
|
||||
dev = ppce500_init_mpic_kvm(pmc, &err);
|
||||
}
|
||||
if (kvm_kernel_irqchip_required() && !dev) {
|
||||
error_reportf_err(err,
|
||||
@@ -1021,7 +1023,7 @@ void ppce500_init(MachineState *machine)
|
||||
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
|
||||
memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
|
||||
sysbus_mmio_get_region(s, 0));
|
||||
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
|
||||
i2c = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
|
||||
i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
|
||||
|
||||
/* eSDHC */
|
||||
@@ -1070,7 +1072,7 @@ void ppce500_init(MachineState *machine)
|
||||
memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
|
||||
sysbus_mmio_get_region(s, 0));
|
||||
|
||||
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
||||
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
|
||||
if (!pci_bus)
|
||||
printf("couldn't create PCI controller!\n");
|
||||
|
||||
|
||||
+20
-12
@@ -18,7 +18,6 @@
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qemu/module.h"
|
||||
#include "qemu/log.h"
|
||||
#include "sysemu/runstate.h"
|
||||
#include "cpu.h"
|
||||
@@ -29,6 +28,12 @@
|
||||
#define MPC8544_GUTS_RSTCR_RESET 0x02
|
||||
|
||||
#define MPC8544_GUTS_ADDR_PORPLLSR 0x00
|
||||
REG32(GUTS_PORPLLSR, 0x00)
|
||||
FIELD(GUTS_PORPLLSR, E500_1_RATIO, 24, 6)
|
||||
FIELD(GUTS_PORPLLSR, E500_0_RATIO, 16, 6)
|
||||
FIELD(GUTS_PORPLLSR, DDR_RATIO, 9, 5)
|
||||
FIELD(GUTS_PORPLLSR, PLAT_RATIO, 1, 5)
|
||||
|
||||
#define MPC8544_GUTS_ADDR_PORBMSR 0x04
|
||||
#define MPC8544_GUTS_ADDR_PORIMPSCR 0x08
|
||||
#define MPC8544_GUTS_ADDR_PORDEVSR 0x0C
|
||||
@@ -75,6 +80,12 @@ static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
|
||||
|
||||
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
|
||||
switch (addr) {
|
||||
case MPC8544_GUTS_ADDR_PORPLLSR:
|
||||
value = FIELD_DP32(value, GUTS_PORPLLSR, E500_1_RATIO, 6); /* 3:1 */
|
||||
value = FIELD_DP32(value, GUTS_PORPLLSR, E500_0_RATIO, 6); /* 3:1 */
|
||||
value = FIELD_DP32(value, GUTS_PORPLLSR, DDR_RATIO, 12); /* 12:1 */
|
||||
value = FIELD_DP32(value, GUTS_PORPLLSR, PLAT_RATIO, 6); /* 6:1 */
|
||||
break;
|
||||
case MPC8544_GUTS_ADDR_PVR:
|
||||
value = env->spr[SPR_PVR];
|
||||
break;
|
||||
@@ -129,16 +140,13 @@ static void mpc8544_guts_initfn(Object *obj)
|
||||
sysbus_init_mmio(d, &s->iomem);
|
||||
}
|
||||
|
||||
static const TypeInfo mpc8544_guts_info = {
|
||||
.name = TYPE_MPC8544_GUTS,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(GutsState),
|
||||
.instance_init = mpc8544_guts_initfn,
|
||||
static const TypeInfo mpc8544_guts_types[] = {
|
||||
{
|
||||
.name = TYPE_MPC8544_GUTS,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(GutsState),
|
||||
.instance_init = mpc8544_guts_initfn,
|
||||
},
|
||||
};
|
||||
|
||||
static void mpc8544_guts_register_types(void)
|
||||
{
|
||||
type_register_static(&mpc8544_guts_info);
|
||||
}
|
||||
|
||||
type_init(mpc8544_guts_register_types)
|
||||
DEFINE_TYPES(mpc8544_guts_types)
|
||||
|
||||
+20
-3
@@ -183,8 +183,25 @@ static void riscv_iommu_pri(RISCVIOMMUState *s,
|
||||
}
|
||||
}
|
||||
|
||||
/* Portable implementation of pext_u64, bit-mask extraction. */
|
||||
static uint64_t _pext_u64(uint64_t val, uint64_t ext)
|
||||
/*
|
||||
* Discards all bits from 'val' whose matching bits in the same
|
||||
* positions in the mask 'ext' are zeros, and packs the remaining
|
||||
* bits from 'val' contiguously at the least-significant end of the
|
||||
* result, keeping the same bit order as 'val' and filling any
|
||||
* other bits at the most-significant end of the result with zeros.
|
||||
*
|
||||
* For example, for the following 'val' and 'ext', the return 'ret'
|
||||
* will be:
|
||||
*
|
||||
* val = a b c d e f g h
|
||||
* ext = 1 0 1 0 0 1 1 0
|
||||
* ret = 0 0 0 0 a c f g
|
||||
*
|
||||
* This function, taken from the riscv-iommu 1.0 spec, section 2.3.3
|
||||
* "Process to translate addresses of MSIs", is similar to bit manip
|
||||
* function PEXT (Parallel bits extract) from x86.
|
||||
*/
|
||||
static uint64_t riscv_iommu_pext_u64(uint64_t val, uint64_t ext)
|
||||
{
|
||||
uint64_t ret = 0;
|
||||
uint64_t rot = 1;
|
||||
@@ -528,7 +545,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState *s,
|
||||
int cause;
|
||||
|
||||
/* Interrupt File Number */
|
||||
intn = _pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask);
|
||||
intn = riscv_iommu_pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask);
|
||||
if (intn >= 256) {
|
||||
/* Interrupt file number out of range */
|
||||
res = MEMTX_ACCESS_ERROR;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user