izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220121-1' into staging

Browse Source 
Third RISC-V PR for QEMU 7.0

 * Fixes for OpenTitan timer
 * Correction of OpenTitan PLIC stride length
 * RISC-V KVM support
 * Device tree code cleanup
 * Support for the Zve64f and Zve32f extensions
 * OpenSBI binary loading support for the Spike machine
 * Removal of OpenSBI ELFs
 * Support for the UXL field in xstatus

# gpg: Signature made Fri 21 Jan 2022 05:57:09 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20220121-1: (61 commits)
  target/riscv: Relax UXL field for debugging
  target/riscv: Enable uxl field write
  target/riscv: Set default XLEN for hypervisor
  target/riscv: Adjust scalar reg in vector with XLEN
  target/riscv: Adjust vector address with mask
  target/riscv: Fix check range for first fault only
  target/riscv: Remove VILL field in VTYPE
  target/riscv: Adjust vsetvl according to XLEN
  target/riscv: Split out the vill from vtype
  target/riscv: Split pm_enabled into mask and base
  target/riscv: Calculate address according to XLEN
  target/riscv: Alloc tcg global for cur_pm[mask|base]
  target/riscv: Create current pm fields in env
  target/riscv: Adjust csr write mask with XLEN
  target/riscv: Relax debug check for pm write
  target/riscv: Use gdb xml according to max mxlen
  target/riscv: Extend pc for runtime pc write
  target/riscv: Ignore the pc bits above XLEN
  target/riscv: Create xl field in env
  target/riscv: Sign extend pc for different XLEN
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2022-01-21 10:31:25 +00:00
parent 2c89b5af5e f297245f6a
commit 5e9d14f2be
42 changed files with 1609 additions and 357 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.gitlab-ci.d/opensbi.yml
-2
View File
@@ -43,9 +43,7 @@ build-opensbi:
artifacts:
paths: # 'artifacts.zip' will contains the following files:
- pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
- pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
- pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
- pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
- opensbi32-generic-stdout.log
- opensbi32-generic-stderr.log
- opensbi64-generic-stdout.log
hw/char/riscv_htif.c
+23 -12
View File
@@ -228,13 +228,25 @@ static const MemoryRegionOps htif_mm_ops = {
.write = htif_mm_write,
};
HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
CPURISCVState *env, Chardev *chr)
bool htif_uses_elf_symbols(void)
{
uint64_t base = MIN(tohost_addr, fromhost_addr);
uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
uint64_t tohost_offset = tohost_addr - base;
uint64_t fromhost_offset = fromhost_addr - base;
return (address_symbol_set == 3) ? true : false;
}
HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
{
uint64_t base, size, tohost_offset, fromhost_offset;
if (!htif_uses_elf_symbols()) {
fromhost_addr = nonelf_base;
tohost_addr = nonelf_base + 8;
}
base = MIN(tohost_addr, fromhost_addr);
size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
tohost_offset = tohost_addr - base;
fromhost_offset = fromhost_addr - base;
HTIFState *s = g_malloc0(sizeof(HTIFState));
s->address_space = address_space;
@@ -249,12 +261,11 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
qemu_chr_fe_init(&s->chr, chr, &error_abort);
qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
htif_be_change, s, NULL, true);
if (address_symbol_set == 3) {
memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
TYPE_HTIF_UART, size);
memory_region_add_subregion_overlap(address_space, base,
&s->mmio, 1);
}
memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
TYPE_HTIF_UART, size);
memory_region_add_subregion_overlap(address_space, base,
&s->mmio, 1);
return s;
}
hw/intc/sifive_plic.c
+15 -5
View File
@@ -30,6 +30,7 @@
#include "target/riscv/cpu.h"
#include "migration/vmstate.h"
#include "hw/irq.h"
#include "sysemu/kvm.h"
static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
{
@@ -430,7 +431,8 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
uint32_t context_stride, uint32_t aperture_size)
{
DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
int i;
int i, j = 0;
SiFivePLICState *plic;
assert(enable_stride == (enable_stride & -enable_stride));
assert(context_stride == (context_stride & -context_stride));
@@ -448,13 +450,21 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
plic = SIFIVE_PLIC(dev);
for (i = 0; i < num_harts; i++) {
CPUState *cpu = qemu_get_cpu(hartid_base + i);
qdev_connect_gpio_out(dev, i,
qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
qdev_connect_gpio_out(dev, num_harts + i,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
if (plic->addr_config[j].mode == PLICMode_M) {
j++;
qdev_connect_gpio_out(dev, num_harts + i,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[j].mode == PLICMode_S) {
j++;
qdev_connect_gpio_out(dev, i,
qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
}
}
return dev;
hw/riscv/boot.c
+15 -1
View File
@@ -30,6 +30,7 @@
#include "elf.h"
#include "sysemu/device_tree.h"
#include "sysemu/qtest.h"
#include "sysemu/kvm.h"
#include <libfdt.h>
@@ -51,7 +52,9 @@ char *riscv_plic_hart_config_string(int hart_count)
CPUState *cs = qemu_get_cpu(i);
CPURISCVState *env = &RISCV_CPU(cs)->env;
if (riscv_has_ext(env, RVS)) {
if (kvm_enabled()) {
vals[i] = "S";
} else if (riscv_has_ext(env, RVS)) {
vals[i] = "MS";
} else {
vals[i] = "M";
@@ -324,3 +327,14 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
return;
}
void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
{
CPUState *cs;
for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
RISCVCPU *riscv_cpu = RISCV_CPU(cs);
riscv_cpu->env.kernel_addr = kernel_addr;
riscv_cpu->env.fdt_addr = fdt_addr;
}
}
hw/riscv/opentitan.c
+1 -1
View File
@@ -160,7 +160,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
hw/riscv/spike.c
+27 -18
View File
@@ -42,6 +42,7 @@
static const MemMapEntry spike_memmap[] = {
[SPIKE_MROM] = { 0x1000, 0xf000 },
[SPIKE_HTIF] = { 0x1000000, 0x1000 },
[SPIKE_CLINT] = { 0x2000000, 0x10000 },
[SPIKE_DRAM] = { 0x80000000, 0x0 },
};
@@ -75,6 +76,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/htif");
qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
if (!htif_uses_elf_symbols()) {
qemu_fdt_setprop_cells(fdt, "/htif", "reg",
0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
}
qemu_fdt_add_subnode(fdt, "/soc");
qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
@@ -172,6 +177,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
if (cmdline) {
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
}
}
@@ -241,10 +247,6 @@ static void spike_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
machine->ram);
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(&s->soc[0]));
/* boot rom */
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
memmap[SPIKE_MROM].size, &error_fatal);
@@ -258,14 +260,15 @@ static void spike_board_init(MachineState *machine)
*/
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
}
/* Load kernel */
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
@@ -273,17 +276,6 @@ static void spike_board_init(MachineState *machine)
kernel_entry = riscv_load_kernel(machine->kernel_filename,
kernel_start_addr,
htif_symbol_callback);
if (machine->initrd_filename) {
hwaddr start;
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
qemu_fdt_setprop_cell(s->fdt, "/chosen",
"linux,initrd-start", start);
qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
end);
}
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
@@ -292,6 +284,22 @@ static void spike_board_init(MachineState *machine)
kernel_entry = 0;
}
/* Create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(&s->soc[0]));
/* Load initrd */
if (machine->kernel_filename && machine->initrd_filename) {
hwaddr start;
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
qemu_fdt_setprop_cell(s->fdt, "/chosen",
"linux,initrd-start", start);
qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
end);
}
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
machine->ram_size, s->fdt);
@@ -303,7 +311,8 @@ static void spike_board_init(MachineState *machine)
/* initialize HTIF using symbols found in load_kernel */
htif_mm_init(system_memory, mask_rom,
&s->soc[0].harts[0].env, serial_hd(0));
&s->soc[0].harts[0].env, serial_hd(0),
memmap[SPIKE_HTIF].base);
}
static void spike_machine_instance_init(Object *obj)
hw/riscv/virt.c
+58 -25
View File
@@ -38,6 +38,7 @@
#include "chardev/char.h"
#include "sysemu/device_tree.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "hw/pci/pci.h"
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
@@ -372,13 +373,22 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
"sifive,plic-1.0.0", "riscv,plic0"
};
plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
if (kvm_enabled()) {
plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
} else {
plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
}
for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
if (kvm_enabled()) {
plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
} else {
plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
}
}
plic_phandles[socket] = (*phandle)++;
@@ -436,10 +446,12 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
create_fdt_socket_memory(s, memmap, socket);
if (s->have_aclint) {
create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
} else {
create_fdt_socket_clint(s, memmap, socket, intc_phandles);
if (!kvm_enabled()) {
if (s->have_aclint) {
create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
} else {
create_fdt_socket_clint(s, memmap, socket, intc_phandles);
}
}
create_fdt_socket_plic(s, memmap, socket, phandle,
@@ -801,23 +813,25 @@ static void virt_machine_init(MachineState *machine)
hart_count, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
/* Per-socket CLINT */
riscv_aclint_swi_create(
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
base_hartid, hart_count, false);
riscv_aclint_mtimer_create(
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
/* Per-socket ACLINT SSWI */
if (s->have_aclint) {
if (!kvm_enabled()) {
/* Per-socket CLINT */
riscv_aclint_swi_create(
memmap[VIRT_ACLINT_SSWI].base +
i * memmap[VIRT_ACLINT_SSWI].size,
base_hartid, hart_count, true);
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
base_hartid, hart_count, false);
riscv_aclint_mtimer_create(
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
/* Per-socket ACLINT SSWI */
if (s->have_aclint) {
riscv_aclint_swi_create(
memmap[VIRT_ACLINT_SSWI].base +
i * memmap[VIRT_ACLINT_SSWI].size,
base_hartid, hart_count, true);
}
}
/* Per-socket PLIC hart topology configuration string */
@@ -884,6 +898,16 @@ static void virt_machine_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
mask_rom);
/*
* Only direct boot kernel is currently supported for KVM VM,
* so the "-bios" parameter is ignored and treated like "-bios none"
* when KVM is enabled.
*/
if (kvm_enabled()) {
g_free(machine->firmware);
machine->firmware = g_strdup("none");
}
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV32_BIOS_BIN, start_addr, NULL);
@@ -941,6 +965,15 @@ static void virt_machine_init(MachineState *machine)
virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, machine->fdt);
/*
* Only direct boot kernel is currently supported for KVM VM,
* So here setup kernel start address and fdt address.
* TODO:Support firmware loading and integrate to TCG start
*/
if (kvm_enabled()) {
riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
}
/* SiFive Test MMIO device */
sifive_test_create(memmap[VIRT_TEST].base);
hw/timer/ibex_timer.c
+15 -10
View File
@@ -34,7 +34,9 @@
#include "target/riscv/cpu.h"
#include "migration/vmstate.h"
REG32(CTRL, 0x00)
REG32(ALERT_TEST, 0x00)
FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
REG32(CTRL, 0x04)
FIELD(CTRL, ACTIVE, 0, 1)
REG32(CFG0, 0x100)
FIELD(CFG0, PRESCALE, 0, 12)
@@ -130,7 +132,6 @@ static void ibex_timer_reset(DeviceState *dev)
s->timer_compare_upper0 = 0xFFFFFFFF;
s->timer_intr_enable = 0x00000000;
s->timer_intr_state = 0x00000000;
s->timer_intr_test = 0x00000000;
ibex_timer_update_irqs(s);
}
@@ -143,6 +144,10 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
uint64_t retvalue = 0;
switch (addr >> 2) {
case R_ALERT_TEST:
qemu_log_mask(LOG_GUEST_ERROR,
"Attempted to read ALERT_TEST, a write only register");
break;
case R_CTRL:
retvalue = s->timer_ctrl;
break;
@@ -168,7 +173,8 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
retvalue = s->timer_intr_state;
break;
case R_INTR_TEST:
retvalue = s->timer_intr_test;
qemu_log_mask(LOG_GUEST_ERROR,
"Attempted to read INTR_TEST, a write only register");
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
@@ -186,6 +192,9 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
uint32_t val = val64;
switch (addr >> 2) {
case R_ALERT_TEST:
qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
break;
case R_CTRL:
s->timer_ctrl = val;
break;
@@ -215,10 +224,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
s->timer_intr_state &= ~val;
break;
case R_INTR_TEST:
s->timer_intr_test = val;
if (s->timer_intr_enable &
s->timer_intr_test &
R_INTR_ENABLE_IE_0_MASK) {
if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true);
}
@@ -247,8 +253,8 @@ static int ibex_timer_post_load(void *opaque, int version_id)
static const VMStateDescription vmstate_ibex_timer = {
.name = TYPE_IBEX_TIMER,
.version_id = 1,
.minimum_version_id = 1,
.version_id = 2,
.minimum_version_id = 2,
.post_load = ibex_timer_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(timer_ctrl, IbexTimerState),
@@ -257,7 +263,6 @@ static const VMStateDescription vmstate_ibex_timer = {
VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
VMSTATE_UINT32(timer_intr_state, IbexTimerState),
VMSTATE_UINT32(timer_intr_test, IbexTimerState),
VMSTATE_END_OF_LIST()
}
};
include/hw/char/riscv_htif.h
+4 -1
View File
@@ -52,8 +52,11 @@ extern const MemoryRegionOps htif_io_ops;
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size);
/* Check if HTIF uses ELF symbols */
bool htif_uses_elf_symbols(void);
/* legacy pre qom */
HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
CPURISCVState *env, Chardev *chr);
CPURISCVState *env, Chardev *chr, uint64_t nonelf_base);
#endif
include/hw/riscv/boot.h
+1 -2
View File
@@ -25,9 +25,7 @@
#include "hw/riscv/riscv_hart.h"
#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
#define RISCV32_BIOS_ELF "opensbi-riscv32-generic-fw_dynamic.elf"
#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
#define RISCV64_BIOS_ELF "opensbi-riscv64-generic-fw_dynamic.elf"
bool riscv_is_32bit(RISCVHartArrayState *harts);
@@ -58,5 +56,6 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
hwaddr rom_size,
uint32_t reset_vec_size,
uint64_t kernel_entry);
void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
#endif /* RISCV_BOOT_H */
include/hw/riscv/spike.h
+1
View File
@@ -43,6 +43,7 @@ struct SpikeState {
enum {
SPIKE_MROM,
SPIKE_HTIF,
SPIKE_CLINT,
SPIKE_DRAM
};
include/hw/timer/ibex_timer.h
-1
View File
@@ -43,7 +43,6 @@ struct IbexTimerState {
uint32_t timer_compare_upper0;
uint32_t timer_intr_enable;
uint32_t timer_intr_state;
uint32_t timer_intr_test;
uint32_t timebase_freq;
linux-headers/asm-riscv/kvm.h
+128
View File
@@ -0,0 +1,128 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright (C) 2019 Western Digital Corporation or its affiliates.
*
* Authors:
* Anup Patel <anup.patel@wdc.com>
*/
#ifndef __LINUX_KVM_RISCV_H
#define __LINUX_KVM_RISCV_H
#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <asm/ptrace.h>
#define __KVM_HAVE_READONLY_MEM
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
#define KVM_INTERRUPT_SET -1U
#define KVM_INTERRUPT_UNSET -2U
/* for KVM_GET_REGS and KVM_SET_REGS */
struct kvm_regs {
};
/* for KVM_GET_FPU and KVM_SET_FPU */
struct kvm_fpu {
};
/* KVM Debug exit structure */
struct kvm_debug_exit_arch {
};
/* for KVM_SET_GUEST_DEBUG */
struct kvm_guest_debug_arch {
};
/* definition of registers in kvm_run */
struct kvm_sync_regs {
};
/* for KVM_GET_SREGS and KVM_SET_SREGS */
struct kvm_sregs {
};
/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_config {
unsigned long isa;
};
/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_core {
struct user_regs_struct regs;
unsigned long mode;
};
/* Possible privilege modes for kvm_riscv_core */
#define KVM_RISCV_MODE_S 1
#define KVM_RISCV_MODE_U 0
/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_csr {
unsigned long sstatus;
unsigned long sie;
unsigned long stvec;
unsigned long sscratch;
unsigned long sepc;
unsigned long scause;
unsigned long stval;
unsigned long sip;
unsigned long satp;
unsigned long scounteren;
};
/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_timer {
__u64 frequency;
__u64 time;
__u64 compare;
__u64 state;
};
/* Possible states for kvm_riscv_timer */
#define KVM_RISCV_TIMER_STATE_OFF 0
#define KVM_RISCV_TIMER_STATE_ON 1
#define KVM_REG_SIZE(id) \
(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
/* If you need to interpret the index values, here is the key: */
#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
#define KVM_REG_RISCV_TYPE_SHIFT 24
/* Config registers are mapped as type 1 */
#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_CONFIG_REG(name) \
(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
/* Core registers are mapped as type 2 */
#define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_CORE_REG(name) \
(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
/* Control and status registers are mapped as type 3 */
#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_CSR_REG(name) \
(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
/* Timer registers are mapped as type 4 */
#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_TIMER_REG(name) \
(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
/* F extension registers are mapped as type 5 */
#define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_FP_F_REG(name) \
(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
/* D extension registers are mapped as type 6 */
#define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_FP_D_REG(name) \
(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
#endif
#endif /* __LINUX_KVM_RISCV_H */
meson.build
+2
View File
@@ -90,6 +90,8 @@ elif cpu in ['ppc', 'ppc64']
kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
elif cpu in ['mips', 'mips64']
kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
elif cpu in ['riscv']
kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
else
kvm_targets = []
endif
pc-bios/meson.build
-2
View File
@@ -80,8 +80,6 @@ blobs = files(
'hppa-firmware.img',
'opensbi-riscv32-generic-fw_dynamic.bin',
'opensbi-riscv64-generic-fw_dynamic.bin',
'opensbi-riscv32-generic-fw_dynamic.elf',
'opensbi-riscv64-generic-fw_dynamic.elf',
'npcm7xx_bootrom.bin',
)
pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
BIN
View File
Binary file not shown.
pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
BIN
View File
Binary file not shown.
roms/Makefile
-2
View File
@@ -178,14 +178,12 @@ opensbi32-generic:
CROSS_COMPILE=$(riscv32_cross_prefix) \
PLATFORM="generic"
cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
opensbi64-generic:
$(MAKE) -C opensbi \
CROSS_COMPILE=$(riscv64_cross_prefix) \
PLATFORM="generic"
cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
MESON = meson
NINJA = ninja
softmmu/device_tree.c
+5 -6
View File
@@ -558,7 +558,6 @@ int qemu_fdt_add_subnode(void *fdt, const char *name)
int qemu_fdt_add_path(void *fdt, const char *path)
{
const char *name;
const char *p = path;
int namelen, retval;
int parent = 0;
@@ -566,10 +565,10 @@ int qemu_fdt_add_path(void *fdt, const char *path)
return -1;
}
while (p) {
name = p + 1;
p = strchr(name, '/');
namelen = p != NULL ? p - name : strlen(name);
do {
name = path + 1;
path = strchr(name, '/');
namelen = path != NULL ? path - name : strlen(name);
retval = fdt_subnode_offset_namelen(fdt, parent, name, namelen);
if (retval < 0 && retval != -FDT_ERR_NOTFOUND) {
@@ -586,7 +585,7 @@ int qemu_fdt_add_path(void *fdt, const char *path)
}
parent = retval;
}
} while (path);
return retval;
}
target/riscv/cpu.c
+68 -9
View File
@@ -29,6 +29,8 @@
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "fpu/softfloat-helpers.h"
#include "sysemu/kvm.h"
#include "kvm_riscv.h"
/* RISC-V CPU definitions */
@@ -233,6 +235,18 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
}
#endif
#if defined(CONFIG_KVM)
static void riscv_host_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
#if defined(TARGET_RISCV32)
set_misa(env, MXL_RV32, 0);
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, 0);
#endif
}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
@@ -341,7 +355,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->pc = value;
if (env->xl == MXL_RV32) {
env->pc = (int32_t)value;
} else {
env->pc = value;
}
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
@@ -349,7 +368,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->pc = tb->pc;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
if (xl == MXL_RV32) {
env->pc = (int32_t)tb->pc;
} else {
env->pc = tb->pc;
}
}
static bool riscv_cpu_has_work(CPUState *cs)
@@ -370,7 +395,12 @@ static bool riscv_cpu_has_work(CPUState *cs)
void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
target_ulong *data)
{
env->pc = data[0];
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
if (xl == MXL_RV32) {
env->pc = (int32_t)data[0];
} else {
env->pc = data[0];
}
}
static void riscv_cpu_reset(DeviceState *dev)
@@ -392,6 +422,16 @@ static void riscv_cpu_reset(DeviceState *dev)
*/
env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
if (riscv_has_ext(env, RVH)) {
env->vsstatus = set_field(env->vsstatus,
MSTATUS64_SXL, env->misa_mxl);
env->vsstatus = set_field(env->vsstatus,
MSTATUS64_UXL, env->misa_mxl);
env->mstatus_hs = set_field(env->mstatus_hs,
MSTATUS64_SXL, env->misa_mxl);
env->mstatus_hs = set_field(env->mstatus_hs,
MSTATUS64_UXL, env->misa_mxl);
}
}
env->mcause = 0;
env->pc = env->resetvec;
@@ -399,9 +439,17 @@ static void riscv_cpu_reset(DeviceState *dev)
/* mmte is supposed to have pm.current hardwired to 1 */
env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
#endif
env->xl = riscv_cpu_mxl(env);
riscv_cpu_update_mask(env);
cs->exception_index = RISCV_EXCP_NONE;
env->load_res = -1;
set_default_nan_mode(1, &env->fp_status);
#ifndef CONFIG_USER_ONLY
if (kvm_enabled()) {
kvm_riscv_reset_vcpu(cpu);
}
#endif
}
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
@@ -429,6 +477,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
RISCVCPU *cpu = RISCV_CPU(dev);
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
CPUClass *cc = CPU_CLASS(mcc);
int priv_version = 0;
Error *local_err = NULL;
@@ -479,11 +528,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
switch (env->misa_mxl_max) {
#ifdef TARGET_RISCV64
case MXL_RV64:
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
break;
case MXL_RV128:
break;
#endif
case MXL_RV32:
cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
break;
default:
g_assert_not_reached();
@@ -589,6 +640,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
set_vext_version(env, vext_version);
}
if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
return;
}
if (cpu->cfg.ext_j) {
ext |= RVJ;
}
@@ -622,7 +677,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
case IRQ_S_EXT:
case IRQ_VS_EXT:
case IRQ_M_EXT:
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
if (kvm_enabled()) {
kvm_riscv_set_irq(cpu, irq, level);
} else {
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
}
break;
default:
g_assert_not_reached();
@@ -660,6 +719,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
@@ -755,11 +816,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
cc->gdb_num_core_regs = 33;
#if defined(TARGET_RISCV32)
cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
#elif defined(TARGET_RISCV64)
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
#endif
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
@@ -835,6 +891,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_init = riscv_cpu_class_init,
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(CONFIG_KVM)
DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
#endif
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),

Some files were not shown because too many files have changed in this diff Show More