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Merge tag 'pull-target-arm-20250515' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

Browse Source 
target-arm queue:
 * target/arm: refactoring for compile-twice changes
 * MAINTAINERS: Add an entry for the Bananapi machine
 * arm/omap: remove hard coded tabs
 * rust: pl011: Cut down amount of text quoted from PL011 TRM
 * target/arm: refactor Arm CPU class hierarchy

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# gpg: Signature made Thu 15 May 2025 06:23:01 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250515' of https://git.linaro.org/people/pmaydell/qemu-arm: (58 commits)
  target/arm/tcg/vfp_helper: compile file twice (system, user)
  target/arm/tcg/arith_helper: compile file once
  target/arm/tcg/tlb-insns: compile file once (system)
  target/arm/helper: restrict define_tlb_insn_regs to system target
  target/arm/tcg/tlb_helper: compile file twice (system, user)
  target/arm/tcg/neon_helper: compile file twice (system, user)
  target/arm/tcg/iwmmxt_helper: compile file twice (system, user)
  target/arm/tcg/hflags: compile file twice (system, user)
  target/arm/tcg/crypto_helper: compile file once
  target/arm/tcg/vec_internal: use forward declaration for CPUARMState
  target/arm/machine: compile file once (system)
  target/arm/kvm-stub: add missing stubs
  target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function
  target/arm/machine: remove TARGET_AARCH64 from migration state
  target/arm/machine: reduce migration include to avoid target specific definitions
  target/arm/kvm-stub: compile file once (system)
  target/arm/meson: accelerator files are not needed in user mode
  target/arm/ptw: compile file once (system)
  target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw
  target/arm/ptw: replace target_ulong with int64_t
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
2025-05-15 13:42:21 -04:00
parent 599f2762ed 9eb5427ac0
commit 5cb8b0988b
53 changed files with 3033 additions and 3100 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+10
View File
@@ -732,6 +732,16 @@ F: include/hw/timer/armv7m_systick.h
F: include/hw/misc/armv7m_ras.h
F: tests/qtest/test-arm-mptimer.c
Bananapi M2U
M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
S: Odd Fixes
F: docs/system/arm/bananapi_m2u.rst
F: hw/*/allwinner-r40*.c
F: hw/arm/bananapi_m2u.c
F: include/hw/*/allwinner-r40*.h
F: tests/functional/test_arm_bpim2u.py
B-L475E-IOT01A IoT Node
M: Samuel Tardieu <sam@rfc1149.net>
L: qemu-arm@nongnu.org
hw/arm/omap1.c
+508 -508
View File
File diff suppressed because it is too large Load Diff
hw/arm/omap_sx1.c
+1 -1
View File
@@ -1,7 +1,7 @@
/* omap_sx1.c Support for the Siemens SX1 smartphone emulation.
*
* Copyright (C) 2008
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com>
*
* based on PalmOne's (TM) PDAs support (palm.c)
hw/core/cpu-common.c
+2 -1
View File
@@ -234,6 +234,8 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
return false;
}
gdb_init_cpu(cpu);
/* Wait until cpu initialization complete before exposing cpu. */
cpu_list_add(cpu);
@@ -304,7 +306,6 @@ static void cpu_common_initfn(Object *obj)
/* cache the cpu class for the hotpath */
cpu->cc = CPU_GET_CLASS(cpu);
gdb_init_cpu(cpu);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
cpu->as = NULL;
hw/dma/omap_dma.c
+167 -167
View File
File diff suppressed because it is too large Load Diff
hw/gpio/omap_gpio.c
+14 -14
View File
@@ -80,25 +80,25 @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
}
switch (offset) {
case 0x00: /* DATA_INPUT */
case 0x00: /* DATA_INPUT */
return s->inputs & s->pins;
case 0x04: /* DATA_OUTPUT */
case 0x04: /* DATA_OUTPUT */
return s->outputs;
case 0x08: /* DIRECTION_CONTROL */
case 0x08: /* DIRECTION_CONTROL */
return s->dir;
case 0x0c: /* INTERRUPT_CONTROL */
case 0x0c: /* INTERRUPT_CONTROL */
return s->edge;
case 0x10: /* INTERRUPT_MASK */
case 0x10: /* INTERRUPT_MASK */
return s->mask;
case 0x14: /* INTERRUPT_STATUS */
case 0x14: /* INTERRUPT_STATUS */
return s->ints;
case 0x18: /* PIN_CONTROL (not in OMAP310) */
case 0x18: /* PIN_CONTROL (not in OMAP310) */
OMAP_BAD_REG(addr);
return s->pins;
}
@@ -121,11 +121,11 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
}
switch (offset) {
case 0x00: /* DATA_INPUT */
case 0x00: /* DATA_INPUT */
OMAP_RO_REG(addr);
return;
case 0x04: /* DATA_OUTPUT */
case 0x04: /* DATA_OUTPUT */
diff = (s->outputs ^ value) & ~s->dir;
s->outputs = value;
while ((ln = ctz32(diff)) != 32) {
@@ -135,7 +135,7 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
}
break;
case 0x08: /* DIRECTION_CONTROL */
case 0x08: /* DIRECTION_CONTROL */
diff = s->outputs & (s->dir ^ value);
s->dir = value;
@@ -147,21 +147,21 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
}
break;
case 0x0c: /* INTERRUPT_CONTROL */
case 0x0c: /* INTERRUPT_CONTROL */
s->edge = value;
break;
case 0x10: /* INTERRUPT_MASK */
case 0x10: /* INTERRUPT_MASK */
s->mask = value;
break;
case 0x14: /* INTERRUPT_STATUS */
case 0x14: /* INTERRUPT_STATUS */
s->ints &= ~value;
if (!s->ints)
qemu_irq_lower(s->irq);
break;
case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
OMAP_BAD_REG(addr);
s->pins = value;
break;
hw/i2c/omap_i2c.c
+89 -89
View File
@@ -55,16 +55,16 @@ struct OMAPI2CState {
uint16_t test;
};
#define OMAP2_INTR_REV 0x34
#define OMAP2_GC_REV 0x34
#define OMAP2_INTR_REV 0x34
#define OMAP2_GC_REV 0x34
static void omap_i2c_interrupts_update(OMAPI2CState *s)
{
qemu_set_irq(s->irq, s->stat & s->mask);
if ((s->dma >> 15) & 1) /* RDMA_EN */
qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
if ((s->dma >> 7) & 1) /* XDMA_EN */
qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
if ((s->dma >> 15) & 1) /* RDMA_EN */
qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
if ((s->dma >> 7) & 1) /* XDMA_EN */
qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
}
static void omap_i2c_fifo_run(OMAPI2CState *s)
@@ -74,25 +74,25 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
if (!i2c_bus_busy(s->bus))
return;
if ((s->control >> 2) & 1) { /* RM */
if ((s->control >> 1) & 1) { /* STP */
if ((s->control >> 2) & 1) { /* RM */
if ((s->control >> 1) & 1) { /* STP */
i2c_end_transfer(s->bus);
s->control &= ~(1 << 1); /* STP */
s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count;
s->txlen = 0;
} else if ((s->control >> 9) & 1) { /* TRX */
} else if ((s->control >> 9) & 1) { /* TRX */
while (ack && s->txlen)
ack = (i2c_send(s->bus,
(s->fifo >> ((-- s->txlen) << 3)) &
0xff) >= 0);
s->stat |= 1 << 4; /* XRDY */
s->stat |= 1 << 4; /* XRDY */
} else {
while (s->rxlen < 4)
s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
s->stat |= 1 << 3; /* RRDY */
s->stat |= 1 << 3; /* RRDY */
}
} else {
if ((s->control >> 9) & 1) { /* TRX */
if ((s->control >> 9) & 1) { /* TRX */
while (ack && s->count_cur && s->txlen) {
ack = (i2c_send(s->bus,
(s->fifo >> ((-- s->txlen) << 3)) &
@@ -100,12 +100,12 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
s->count_cur --;
}
if (ack && s->count_cur)
s->stat |= 1 << 4; /* XRDY */
s->stat |= 1 << 4; /* XRDY */
else
s->stat &= ~(1 << 4); /* XRDY */
s->stat &= ~(1 << 4); /* XRDY */
if (!s->count_cur) {
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
}
} else {
while (s->count_cur && s->rxlen < 4) {
@@ -113,26 +113,26 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
s->count_cur --;
}
if (s->rxlen)
s->stat |= 1 << 3; /* RRDY */
s->stat |= 1 << 3; /* RRDY */
else
s->stat &= ~(1 << 3); /* RRDY */
s->stat &= ~(1 << 3); /* RRDY */
}
if (!s->count_cur) {
if ((s->control >> 1) & 1) { /* STP */
if ((s->control >> 1) & 1) { /* STP */
i2c_end_transfer(s->bus);
s->control &= ~(1 << 1); /* STP */
s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count;
s->txlen = 0;
} else {
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
}
}
}
s->stat |= (!ack) << 1; /* NACK */
s->stat |= (!ack) << 1; /* NACK */
if (!ack)
s->control &= ~(1 << 1); /* STP */
s->control &= ~(1 << 1); /* STP */
}
static void omap_i2c_reset(DeviceState *dev)
@@ -163,16 +163,16 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
uint16_t ret;
switch (offset) {
case 0x00: /* I2C_REV */
return s->revision; /* REV */
case 0x00: /* I2C_REV */
return s->revision; /* REV */
case 0x04: /* I2C_IE */
case 0x04: /* I2C_IE */
return s->mask;
case 0x08: /* I2C_STAT */
case 0x08: /* I2C_STAT */
return s->stat | (i2c_bus_busy(s->bus) << 12);
case 0x0c: /* I2C_IV */
case 0x0c: /* I2C_IV */
if (s->revision >= OMAP2_INTR_REV)
break;
ret = ctz32(s->stat & s->mask);
@@ -185,18 +185,18 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
omap_i2c_interrupts_update(s);
return ret;
case 0x10: /* I2C_SYSS */
return (s->control >> 15) & 1; /* I2C_EN */
case 0x10: /* I2C_SYSS */
return (s->control >> 15) & 1; /* I2C_EN */
case 0x14: /* I2C_BUF */
case 0x14: /* I2C_BUF */
return s->dma;
case 0x18: /* I2C_CNT */
return s->count_cur; /* DCOUNT */
case 0x18: /* I2C_CNT */
return s->count_cur; /* DCOUNT */
case 0x1c: /* I2C_DATA */
case 0x1c: /* I2C_DATA */
ret = 0;
if (s->control & (1 << 14)) { /* BE */
if (s->control & (1 << 14)) { /* BE */
ret |= ((s->fifo >> 0) & 0xff) << 8;
ret |= ((s->fifo >> 8) & 0xff) << 0;
} else {
@@ -204,7 +204,7 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
ret |= ((s->fifo >> 0) & 0xff) << 0;
}
if (s->rxlen == 1) {
s->stat |= 1 << 15; /* SBD */
s->stat |= 1 << 15; /* SBD */
s->rxlen = 0;
} else if (s->rxlen > 1) {
if (s->rxlen > 2)
@@ -214,41 +214,41 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
/* XXX: remote access (qualifier) error - what's that? */
}
if (!s->rxlen) {
s->stat &= ~(1 << 3); /* RRDY */
if (((s->control >> 10) & 1) && /* MST */
((~s->control >> 9) & 1)) { /* TRX */
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
s->stat &= ~(1 << 3); /* RRDY */
if (((s->control >> 10) & 1) && /* MST */
((~s->control >> 9) & 1)) { /* TRX */
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
}
}
s->stat &= ~(1 << 11); /* ROVR */
s->stat &= ~(1 << 11); /* ROVR */
omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s);
return ret;
case 0x20: /* I2C_SYSC */
case 0x20: /* I2C_SYSC */
return 0;
case 0x24: /* I2C_CON */
case 0x24: /* I2C_CON */
return s->control;
case 0x28: /* I2C_OA */
case 0x28: /* I2C_OA */
return s->addr[0];
case 0x2c: /* I2C_SA */
case 0x2c: /* I2C_SA */
return s->addr[1];
case 0x30: /* I2C_PSC */
case 0x30: /* I2C_PSC */
return s->divider;
case 0x34: /* I2C_SCLL */
case 0x34: /* I2C_SCLL */
return s->times[0];
case 0x38: /* I2C_SCLH */
case 0x38: /* I2C_SCLH */
return s->times[1];
case 0x3c: /* I2C_SYSTEST */
if (s->test & (1 << 15)) { /* ST_EN */
case 0x3c: /* I2C_SYSTEST */
if (s->test & (1 << 15)) { /* ST_EN */
s->test ^= 0xa;
return s->test;
} else
@@ -267,17 +267,17 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
int nack;
switch (offset) {
case 0x00: /* I2C_REV */
case 0x0c: /* I2C_IV */
case 0x10: /* I2C_SYSS */
case 0x00: /* I2C_REV */
case 0x0c: /* I2C_IV */
case 0x10: /* I2C_SYSS */
OMAP_RO_REG(addr);
return;
case 0x04: /* I2C_IE */
case 0x04: /* I2C_IE */
s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
break;
case 0x08: /* I2C_STAT */
case 0x08: /* I2C_STAT */
if (s->revision < OMAP2_INTR_REV) {
OMAP_RO_REG(addr);
return;
@@ -288,40 +288,40 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
omap_i2c_interrupts_update(s);
break;
case 0x14: /* I2C_BUF */
case 0x14: /* I2C_BUF */
s->dma = value & 0x8080;
if (value & (1 << 15)) /* RDMA_EN */
s->mask &= ~(1 << 3); /* RRDY_IE */
if (value & (1 << 7)) /* XDMA_EN */
s->mask &= ~(1 << 4); /* XRDY_IE */
if (value & (1 << 15)) /* RDMA_EN */
s->mask &= ~(1 << 3); /* RRDY_IE */
if (value & (1 << 7)) /* XDMA_EN */
s->mask &= ~(1 << 4); /* XRDY_IE */
break;
case 0x18: /* I2C_CNT */
s->count = value; /* DCOUNT */
case 0x18: /* I2C_CNT */
s->count = value; /* DCOUNT */
break;
case 0x1c: /* I2C_DATA */
case 0x1c: /* I2C_DATA */
if (s->txlen > 2) {
/* XXX: remote access (qualifier) error - what's that? */
break;
}
s->fifo <<= 16;
s->txlen += 2;
if (s->control & (1 << 14)) { /* BE */
if (s->control & (1 << 14)) { /* BE */
s->fifo |= ((value >> 8) & 0xff) << 8;
s->fifo |= ((value >> 0) & 0xff) << 0;
} else {
s->fifo |= ((value >> 0) & 0xff) << 8;
s->fifo |= ((value >> 8) & 0xff) << 0;
}
s->stat &= ~(1 << 10); /* XUDF */
s->stat &= ~(1 << 10); /* XUDF */
if (s->txlen > 2)
s->stat &= ~(1 << 4); /* XRDY */
s->stat &= ~(1 << 4); /* XRDY */
omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s);
break;
case 0x20: /* I2C_SYSC */
case 0x20: /* I2C_SYSC */
if (s->revision < OMAP2_INTR_REV) {
OMAP_BAD_REG(addr);
return;
@@ -332,9 +332,9 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
}
break;
case 0x24: /* I2C_CON */
case 0x24: /* I2C_CON */
s->control = value & 0xcf87;
if (~value & (1 << 15)) { /* I2C_EN */
if (~value & (1 << 15)) { /* I2C_EN */
if (s->revision < OMAP2_INTR_REV) {
omap_i2c_reset(DEVICE(s));
}
@@ -351,14 +351,14 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
__func__);
break;
}
if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
(~value >> 9) & 1); /* TRX */
s->stat |= nack << 1; /* NACK */
s->control &= ~(1 << 0); /* STT */
if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
(~value >> 9) & 1); /* TRX */
s->stat |= nack << 1; /* NACK */
s->control &= ~(1 << 0); /* STT */
s->fifo = 0;
if (nack)
s->control &= ~(1 << 1); /* STP */
s->control &= ~(1 << 1); /* STP */
else {
s->count_cur = s->count;
omap_i2c_fifo_run(s);
@@ -367,34 +367,34 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
}
break;
case 0x28: /* I2C_OA */
case 0x28: /* I2C_OA */
s->addr[0] = value & 0x3ff;
break;
case 0x2c: /* I2C_SA */
case 0x2c: /* I2C_SA */
s->addr[1] = value & 0x3ff;
break;
case 0x30: /* I2C_PSC */
case 0x30: /* I2C_PSC */
s->divider = value;
break;
case 0x34: /* I2C_SCLL */
case 0x34: /* I2C_SCLL */
s->times[0] = value;
break;
case 0x38: /* I2C_SCLH */
case 0x38: /* I2C_SCLH */
s->times[1] = value;
break;
case 0x3c: /* I2C_SYSTEST */
case 0x3c: /* I2C_SYSTEST */
s->test = value & 0xf80f;
if (value & (1 << 11)) /* SBB */
if (value & (1 << 11)) /* SBB */
if (s->revision >= OMAP2_INTR_REV) {
s->stat |= 0x3f;
omap_i2c_interrupts_update(s);
}
if (value & (1 << 15)) { /* ST_EN */
if (value & (1 << 15)) { /* ST_EN */
qemu_log_mask(LOG_UNIMP,
"%s: System Test not supported\n", __func__);
}
@@ -413,7 +413,7 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x1c: /* I2C_DATA */
case 0x1c: /* I2C_DATA */
if (s->txlen > 2) {
/* XXX: remote access (qualifier) error - what's that? */
break;
@@ -421,9 +421,9 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
s->fifo <<= 8;
s->txlen += 1;
s->fifo |= value & 0xff;
s->stat &= ~(1 << 10); /* XUDF */
s->stat &= ~(1 << 10); /* XUDF */
if (s->txlen > 2)
s->stat &= ~(1 << 4); /* XRDY */
s->stat &= ~(1 << 4); /* XRDY */
omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s);
break;
hw/intc/omap_intc.c
+77 -77
View File
@@ -102,8 +102,8 @@ static inline void omap_inth_update(OMAPIntcState *s, int is_fiq)
}
}
#define INT_FALLING_EDGE 0
#define INT_LOW_LEVEL 1
#define INT_FALLING_EDGE 0
#define INT_LOW_LEVEL 1
static void omap_set_intr(void *opaque, int irq, int req)
{
@@ -142,13 +142,13 @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
offset &= 0xff;
switch (offset) {
case 0x00: /* ITR */
case 0x00: /* ITR */
return bank->irqs;
case 0x04: /* MIR */
case 0x04: /* MIR */
return bank->mask;
case 0x10: /* SIR_IRQ_CODE */
case 0x10: /* SIR_IRQ_CODE */
case 0x14: /* SIR_FIQ_CODE */
if (bank_no != 0)
break;
@@ -159,49 +159,49 @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
bank->irqs &= ~(1 << i);
return line_no;
case 0x18: /* CONTROL_REG */
case 0x18: /* CONTROL_REG */
if (bank_no != 0)
break;
return 0;
case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */
case 0x24: /* ILR2 */
case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */
case 0x34: /* ILR6 */
case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */
case 0x44: /* ILR10 */
case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */
case 0x54: /* ILR14 */
case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */
case 0x64: /* ILR18 */
case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */
case 0x74: /* ILR22 */
case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */
case 0x84: /* ILR26 */
case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */
case 0x94: /* ILR30 */
case 0x98: /* ILR31 */
case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */
case 0x24: /* ILR2 */
case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */
case 0x34: /* ILR6 */
case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */
case 0x44: /* ILR10 */
case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */
case 0x54: /* ILR14 */
case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */
case 0x64: /* ILR18 */
case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */
case 0x74: /* ILR22 */
case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */
case 0x84: /* ILR26 */
case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */
case 0x94: /* ILR30 */
case 0x98: /* ILR31 */
i = (offset - 0x1c) >> 2;
return (bank->priority[i] << 2) |
(((bank->sens_edge >> i) & 1) << 1) |
((bank->fiq >> i) & 1);
case 0x9c: /* ISR */
case 0x9c: /* ISR */
return 0x00000000;
}
@@ -219,24 +219,24 @@ static void omap_inth_write(void *opaque, hwaddr addr,
offset &= 0xff;
switch (offset) {
case 0x00: /* ITR */
case 0x00: /* ITR */
/* Important: ignore the clearing if the IRQ is level-triggered and
the input bit is 1 */
bank->irqs &= value | (bank->inputs & bank->sens_edge);
return;
case 0x04: /* MIR */
case 0x04: /* MIR */
bank->mask = value;
omap_inth_update(s, 0);
omap_inth_update(s, 1);
return;
case 0x10: /* SIR_IRQ_CODE */
case 0x14: /* SIR_FIQ_CODE */
case 0x10: /* SIR_IRQ_CODE */
case 0x14: /* SIR_FIQ_CODE */
OMAP_RO_REG(addr);
break;
case 0x18: /* CONTROL_REG */
case 0x18: /* CONTROL_REG */
if (bank_no != 0)
break;
if (value & 2) {
@@ -251,38 +251,38 @@ static void omap_inth_write(void *opaque, hwaddr addr,
}
return;
case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */
case 0x24: /* ILR2 */
case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */
case 0x34: /* ILR6 */
case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */
case 0x44: /* ILR10 */
case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */
case 0x54: /* ILR14 */
case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */
case 0x64: /* ILR18 */
case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */
case 0x74: /* ILR22 */
case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */
case 0x84: /* ILR26 */
case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */
case 0x94: /* ILR30 */
case 0x98: /* ILR31 */
case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */
case 0x24: /* ILR2 */
case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */
case 0x34: /* ILR6 */
case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */
case 0x44: /* ILR10 */
case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */
case 0x54: /* ILR14 */
case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */
case 0x64: /* ILR18 */
case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */
case 0x74: /* ILR22 */
case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */
case 0x84: /* ILR26 */
case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */
case 0x94: /* ILR30 */
case 0x98: /* ILR31 */
i = (offset - 0x1c) >> 2;
bank->priority[i] = (value >> 2) & 0x1f;
bank->sens_edge &= ~(1 << i);
@@ -291,7 +291,7 @@ static void omap_inth_write(void *opaque, hwaddr addr,
bank->fiq |= (value & 1) << i;
return;
case 0x9c: /* ISR */
case 0x9c: /* ISR */
for (i = 0; i < 32; i ++)
if (value & (1 << i)) {
omap_set_intr(s, 32 * bank_no + i, 1);
hw/misc/omap_clk.c
+235 -235
View File
File diff suppressed because it is too large Load Diff
hw/timer/pxa2xx_timer.c
+38 -38
View File
@@ -19,41 +19,41 @@
#include "qom/object.h"
#include "system/watchdog.h"
#define OSMR0 0x00
#define OSMR1 0x04
#define OSMR2 0x08
#define OSMR3 0x0c
#define OSMR4 0x80
#define OSMR5 0x84
#define OSMR6 0x88
#define OSMR7 0x8c
#define OSMR8 0x90
#define OSMR9 0x94
#define OSMR10 0x98
#define OSMR11 0x9c
#define OSCR 0x10 /* OS Timer Count */
#define OSCR4 0x40
#define OSCR5 0x44
#define OSCR6 0x48
#define OSCR7 0x4c
#define OSCR8 0x50
#define OSCR9 0x54
#define OSCR10 0x58
#define OSCR11 0x5c
#define OSSR 0x14 /* Timer status register */
#define OWER 0x18
#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
#define OMCR4 0xc0 /* OS Match Control registers */
#define OMCR5 0xc4
#define OMCR6 0xc8
#define OMCR7 0xcc
#define OMCR8 0xd0
#define OMCR9 0xd4
#define OMCR10 0xd8
#define OMCR11 0xdc
#define OSNR 0x20
#define OSMR0 0x00
#define OSMR1 0x04
#define OSMR2 0x08
#define OSMR3 0x0c
#define OSMR4 0x80
#define OSMR5 0x84
#define OSMR6 0x88
#define OSMR7 0x8c
#define OSMR8 0x90
#define OSMR9 0x94
#define OSMR10 0x98
#define OSMR11 0x9c
#define OSCR 0x10 /* OS Timer Count */
#define OSCR4 0x40
#define OSCR5 0x44
#define OSCR6 0x48
#define OSCR7 0x4c
#define OSCR8 0x50
#define OSCR9 0x54
#define OSCR10 0x58
#define OSCR11 0x5c
#define OSSR 0x14 /* Timer status register */
#define OWER 0x18
#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
#define OMCR4 0xc0 /* OS Match Control registers */
#define OMCR5 0xc4
#define OMCR6 0xc8
#define OMCR7 0xcc
#define OMCR8 0xd0
#define OMCR9 0xd4
#define OMCR10 0xd8
#define OMCR11 0xdc
#define OSNR 0x20
#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
static int pxa2xx_timer4_freq[8] = {
[0] = 0,
@@ -106,7 +106,7 @@ struct PXA2xxTimerInfo {
PXA2xxTimer4 tm4[8];
};
#define PXA2XX_TIMER_HAVE_TM4 0
#define PXA2XX_TIMER_HAVE_TM4 0
static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
{
@@ -230,7 +230,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
NANOSECONDS_PER_SECOND);
case OIER:
return s->irq_enabled;
case OSSR: /* Status register */
case OSSR: /* Status register */
return s->events;
case OWER:
return s->reset3;
@@ -336,7 +336,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
case OIER:
s->irq_enabled = value & 0xfff;
break;
case OSSR: /* Status register */
case OSSR: /* Status register */
value &= s->events;
s->events &= ~value;
for (i = 0; i < 4; i ++, value >>= 1)
@@ -345,7 +345,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
qemu_irq_lower(s->irq4);
break;
case OWER: /* XXX: Reset on OSMR3 match? */
case OWER: /* XXX: Reset on OSMR3 match? */
s->reset3 = value;
break;
case OMCR7: tm ++;
include/exec/helper-head.h.inc
+11
View File
@@ -58,6 +58,17 @@
# define dh_ctype_tl target_ulong
#endif /* COMPILING_PER_TARGET */
#if __SIZEOF_POINTER__ == 4
# define dh_alias_vaddr i32
# define dh_typecode_vaddr dh_typecode_i32
#elif __SIZEOF_POINTER__ == 8
# define dh_alias_vaddr i64
# define dh_typecode_vaddr dh_typecode_i64
#else
# error "sizeof pointer is different from {4,8}"
#endif /* __SIZEOF_POINTER__ */
# define dh_ctype_vaddr uintptr_t
/* We can't use glue() here because it falls foul of C preprocessor
recursive expansion rules. */
#define dh_retvar_decl0_void void
include/hw/arm/omap.h
+267 -267
View File
File diff suppressed because it is too large Load Diff
include/hw/arm/sharpsl.h
+1 -1
View File
@@ -11,7 +11,7 @@
/* zaurus.c */
#define SL_PXA_PARAM_BASE 0xa0000a00
#define SL_PXA_PARAM_BASE 0xa0000a00
void sl_bootparam_write(hwaddr ptr);
#endif
include/hw/arm/soc_dma.h
+2 -2
View File
@@ -54,7 +54,7 @@ struct soc_dma_ch_s {
int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2];
hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */
void *paddr[2];
soc_dma_io_t io_fn[2];
@@ -70,7 +70,7 @@ struct soc_dma_ch_s {
struct soc_dma_s {
/* Following fields are set by the SoC DMA module and can be used
* by anybody. */
uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
qemu_irq *drq;
void *opaque;
int64_t freq;
include/system/hvf.h
+1
View File
@@ -17,6 +17,7 @@
#include "qemu/queue.h"
#include "exec/vaddr.h"
#include "qom/object.h"
#include "exec/vaddr.h"
#ifdef COMPILING_PER_TARGET
# ifdef CONFIG_HVF
include/tcg/tcg-op-common.h
+1
View File
@@ -14,6 +14,7 @@
TCGv_i32 tcg_constant_i32(int32_t val);
TCGv_i64 tcg_constant_i64(int64_t val);
TCGv_vaddr tcg_constant_vaddr(uintptr_t val);
TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
include/tcg/tcg.h
+14
View File
@@ -189,6 +189,7 @@ typedef tcg_target_ulong TCGArg;
* TCGv_i64 : 64 bit integer type
* TCGv_i128 : 128 bit integer type
* TCGv_ptr : a host pointer type
* TCGv_vaddr: an integer type wide enough to hold a target pointer type
* TCGv_vec : a host vector type; the exact size is not exposed
to the CPU front-end code.
* TCGv : an integer type the same size as target_ulong
@@ -217,6 +218,14 @@ typedef struct TCGv_ptr_d *TCGv_ptr;
typedef struct TCGv_vec_d *TCGv_vec;
typedef TCGv_ptr TCGv_env;
#if __SIZEOF_POINTER__ == 4
typedef TCGv_i32 TCGv_vaddr;
#elif __SIZEOF_POINTER__ == 8
typedef TCGv_i64 TCGv_vaddr;
#else
# error "sizeof pointer is different from {4,8}"
#endif /* __SIZEOF_POINTER__ */
/* call flags */
/* Helper does not read globals (either directly or through an exception). It
implies TCG_CALL_NO_WRITE_GLOBALS. */
@@ -577,6 +586,11 @@ static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
return (TCGv_ptr)temp_tcgv_i32(t);
}
static inline TCGv_vaddr temp_tcgv_vaddr(TCGTemp *t)
{
return (TCGv_vaddr)temp_tcgv_i32(t);
}
static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
{
return (TCGv_vec)temp_tcgv_i32(t);
meson.build
+61 -17
View File
@@ -3709,6 +3709,8 @@ target_arch = {}
target_system_arch = {}
target_user_arch = {}
hw_common_arch = {}
target_common_arch = {}
target_common_system_arch = {}
# NOTE: the trace/ subdirectory needs the qapi_trace_events variable
# that is filled in by qapi/.
@@ -4107,29 +4109,59 @@ common_all = static_library('common',
# construct common libraries per base architecture
hw_common_arch_libs = {}
target_common_arch_libs = {}
target_common_system_arch_libs = {}
foreach target : target_dirs
config_target = config_target_mak[target]
target_base_arch = config_target['TARGET_BASE_ARCH']
target_inc = [include_directories('target' / target_base_arch)]
inc = [common_user_inc + target_inc]
# check if already generated
if target_base_arch in hw_common_arch_libs
continue
endif
# prevent common code to access cpu compile time definition,
# but still allow access to cpu.h
target_c_args = ['-DCPU_DEFS_H']
target_system_c_args = target_c_args + ['-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOFTMMU']
if target_base_arch in hw_common_arch
target_inc = [include_directories('target' / target_base_arch)]
src = hw_common_arch[target_base_arch]
lib = static_library(
'hw_' + target_base_arch,
build_by_default: false,
sources: src.all_sources() + genh,
include_directories: common_user_inc + target_inc,
implicit_include_directories: false,
# prevent common code to access cpu compile time
# definition, but still allow access to cpu.h
c_args: ['-DCPU_DEFS_H', '-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOFTMMU'],
dependencies: src.all_dependencies())
hw_common_arch_libs += {target_base_arch: lib}
if target_base_arch not in hw_common_arch_libs
src = hw_common_arch[target_base_arch]
lib = static_library(
'hw_' + target_base_arch,
build_by_default: false,
sources: src.all_sources() + genh,
include_directories: inc,
c_args: target_system_c_args,
dependencies: src.all_dependencies())
hw_common_arch_libs += {target_base_arch: lib}
endif
endif
if target_base_arch in target_common_arch
if target_base_arch not in target_common_arch_libs
src = target_common_arch[target_base_arch]
lib = static_library(
'target_' + target_base_arch,
build_by_default: false,
sources: src.all_sources() + genh,
include_directories: inc,
c_args: target_c_args,
dependencies: src.all_dependencies())
target_common_arch_libs += {target_base_arch: lib}
endif
endif
if target_base_arch in target_common_system_arch
if target_base_arch not in target_common_system_arch_libs
src = target_common_system_arch[target_base_arch]
lib = static_library(
'target_system_' + target_base_arch,
build_by_default: false,
sources: src.all_sources() + genh,
include_directories: inc,
c_args: target_system_c_args,
dependencies: src.all_dependencies())
target_common_system_arch_libs += {target_base_arch: lib}
endif
endif
endforeach
@@ -4300,12 +4332,24 @@ foreach target : target_dirs
target_common = common_ss.apply(config_target, strict: false)
objects = [common_all.extract_objects(target_common.sources())]
arch_deps += target_common.dependencies()
if target_base_arch in target_common_arch_libs
src = target_common_arch[target_base_arch].apply(config_target, strict: false)
lib = target_common_arch_libs[target_base_arch]
objects += lib.extract_objects(src.sources())
arch_deps += src.dependencies()
endif
if target_type == 'system' and target_base_arch in hw_common_arch_libs
src = hw_common_arch[target_base_arch].apply(config_target, strict: false)
lib = hw_common_arch_libs[target_base_arch]
objects += lib.extract_objects(src.sources())
arch_deps += src.dependencies()
endif
if target_type == 'system' and target_base_arch in target_common_system_arch_libs
src = target_common_system_arch[target_base_arch].apply(config_target, strict: false)
lib = target_common_system_arch_libs[target_base_arch]
objects += lib.extract_objects(src.sources())
arch_deps += src.dependencies()
endif
target_specific = specific_ss.apply(config_target, strict: false)
arch_srcs += target_specific.sources()
rust/hw/char/pl011/src/registers.rs
+51 -210
View File
@@ -5,13 +5,13 @@
//! Device registers exposed as typed structs which are backed by arbitrary
//! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
// For more detail see the PL011 Technical Reference Manual DDI0183:
// https://developer.arm.com/documentation/ddi0183/latest/
use bilge::prelude::*;
use qemu_api::impl_vmstate_bitsized;
/// Offset of each register from the base memory address of the device.
///
/// # Source
/// ARM DDI 0183G, Table 3-1 p.3-3
#[doc(alias = "offset")]
#[allow(non_camel_case_types)]
#[repr(u64)]
@@ -87,48 +87,11 @@ pub struct Errors {
_reserved_unpredictable: u4,
}
// TODO: FIFO Mode has different semantics
/// Data Register, `UARTDR`
///
/// The `UARTDR` register is the data register.
///
/// For words to be transmitted:
///
/// - if the FIFOs are enabled, data written to this location is pushed onto the
/// transmit
/// FIFO
/// - if the FIFOs are not enabled, data is stored in the transmitter holding
/// register (the
/// bottom word of the transmit FIFO).
///
/// The write operation initiates transmission from the UART. The data is
/// prefixed with a start bit, appended with the appropriate parity bit
/// (if parity is enabled), and a stop bit. The resultant word is then
/// transmitted.
///
/// For received words:
///
/// - if the FIFOs are enabled, the data byte and the 4-bit status (break,
/// frame, parity,
/// and overrun) is pushed onto the 12-bit wide receive FIFO
/// - if the FIFOs are not enabled, the data byte and status are stored in the
/// receiving
/// holding register (the bottom word of the receive FIFO).
///
/// The received data byte is read by performing reads from the `UARTDR`
/// register along with the corresponding status information. The status
/// information can also be read by a read of the `UARTRSR/UARTECR`
/// register.
///
/// # Note
///
/// You must disable the UART before any of the control registers are
/// reprogrammed. When the UART is disabled in the middle of
/// transmission or reception, it completes the current character before
/// stopping.
///
/// # Source
/// ARM DDI 0183G 3.3.1 Data Register, UARTDR
/// The `UARTDR` register is the data register; write for TX and
/// read for RX. It is a 12-bit register, where bits 7..0 are the
/// character and bits 11..8 are error bits.
#[bitsize(32)]
#[derive(Clone, Copy, Default, DebugBits, FromBits)]
#[doc(alias = "UARTDR")]
@@ -144,30 +107,17 @@ impl Data {
pub const BREAK: Self = Self { value: 1 << 10 };
}
// TODO: FIFO Mode has different semantics
/// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR`
///
/// The UARTRSR/UARTECR register is the receive status register/error clear
/// register. Receive status can also be read from the `UARTRSR`
/// register. If the status is read from this register, then the status
/// information for break, framing and parity corresponds to the
/// data character read from the [Data register](Data), `UARTDR` prior to
/// reading the UARTRSR register. The status information for overrun is
/// set immediately when an overrun condition occurs.
/// This register provides a different way to read the four receive
/// status error bits that can be found in bits 11..8 of the UARTDR
/// on a read. It gets updated when the guest reads UARTDR, and the
/// status bits correspond to that character that was just read.
///
///
/// # Note
/// The received data character must be read first from the [Data
/// Register](Data), `UARTDR` before reading the error status associated
/// with that data character from the `UARTRSR` register. This read
/// sequence cannot be reversed, because the `UARTRSR` register is
/// updated only when a read occurs from the `UARTDR` register. However,
/// the status information can also be obtained by reading the `UARTDR`
/// register
///
/// # Source
/// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register,
/// UARTRSR/UARTECR
/// The TRM confusingly describes this offset as UARTRSR for reads
/// and UARTECR for writes, but really it's a single error status
/// register where writing anything to the register clears the error
/// bits.
#[bitsize(32)]
#[derive(Clone, Copy, DebugBits, FromBits)]
pub struct ReceiveStatusErrorClear {
@@ -196,54 +146,29 @@ impl Default for ReceiveStatusErrorClear {
#[bitsize(32)]
#[derive(Clone, Copy, DebugBits, FromBits)]
/// Flag Register, `UARTFR`
///
/// This has the usual inbound RS232 modem-control signals, plus flags
/// for RX and TX FIFO fill levels and a BUSY flag.
#[doc(alias = "UARTFR")]
pub struct Flags {
/// CTS Clear to send. This bit is the complement of the UART clear to
/// send, `nUARTCTS`, modem status input. That is, the bit is 1
/// when `nUARTCTS` is LOW.
/// CTS: Clear to send
pub clear_to_send: bool,
/// DSR Data set ready. This bit is the complement of the UART data set
/// ready, `nUARTDSR`, modem status input. That is, the bit is 1 when
/// `nUARTDSR` is LOW.
/// DSR: Data set ready
pub data_set_ready: bool,
/// DCD Data carrier detect. This bit is the complement of the UART data
/// carrier detect, `nUARTDCD`, modem status input. That is, the bit is
/// 1 when `nUARTDCD` is LOW.
/// DCD: Data carrier detect
pub data_carrier_detect: bool,
/// BUSY UART busy. If this bit is set to 1, the UART is busy
/// transmitting data. This bit remains set until the complete
/// byte, including all the stop bits, has been sent from the
/// shift register. This bit is set as soon as the transmit FIFO
/// becomes non-empty, regardless of whether the UART is enabled
/// or not.
/// BUSY: UART busy. In real hardware, set while the UART is
/// busy transmitting data. QEMU's implementation never sets BUSY.
pub busy: bool,
/// RXFE Receive FIFO empty. The meaning of this bit depends on the
/// state of the FEN bit in the UARTLCR_H register. If the FIFO
/// is disabled, this bit is set when the receive holding
/// register is empty. If the FIFO is enabled, the RXFE bit is
/// set when the receive FIFO is empty.
/// RXFE: Receive FIFO empty
pub receive_fifo_empty: bool,
/// TXFF Transmit FIFO full. The meaning of this bit depends on the
/// state of the FEN bit in the UARTLCR_H register. If the FIFO
/// is disabled, this bit is set when the transmit holding
/// register is full. If the FIFO is enabled, the TXFF bit is
/// set when the transmit FIFO is full.
/// TXFF: Transmit FIFO full
pub transmit_fifo_full: bool,
/// RXFF Receive FIFO full. The meaning of this bit depends on the state
/// of the FEN bit in the UARTLCR_H register. If the FIFO is
/// disabled, this bit is set when the receive holding register
/// is full. If the FIFO is enabled, the RXFF bit is set when
/// the receive FIFO is full.
/// RXFF: Receive FIFO full
pub receive_fifo_full: bool,
/// Transmit FIFO empty. The meaning of this bit depends on the state of
/// the FEN bit in the [Line Control register](LineControl),
/// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the
/// transmit holding register is empty. If the FIFO is enabled,
/// the TXFE bit is set when the transmit FIFO is empty. This
/// bit does not indicate if there is data in the transmit shift
/// register.
/// TXFE: Transmit FIFO empty
pub transmit_fifo_empty: bool,
/// `RI`, is `true` when `nUARTRI` is `LOW`.
/// RI: Ring indicator
pub ring_indicator: bool,
_reserved_zero_no_modify: u23,
}
@@ -270,54 +195,23 @@ impl Default for Flags {
/// Line Control Register, `UARTLCR_H`
#[doc(alias = "UARTLCR_H")]
pub struct LineControl {
/// BRK Send break.
///
/// If this bit is set to `1`, a low-level is continually output on the
/// `UARTTXD` output, after completing transmission of the
/// current character. For the proper execution of the break command,
/// the software must set this bit for at least two complete
/// frames. For normal use, this bit must be cleared to `0`.
/// BRK: Send break
pub send_break: bool,
/// 1 PEN Parity enable:
///
/// - 0 = parity is disabled and no parity bit added to the data frame
/// - 1 = parity checking and generation is enabled.
///
/// See Table 3-11 on page 3-14 for the parity truth table.
/// PEN: Parity enable
pub parity_enabled: bool,
/// EPS Even parity select. Controls the type of parity the UART uses
/// during transmission and reception:
/// - 0 = odd parity. The UART generates or checks for an odd number of 1s
/// in the data and parity bits.
/// - 1 = even parity. The UART generates or checks for an even number of 1s
/// in the data and parity bits.
/// This bit has no effect when the `PEN` bit disables parity checking
/// and generation. See Table 3-11 on page 3-14 for the parity
/// truth table.
/// EPS: Even parity select
pub parity: Parity,
/// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits
/// are transmitted at the end of the frame. The receive
/// logic does not check for two stop bits being received.
/// STP2: Two stop bits select
pub two_stops_bits: bool,
/// FEN Enable FIFOs:
/// 0 = FIFOs are disabled (character mode) that is, the FIFOs become
/// 1-byte-deep holding registers 1 = transmit and receive FIFO
/// buffers are enabled (FIFO mode).
/// FEN: Enable FIFOs
pub fifos_enabled: Mode,
/// WLEN Word length. These bits indicate the number of data bits
/// transmitted or received in a frame as follows: b11 = 8 bits
/// WLEN: Word length in bits
/// b11 = 8 bits
/// b10 = 7 bits
/// b01 = 6 bits
/// b00 = 5 bits.
pub word_length: WordLength,
/// 7 SPS Stick parity select.
/// 0 = stick parity is disabled
/// 1 = either:
/// • if the EPS bit is 0 then the parity bit is transmitted and checked
/// as a 1 • if the EPS bit is 1 then the parity bit is
/// transmitted and checked as a 0. This bit has no effect when
/// the PEN bit disables parity checking and generation. See Table 3-11
/// on page 3-14 for the parity truth table.
/// SPS Stick parity select
pub sticky_parity: bool,
/// 31:8 - Reserved, do not modify, read as zero.
_reserved_zero_no_modify: u24,
@@ -342,11 +236,7 @@ impl Default for LineControl {
/// `EPS` "Even parity select", field of [Line Control
/// register](LineControl).
pub enum Parity {
/// - 0 = odd parity. The UART generates or checks for an odd number of 1s
/// in the data and parity bits.
Odd = 0,
/// - 1 = even parity. The UART generates or checks for an even number of 1s
/// in the data and parity bits.
Even = 1,
}
@@ -381,88 +271,39 @@ pub enum WordLength {
/// Control Register, `UARTCR`
///
/// The `UARTCR` register is the control register. All the bits are cleared
/// to `0` on reset except for bits `9` and `8` that are set to `1`.
///
/// # Source
/// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12
/// The `UARTCR` register is the control register. It contains various
/// enable bits, and the bits to write to set the usual outbound RS232
/// modem control signals. All bits reset to 0 except TXE and RXE.
#[bitsize(32)]
#[doc(alias = "UARTCR")]
#[derive(Clone, Copy, DebugBits, FromBits)]
pub struct Control {
/// `UARTEN` UART enable: 0 = UART is disabled. If the UART is disabled
/// in the middle of transmission or reception, it completes the current
/// character before stopping. 1 = the UART is enabled. Data
/// transmission and reception occurs for either UART signals or SIR
/// signals depending on the setting of the SIREN bit.
/// `UARTEN` UART enable: 0 = UART is disabled.
pub enable_uart: bool,
/// `SIREN` `SIR` enable: 0 = IrDA SIR ENDEC is disabled. `nSIROUT`
/// remains LOW (no light pulse generated), and signal transitions on
/// SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is
/// transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH,
/// in the marking state. Signal transitions on UARTRXD or modem status
/// inputs have no effect. This bit has no effect if the UARTEN bit
/// disables the UART.
/// `SIREN` `SIR` enable: disable or enable IrDA SIR ENDEC.
/// QEMU does not model this.
pub enable_sir: bool,
/// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding
/// mode. If this bit is cleared to 0, low-level bits are transmitted as
/// an active high pulse with a width of 3/ 16th of the bit period. If
/// this bit is set to 1, low-level bits are transmitted with a pulse
/// width that is 3 times the period of the IrLPBaud16 input signal,
/// regardless of the selected bit rate. Setting this bit uses less
/// power, but might reduce transmission distances.
/// `SIRLP` SIR low-power IrDA mode. QEMU does not model this.
pub sir_lowpower_irda_mode: u1,
/// Reserved, do not modify, read as zero.
_reserved_zero_no_modify: u4,
/// `LBE` Loopback enable. If this bit is set to 1 and the SIREN bit is
/// set to 1 and the SIRTEST bit in the Test Control register, UARTTCR
/// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed
/// through to the SIRIN path. The SIRTEST bit in the test register must
/// be set to 1 to override the normal half-duplex SIR operation. This
/// must be the requirement for accessing the test registers during
/// normal operation, and SIRTEST must be cleared to 0 when loopback
/// testing is finished. This feature reduces the amount of external
/// coupling required during system test. If this bit is set to 1, and
/// the SIRTEST bit is set to 0, the UARTTXD path is fed through to the
/// UARTRXD path. In either SIR mode or UART mode, when this bit is set,
/// the modem outputs are also fed through to the modem inputs. This bit
/// is cleared to 0 on reset, to disable loopback.
/// `LBE` Loopback enable: feed UART output back to the input
pub enable_loopback: bool,
/// `TXE` Transmit enable. If this bit is set to 1, the transmit section
/// of the UART is enabled. Data transmission occurs for either UART
/// signals, or SIR signals depending on the setting of the SIREN bit.
/// When the UART is disabled in the middle of transmission, it
/// completes the current character before stopping.
/// `TXE` Transmit enable
pub enable_transmit: bool,
/// `RXE` Receive enable. If this bit is set to 1, the receive section
/// of the UART is enabled. Data reception occurs for either UART
/// signals or SIR signals depending on the setting of the SIREN bit.
/// When the UART is disabled in the middle of reception, it completes
/// the current character before stopping.
/// `RXE` Receive enable
pub enable_receive: bool,
/// `DTR` Data transmit ready. This bit is the complement of the UART
/// data transmit ready, `nUARTDTR`, modem status output. That is, when
/// the bit is programmed to a 1 then `nUARTDTR` is LOW.
/// `DTR` Data transmit ready
pub data_transmit_ready: bool,
/// `RTS` Request to send. This bit is the complement of the UART
/// request to send, `nUARTRTS`, modem status output. That is, when the
/// bit is programmed to a 1 then `nUARTRTS` is LOW.
/// `RTS` Request to send
pub request_to_send: bool,
/// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1`)
/// modem status output. That is, when the bit is programmed to a 1 the
/// output is 0. For DTE this can be used as Data Carrier Detect (DCD).
/// `Out1` UART Out1 signal; can be used as DCD
pub out_1: bool,
/// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2`)
/// modem status output. That is, when the bit is programmed to a 1, the
/// output is 0. For DTE this can be used as Ring Indicator (RI).
/// `Out2` UART Out2 signal; can be used as RI
pub out_2: bool,
/// `RTSEn` RTS hardware flow control enable. If this bit is set to 1,
/// RTS hardware flow control is enabled. Data is only requested when
/// there is space in the receive FIFO for it to be received.
/// `RTSEn` RTS hardware flow control enable
pub rts_hardware_flow_control_enable: bool,
/// `CTSEn` CTS hardware flow control enable. If this bit is set to 1,
/// CTS hardware flow control is enabled. Data is only transmitted when
/// the `nUARTCTS` signal is asserted.
/// `CTSEn` CTS hardware flow control enable
pub cts_hardware_flow_control_enable: bool,
/// 31:16 - Reserved, do not modify, read as zero.
_reserved_zero_no_modify2: u16,
target/arm/arch_dump.c
-6
View File
@@ -143,7 +143,6 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
return 0;
}
#ifdef TARGET_AARCH64
static off_t sve_zreg_offset(uint32_t vq, int n)
{
off_t off = sizeof(struct aarch64_user_sve_header);
@@ -231,7 +230,6 @@ static int aarch64_write_elf64_sve(WriteCoreDumpFunction f,
return 0;
}
#endif
int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s)
@@ -273,11 +271,9 @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
return ret;
}
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) {
ret = aarch64_write_elf64_sve(f, env, cpuid, s);
}
#endif
return ret;
}
@@ -451,11 +447,9 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
if (class == ELFCLASS64) {
note_size = AARCH64_PRSTATUS_NOTE_SIZE;
note_size += AARCH64_PRFPREG_NOTE_SIZE;
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) {
note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);
}
#endif
} else {
note_size = ARM_PRSTATUS_NOTE_SIZE;
if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

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