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hw/ufs: Add support MCQ of UFSHCI 4.0

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This patch adds support for MCQ defined in UFSHCI 4.0.  This patch
utilized the legacy I/O codes as much as possible to support MCQ.

MCQ operation & runtime register is placed at 0x1000 offset of UFSHCI
register statically with no spare space among four registers (48B):

	UfsMcqSqReg, UfsMcqSqIntReg, UfsMcqCqReg, UfsMcqCqIntReg

The maxinum number of queue is 32 as per spec, and the default
MAC(Multiple Active Commands) are 32 in the device.

Example:
	-device ufs,serial=foo,id=ufs0,mcq=true,mcq-maxq=8

Signed-off-by: Minwoo Im <minwoo.im@samsung.com>
Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com>
Message-Id: <20240528023106.856777-3-minwoo.im@samsung.com>
Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
This commit is contained in:
Minwoo Im
2024-06-03 16:20:42 +09:00
committed by Jeuk Kim
parent cdba3b901a
commit 5c079578d2
4 changed files with 593 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/ufs/trace-events
+17
View File
@@ -11,13 +11,18 @@ ufs_exec_nop_cmd(uint32_t slot) "UTRLDBR slot %"PRIu32""
ufs_exec_scsi_cmd(uint32_t slot, uint8_t lun, uint8_t opcode) "slot %"PRIu32", lun 0x%"PRIx8", opcode 0x%"PRIx8""
ufs_exec_query_cmd(uint32_t slot, uint8_t opcode) "slot %"PRIu32", opcode 0x%"PRIx8""
ufs_process_uiccmd(uint32_t uiccmd, uint32_t ucmdarg1, uint32_t ucmdarg2, uint32_t ucmdarg3) "uiccmd 0x%"PRIx32", ucmdarg1 0x%"PRIx32", ucmdarg2 0x%"PRIx32", ucmdarg3 0x%"PRIx32""
ufs_mcq_complete_req(uint8_t qid) "sqid %"PRIu8""
ufs_mcq_create_sq(uint8_t sqid, uint8_t cqid, uint64_t addr, uint16_t size) "mcq create sq sqid %"PRIu8", cqid %"PRIu8", addr 0x%"PRIx64", size %"PRIu16""
ufs_mcq_create_cq(uint8_t cqid, uint64_t addr, uint16_t size) "mcq create cq cqid %"PRIu8", addr 0x%"PRIx64", size %"PRIu16""
# error condition
ufs_err_dma_read_utrd(uint32_t slot, uint64_t addr) "failed to read utrd. UTRLDBR slot %"PRIu32", UTRD dma addr %"PRIu64""
ufs_err_dma_read_req_upiu(uint32_t slot, uint64_t addr) "failed to read req upiu. UTRLDBR slot %"PRIu32", request upiu addr %"PRIu64""
ufs_err_dma_read_prdt(uint32_t slot, uint64_t addr) "failed to read prdt. UTRLDBR slot %"PRIu32", prdt addr %"PRIu64""
ufs_err_dma_read_sq(uint8_t sqid, uint64_t addr) "failed to read sq entry. sqid %"PRIu8", hwaddr %"PRIu64""
ufs_err_dma_write_utrd(uint32_t slot, uint64_t addr) "failed to write utrd. UTRLDBR slot %"PRIu32", UTRD dma addr %"PRIu64""
ufs_err_dma_write_rsp_upiu(uint32_t slot, uint64_t addr) "failed to write rsp upiu. UTRLDBR slot %"PRIu32", response upiu addr %"PRIu64""
ufs_err_dma_write_cq(uint8_t cqid, uint64_t addr) "failed to write cq entry. cqid %"PRIu8", hwaddr %"PRIu64""
ufs_err_utrl_slot_error(uint32_t slot) "UTRLDBR slot %"PRIu32" is in error"
ufs_err_utrl_slot_busy(uint32_t slot) "UTRLDBR slot %"PRIu32" is busy"
ufs_err_unsupport_register_offset(uint32_t offset) "Register offset 0x%"PRIx32" is not yet supported"
@@ -31,3 +36,15 @@ ufs_err_query_invalid_opcode(uint8_t opcode) "query request has invalid opcode.
ufs_err_query_invalid_idn(uint8_t opcode, uint8_t idn) "query request has invalid idn. opcode: 0x%"PRIx8", idn 0x%"PRIx8""
ufs_err_query_invalid_index(uint8_t opcode, uint8_t index) "query request has invalid index. opcode: 0x%"PRIx8", index 0x%"PRIx8""
ufs_err_invalid_trans_code(uint32_t slot, uint8_t trans_code) "request upiu has invalid transaction code. slot: %"PRIu32", trans_code: 0x%"PRIx8""
ufs_err_mcq_db_wr_invalid_sqid(uint8_t qid) "invalid mcq sqid %"PRIu8""
ufs_err_mcq_db_wr_invalid_db(uint8_t qid, uint32_t db) "invalid mcq doorbell sqid %"PRIu8", db %"PRIu32""
ufs_err_mcq_create_sq_invalid_sqid(uint8_t qid) "invalid mcq sqid %"PRIu8""
ufs_err_mcq_create_sq_invalid_cqid(uint8_t qid) "invalid mcq cqid %"PRIu8""
ufs_err_mcq_create_sq_already_exists(uint8_t qid) "mcq sqid %"PRIu8 "already exists"
ufs_err_mcq_delete_sq_invalid_sqid(uint8_t qid) "invalid mcq sqid %"PRIu8""
ufs_err_mcq_delete_sq_not_exists(uint8_t qid) "mcq sqid %"PRIu8 "not exists"
ufs_err_mcq_create_cq_invalid_cqid(uint8_t qid) "invalid mcq cqid %"PRIu8""
ufs_err_mcq_create_cq_already_exists(uint8_t qid) "mcq cqid %"PRIu8 "already exists"
ufs_err_mcq_delete_cq_invalid_cqid(uint8_t qid) "invalid mcq cqid %"PRIu8""
ufs_err_mcq_delete_cq_not_exists(uint8_t qid) "mcq cqid %"PRIu8 "not exists"
ufs_err_mcq_delete_cq_sq_not_deleted(uint8_t sqid, uint8_t cqid) "mcq sq %"PRIu8" still has cq %"PRIu8""
hw/ufs/ufs.c
+457 -18
View File
File diff suppressed because it is too large Load Diff
hw/ufs/ufs.h
+97 -1
View File
@@ -16,6 +16,7 @@
#include "block/ufs.h"
#define UFS_MAX_LUS 32
#define UFS_MAX_MCQ_QNUM 32
#define UFS_BLOCK_SIZE_SHIFT 12
#define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SIZE_SHIFT)
@@ -45,10 +46,11 @@ typedef enum UfsReqResult {
UFS_REQUEST_NO_COMPLETE = 2,
} UfsReqResult;
#define UFS_INVALID_SLOT (-1)
typedef struct UfsRequest {
struct UfsHc *hc;
UfsRequestState state;
int slot;
int slot; /* -1 when it's a MCQ request */
UtpTransferReqDesc utrd;
UtpUpiuReq req_upiu;
@@ -57,8 +59,18 @@ typedef struct UfsRequest {
/* for scsi command */
QEMUSGList *sg;
uint32_t data_len;
/* for MCQ */
struct UfsSq *sq;
struct UfsCqEntry cqe;
QTAILQ_ENTRY(UfsRequest) entry;
} UfsRequest;
static inline bool ufs_mcq_req(UfsRequest *req)
{
return req->sq != NULL;
}
struct UfsLu;
typedef UfsReqResult (*UfsScsiOp)(struct UfsLu *, UfsRequest *);
@@ -76,13 +88,43 @@ typedef struct UfsParams {
char *serial;
uint8_t nutrs; /* Number of UTP Transfer Request Slots */
uint8_t nutmrs; /* Number of UTP Task Management Request Slots */
bool mcq; /* Multiple Command Queue support */
uint8_t mcq_qcfgptr; /* MCQ Queue Configuration Pointer in MCQCAP */
uint8_t mcq_maxq; /* MCQ Maximum number of Queues */
} UfsParams;
/*
* MCQ Properties
*/
typedef struct UfsSq {
struct UfsHc *u;
uint8_t sqid;
struct UfsCq *cq;
uint64_t addr;
uint16_t size; /* A number of entries (qdepth) */
QEMUBH *bh; /* Bottom half to process requests in async */
UfsRequest *req;
QTAILQ_HEAD(, UfsRequest) req_list; /* Free request list */
} UfsSq;
typedef struct UfsCq {
struct UfsHc *u;
uint8_t cqid;
uint64_t addr;
uint16_t size; /* A number of entries (qdepth) */
QEMUBH *bh;
QTAILQ_HEAD(, UfsRequest) req_list;
} UfsCq;
typedef struct UfsHc {
PCIDevice parent_obj;
UfsBus bus;
MemoryRegion iomem;
UfsReg reg;
UfsMcqReg mcq_reg[UFS_MAX_MCQ_QNUM];
UfsMcqOpReg mcq_op_reg[UFS_MAX_MCQ_QNUM];
UfsParams params;
uint32_t reg_size;
UfsRequest *req_list;
@@ -100,8 +142,62 @@ typedef struct UfsHc {
qemu_irq irq;
QEMUBH *doorbell_bh;
QEMUBH *complete_bh;
/* MCQ properties */
UfsSq *sq[UFS_MAX_MCQ_QNUM];
UfsCq *cq[UFS_MAX_MCQ_QNUM];
} UfsHc;
static inline uint32_t ufs_mcq_sq_tail(UfsHc *u, uint32_t qid)
{
return u->mcq_op_reg[qid].sq.tp;
}
static inline void ufs_mcq_update_sq_tail(UfsHc *u, uint32_t qid, uint32_t db)
{
u->mcq_op_reg[qid].sq.tp = db;
}
static inline uint32_t ufs_mcq_sq_head(UfsHc *u, uint32_t qid)
{
return u->mcq_op_reg[qid].sq.hp;
}
static inline void ufs_mcq_update_sq_head(UfsHc *u, uint32_t qid, uint32_t db)
{
u->mcq_op_reg[qid].sq.hp = db;
}
static inline bool ufs_mcq_sq_empty(UfsHc *u, uint32_t qid)
{
return ufs_mcq_sq_tail(u, qid) == ufs_mcq_sq_head(u, qid);
}
static inline uint32_t ufs_mcq_cq_tail(UfsHc *u, uint32_t qid)
{
return u->mcq_op_reg[qid].cq.tp;
}
static inline void ufs_mcq_update_cq_tail(UfsHc *u, uint32_t qid, uint32_t db)
{
u->mcq_op_reg[qid].cq.tp = db;
}
static inline uint32_t ufs_mcq_cq_head(UfsHc *u, uint32_t qid)
{
return u->mcq_op_reg[qid].cq.hp;
}
static inline void ufs_mcq_update_cq_head(UfsHc *u, uint32_t qid, uint32_t db)
{
u->mcq_op_reg[qid].cq.hp = db;
}
static inline bool ufs_mcq_cq_empty(UfsHc *u, uint32_t qid)
{
return ufs_mcq_cq_tail(u, qid) == ufs_mcq_cq_head(u, qid);
}
#define TYPE_UFS "ufs"
#define UFS(obj) OBJECT_CHECK(UfsHc, (obj), TYPE_UFS)
include/block/ufs.h
+22 -1
View File
@@ -152,7 +152,8 @@ REG32(MCQCONFIG, offsetof(UfsReg, mcqconfig))
FIELD(MCQCONFIG, MAC, 8, 8)
#define UFS_INTR_MASK \
((1 << R_IS_CEFES_SHIFT) | (1 << R_IS_SBFES_SHIFT) | \
((1 << R_IS_CQES_SHIFT) | \
(1 << R_IS_CEFES_SHIFT) | (1 << R_IS_SBFES_SHIFT) | \
(1 << R_IS_HCFES_SHIFT) | (1 << R_IS_UTPES_SHIFT) | \
(1 << R_IS_DFES_SHIFT) | (1 << R_IS_UCCS_SHIFT) | \
(1 << R_IS_UTMRCS_SHIFT) | (1 << R_IS_ULSS_SHIFT) | \
@@ -242,6 +243,21 @@ typedef struct QEMU_PACKED UfsMcqCqIntReg {
REG32(CQIS, offsetof(UfsMcqCqIntReg, is))
FIELD(CQIS, TEPS, 0, 1)
/*
* Provide MCQ Operation & Runtime Registers as a contiguous addressed
* registers for the simplicity.
* DAO(Doorbell Address Offset) and ISAO(Interrupt Status Register Address
* Offset) registers should be properly configured with the following
* structure.
*/
#define UFS_MCQ_OPR_START 0x1000
typedef struct QEMU_PACKED UfsMcqOpReg {
UfsMcqSqReg sq;
UfsMcqSqIntReg sq_int;
UfsMcqCqReg cq;
UfsMcqCqIntReg cq_int;
} UfsMcqOpReg;
typedef struct QEMU_PACKED DeviceDescriptor {
uint8_t length;
uint8_t descriptor_idn;
@@ -1169,6 +1185,11 @@ static inline void _ufs_check_size(void)
{
QEMU_BUILD_BUG_ON(sizeof(UfsReg) != 0x38C);
QEMU_BUILD_BUG_ON(sizeof(UfsMcqReg) != 64);
QEMU_BUILD_BUG_ON(sizeof(UfsMcqSqReg) != 20);
QEMU_BUILD_BUG_ON(sizeof(UfsMcqCqReg) != 8);
QEMU_BUILD_BUG_ON(sizeof(UfsMcqSqIntReg) != 8);
QEMU_BUILD_BUG_ON(sizeof(UfsMcqCqIntReg) != 12);
QEMU_BUILD_BUG_ON(sizeof(UfsMcqOpReg) != 48);
QEMU_BUILD_BUG_ON(sizeof(DeviceDescriptor) != 89);
QEMU_BUILD_BUG_ON(sizeof(GeometryDescriptor) != 87);
QEMU_BUILD_BUG_ON(sizeof(UnitDescriptor) != 45);