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target/openrisc: Replace target_ulong -> uint32_t

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The OpenRISC targets are only built as 32-bit:

  $ git grep TARGET_LONG_BITS configs/targets/or1k-*
  configs/targets/or1k-linux-user.mak:5:TARGET_LONG_BITS=32
  configs/targets/or1k-softmmu.mak:5:TARGET_LONG_BITS=32

Therefore target_ulong always expands to uint32_t. Replace and
adapt the API uses mechanically:

  target_ulong -> uint32_t
  target_long -> int32_t
  tl -> i32
  TCGv -> TCGv_i32
  tcg_temp_new -> tcg_temp_new_i32
  tcg_global_mem_new -> tcg_global_mem_new_i32
  VMSTATE_UINTTL -> VMSTATE_UINT32

There is no functional change (the migration stream is not modified).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010070702.51484-14-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2025-10-16 17:07:28 +02:00
parent 500708331e
commit 5b67dbf1dc
6 changed files with 228 additions and 222 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/openrisc/cpu.h
+11 -11
View File
@@ -224,20 +224,20 @@ typedef struct CPUOpenRISCTLBContext {
#endif
typedef struct CPUArchState {
target_ulong shadow_gpr[16][32]; /* Shadow registers */
uint32_t shadow_gpr[16][32]; /* Shadow registers */
target_ulong pc; /* Program counter */
target_ulong ppc; /* Prev PC */
target_ulong jmp_pc; /* Jump PC */
uint32_t pc; /* Program counter */
uint32_t ppc; /* Prev PC */
uint32_t jmp_pc; /* Jump PC */
uint64_t mac; /* Multiply registers MACHI:MACLO */
target_ulong epcr; /* Exception PC register */
target_ulong eear; /* Exception EA register */
uint32_t epcr; /* Exception PC register */
uint32_t eear; /* Exception EA register */
target_ulong sr_f; /* the SR_F bit, values 0, 1. */
target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */
target_long sr_ov; /* the SR_OV bit (in the sign bit only) */
uint32_t sr_f; /* the SR_F bit, values 0, 1. */
uint32_t sr_cy; /* the SR_CY bit, values 0, 1. */
int32_t sr_ov; /* the SR_OV bit (in the sign bit only) */
uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */
uint32_t esr; /* Exception supervisor register */
uint32_t evbar; /* Exception vector base address register */
@@ -245,8 +245,8 @@ typedef struct CPUArchState {
uint32_t fpcsr; /* Float register */
float_status fp_status;
target_ulong lock_addr;
target_ulong lock_value;
uint32_t lock_addr;
uint32_t lock_value;
uint32_t dflag; /* In delay slot (boolean) */
target/openrisc/fpu_helper.c
+4 -4
View File
@@ -146,10 +146,10 @@ uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a,
#define FLOAT_CMP(name, impl) \
target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint32_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint64_t fdt0, uint64_t fdt1) \
{ return float64_ ## impl(fdt0, fdt1, &env->fp_status); } \
target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t fdt0, uint32_t fdt1) \
{ return float32_ ## impl(fdt0, fdt1, &env->fp_status); }
@@ -160,13 +160,13 @@ FLOAT_CMP(un, unordered_quiet)
#undef FLOAT_CMP
#define FLOAT_UCMP(name, expr) \
target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint32_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint64_t fdt0, uint64_t fdt1) \
{ \
FloatRelation r = float64_compare_quiet(fdt0, fdt1, &env->fp_status); \
return expr; \
} \
target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t fdt0, uint32_t fdt1) \
{ \
FloatRelation r = float32_compare_quiet(fdt0, fdt1, &env->fp_status); \
target/openrisc/helper.h
+4 -4
View File
@@ -47,8 +47,8 @@ FOP_CALC(rem)
#undef FOP_CALC
#define FOP_CMP(op) \
DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, tl, env, i32, i32) \
DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, i32, env, i32, i32) \
DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, i32, env, i64, i64)
FOP_CMP(eq)
FOP_CMP(lt)
FOP_CMP(le)
@@ -62,5 +62,5 @@ FOP_CMP(ult)
DEF_HELPER_FLAGS_1(rfe, 0, void, env)
/* sys */
DEF_HELPER_FLAGS_3(mtspr, 0, void, env, tl, tl)
DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl)
DEF_HELPER_FLAGS_3(mtspr, 0, void, env, i32, i32)
DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, i32, env, i32, i32)
target/openrisc/machine.c
+8 -8
View File
@@ -72,14 +72,14 @@ static const VMStateDescription vmstate_env = {
.version_id = 6,
.minimum_version_id = 6,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32),
VMSTATE_UINTTL(pc, CPUOpenRISCState),
VMSTATE_UINTTL(ppc, CPUOpenRISCState),
VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState),
VMSTATE_UINTTL(lock_addr, CPUOpenRISCState),
VMSTATE_UINTTL(lock_value, CPUOpenRISCState),
VMSTATE_UINTTL(epcr, CPUOpenRISCState),
VMSTATE_UINTTL(eear, CPUOpenRISCState),
VMSTATE_UINT32_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32),
VMSTATE_UINT32(pc, CPUOpenRISCState),
VMSTATE_UINT32(ppc, CPUOpenRISCState),
VMSTATE_UINT32(jmp_pc, CPUOpenRISCState),
VMSTATE_UINT32(lock_addr, CPUOpenRISCState),
VMSTATE_UINT32(lock_value, CPUOpenRISCState),
VMSTATE_UINT32(epcr, CPUOpenRISCState),
VMSTATE_UINT32(eear, CPUOpenRISCState),
/* Save the architecture value of the SR, not the internally
expanded version. Since this architecture value does not
target/openrisc/sys_helper.c
+2 -3
View File
@@ -40,7 +40,7 @@ static inline bool is_user(CPUOpenRISCState *env)
#endif
}
void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
void HELPER(mtspr)(CPUOpenRISCState *env, uint32_t spr, uint32_t rb)
{
OpenRISCCPU *cpu = env_archcpu(env);
#ifndef CONFIG_USER_ONLY
@@ -213,8 +213,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
#endif
}
target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
target_ulong spr)
uint32_t HELPER(mfspr)(CPUOpenRISCState *env, uint32_t rd, uint32_t spr)
{
OpenRISCCPU *cpu = env_archcpu(env);
#ifndef CONFIG_USER_ONLY
target/openrisc/translate.c
+199 -192
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