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Force correct evaluation order in a a == b != c condition.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4358 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
2008-05-06 14:45:30 +00:00
parent c7b76a0ae3
commit 57d69a91c4
1 changed files with 1 additions and 1 deletions
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hw/arm_gic.c
+1 -1
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@@ -62,7 +62,7 @@ typedef struct gic_irq_state
#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
#define GIC_TEST_LEVEL(irq, cm) (s->irq_state[irq].level & (cm)) != 0
#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger