izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging

Browse Source 
virtio,pc,pci: features, cleanups, fixes

vhost-user-snd support
x2APIC mode with TCG support
CXL update to r3.1

fixes, cleanups all over the place.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# -----BEGIN PGP SIGNATURE-----
#
# iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmXMoXUPHG1zdEByZWRo
# YXQuY29tAAoJECgfDbjSjVRpFtMIAKUKD0hzJrwOyPo4xsRUMbsB3ehIsJsMKfOK
# w+JWzTaojAG8ENPelWBdL2sEIs5U73VOchjLqHbH2m5sz6GJ13214amvdU/fYc8+
# /dU2ZKoAmaR5L1ovKO/fq07y/J6DrITZ5tosy2i84Xa8EnsL4j3wEPNVWsDi7dna
# mvXUICSOOoJQ4O2YhSruKCQ8qIgF1/0Oi3u/rcrW3alSs8VQlrtQXxl6k+LbYqek
# +Fytco3jMRHPvQ+GYUIwGuHjN15ghArcvbsV0GIa+24BPY5h7YbDYGbfasePT5OK
# zDz51jitkoyDrQr+OzwOEe/X5+dVGhayRXfMtU5Qm53IE3y61qc=
# =K4b1
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 14 Feb 2024 11:18:13 GMT
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (60 commits)
  MAINTAINERS: Switch to my Enfabrica email
  virtio-gpu-rutabaga.c: override resource_destroy method
  virtio-gpu.c: add resource_destroy class method
  hw/display/virtio-gpu.c: use reset_bh class method
  hw/smbios: Fix port connector option validation
  hw/smbios: Fix OEM strings table option validation
  virtio-gpu: Correct virgl_renderer_resource_get_info() error check
  hw/cxl: Standardize all references on CXL r3.1 and minor updates
  hw/cxl: Update mailbox status registers.
  hw/cxl: Update RAS Capability Definitions for version 3.
  hw/cxl: Update link register definitions.
  hw/cxl: Update HDM Decoder capability to version 3
  tests/acpi: Update DSDT.cxl to reflect change _STA return value.
  hw/i386: Fix _STA return value for ACPI0017
  tests/acpi: Allow update of DSDT.cxl
  hw/mem/cxl_type3: Fix potential divide by zero reported by coverity
  hw/cxl: Pass NULL for a NULL MemoryRegionOps
  hw/cxl: Pass CXLComponentState to cache_mem_ops
  hw/cxl/device: read from register values in mdev_reg_read()
  hw/cxl/mbox: Remove dead code
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2024-02-14 15:45:52 +00:00
parent 708322660e 1dd6954c3f
commit 5767815218
84 changed files with 2003 additions and 1909 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+16 -3
View File
@@ -2289,8 +2289,9 @@ L: virtio-fs@lists.linux.dev
virtio-input
M: Gerd Hoffmann <kraxel@redhat.com>
S: Odd Fixes
F: hw/input/vhost-user-input.c
F: docs/system/devices/vhost-user-input.rst
F: hw/input/virtio-input*.c
F: hw/virtio/vhost-user-input.c
F: include/hw/virtio/virtio-input.h
F: contrib/vhost-user-input/*
@@ -2319,6 +2320,12 @@ F: include/sysemu/rng*.h
F: backends/rng*.c
F: tests/qtest/virtio-rng-test.c
vhost-user-stubs
M: Alex Bennée <alex.bennee@linaro.org>
S: Maintained
F: hw/virtio/vhost-user-base.c
F: hw/virtio/vhost-user-device*
vhost-user-rng
M: Mathieu Poirier <mathieu.poirier@linaro.org>
S: Supported
@@ -2336,6 +2343,13 @@ F: hw/virtio/vhost-user-gpio*
F: include/hw/virtio/vhost-user-gpio.h
F: tests/qtest/libqos/virtio-gpio.*
vhost-user-snd
M: Alex Bennée <alex.bennee@linaro.org>
R: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
S: Maintained
F: hw/virtio/vhost-user-snd*
F: include/hw/virtio/vhost-user-snd.h
vhost-user-scmi
R: mzamazal@redhat.com
S: Supported
@@ -2556,7 +2570,7 @@ F: include/hw/virtio/virtio-gpu.h
F: docs/system/devices/virtio-gpu.rst
vhost-user-blk
M: Raphael Norwitz <raphael.s.norwitz@gmail.com>
M: Raphael Norwitz <raphael@enfabrica.net>
S: Maintained
F: contrib/vhost-user-blk/
F: contrib/vhost-user-scsi/
@@ -3623,7 +3637,6 @@ F: tests/uefi-test-tools/
VT-d Emulation
M: Michael S. Tsirkin <mst@redhat.com>
M: Peter Xu <peterx@redhat.com>
R: Jason Wang <jasowang@redhat.com>
S: Supported
F: hw/i386/intel_iommu.c
contrib/vhost-user-gpu/virgl.c
+3 -3
View File
@@ -327,7 +327,7 @@ virgl_get_resource_info_modifiers(uint32_t resource_id,
#ifdef VIRGL_RENDERER_RESOURCE_INFO_EXT_VERSION
struct virgl_renderer_resource_info_ext info_ext;
ret = virgl_renderer_resource_get_info_ext(resource_id, &info_ext);
if (ret < 0) {
if (ret) {
return ret;
}
@@ -335,7 +335,7 @@ virgl_get_resource_info_modifiers(uint32_t resource_id,
*modifiers = info_ext.modifiers;
#else
ret = virgl_renderer_resource_get_info(resource_id, info);
if (ret < 0) {
if (ret) {
return ret;
}
@@ -372,7 +372,7 @@ virgl_cmd_set_scanout(VuGpu *g,
uint64_t modifiers = 0;
ret = virgl_get_resource_info_modifiers(ss.resource_id, &info,
&modifiers);
if (ret == -1) {
if (ret) {
g_critical("%s: illegal resource specified %d\n",
__func__, ss.resource_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
docs/devel/migration/main.rst
+4 -2
View File
@@ -431,10 +431,10 @@ data doesn't match the stored device data well; it allows an
intermediate temporary structure to be populated with migration
data and then transferred to the main structure.
If you use memory API functions that update memory layout outside
If you use memory or portio_list API functions that update memory layout outside
initialization (i.e., in response to a guest action), this is a strong
indication that you need to call these functions in a ``post_load`` callback.
Examples of such memory API functions are:
Examples of such API functions are:
- memory_region_add_subregion()
- memory_region_del_subregion()
@@ -443,6 +443,8 @@ Examples of such memory API functions are:
- memory_region_set_enabled()
- memory_region_set_address()
- memory_region_set_alias_offset()
- portio_list_set_address()
- portio_list_set_enabled()
Iterative device migration
--------------------------
docs/interop/vhost-user.rst
+3 -3
View File
@@ -148,9 +148,9 @@ Vring descriptor indices for packed virtqueues
A vring address description
^^^^^^^^^^^^^^^^^^^^^^^^^^^
+-------+-------+------+------------+------+-----------+-----+
| index | flags | size | descriptor | used | available | log |
+-------+-------+------+------------+------+-----------+-----+
+-------+-------+------------+------+-----------+-----+
| index | flags | descriptor | used | available | log |
+-------+-------+------------+------+-----------+-----+
:index: a 32-bit vring index
docs/system/device-emulation.rst
+1
View File
@@ -94,6 +94,7 @@ Emulated Devices
devices/virtio-gpu.rst
devices/virtio-pmem.rst
devices/virtio-snd.rst
devices/vhost-user-input.rst
devices/vhost-user-rng.rst
devices/canokey.rst
devices/usb-u2f.rst
docs/system/devices/cxl.rst
+1 -2
View File
@@ -411,5 +411,4 @@ References
- Consortium website for specifications etc:
http://www.computeexpresslink.org
- Compute Express link Revision 2 specification, October 2020
- CEDT CFMWS & QTG _DSM ECN May 2021
- Compute Express Link (CXL) Specification, Revision 3.1, August 2023
docs/system/devices/vhost-user-input.rst
+45
View File
@@ -0,0 +1,45 @@
.. _vhost_user_input:
QEMU vhost-user-input - Input emulation
=======================================
This document describes the setup and usage of the Virtio input device.
The Virtio input device is a paravirtualized device for input events.
Description
-----------
The vhost-user-input device implementation was designed to work with a daemon
polling on input devices and passes input events to the guest.
QEMU provides a backend implementation in contrib/vhost-user-input.
Linux kernel support
--------------------
Virtio input requires a guest Linux kernel built with the
``CONFIG_VIRTIO_INPUT`` option.
Examples
--------
The backend daemon should be started first:
::
host# vhost-user-input --socket-path=input.sock \
--evdev-path=/dev/input/event17
The QEMU invocation needs to create a chardev socket to communicate with the
backend daemon and access the VirtIO queues with the guest over the
:ref:`shared memory <shared_memory_object>`.
::
host# qemu-system \
-chardev socket,path=/tmp/input.sock,id=mouse0 \
-device vhost-user-input-pci,chardev=mouse0 \
-m 4096 \
-object memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on \
-numa node,memdev=mem \
...
docs/system/devices/vhost-user-rng.rst
+2
View File
@@ -1,3 +1,5 @@
.. _vhost_user_rng:
QEMU vhost-user-rng - RNG emulation
===================================
docs/system/devices/vhost-user.rst
+71 -1
View File
@@ -8,13 +8,81 @@ outside of QEMU itself. To do this there are a number of things
required.
vhost-user device
===================
=================
These are simple stub devices that ensure the VirtIO device is visible
to the guest. The code is mostly boilerplate although each device has
a ``chardev`` option which specifies the ID of the ``--chardev``
device that connects via a socket to the vhost-user *daemon*.
Each device will have an virtio-mmio and virtio-pci variant. See your
platform details for what sort of virtio bus to use.
.. list-table:: vhost-user devices
:widths: 20 20 60
:header-rows: 1
* - Device
- Type
- Notes
* - vhost-user-blk
- Block storage
- See contrib/vhost-user-blk
* - vhost-user-fs
- File based storage driver
- See https://gitlab.com/virtio-fs/virtiofsd
* - vhost-user-gpio
- Proxy gpio pins to host
- See https://github.com/rust-vmm/vhost-device
* - vhost-user-gpu
- GPU driver
- See contrib/vhost-user-gpu
* - vhost-user-i2c
- Proxy i2c devices to host
- See https://github.com/rust-vmm/vhost-device
* - vhost-user-input
- Generic input driver
- :ref:`vhost_user_input`
* - vhost-user-rng
- Entropy driver
- :ref:`vhost_user_rng`
* - vhost-user-scmi
- System Control and Management Interface
- See https://github.com/rust-vmm/vhost-device
* - vhost-user-snd
- Audio device
- See https://github.com/rust-vmm/vhost-device/staging
* - vhost-user-scsi
- SCSI based storage
- See contrib/vhost-user-scsi
* - vhost-user-vsock
- Socket based communication
- See https://github.com/rust-vmm/vhost-device
The referenced *daemons* are not exhaustive, any conforming backend
implementing the device and using the vhost-user protocol should work.
vhost-user-device
^^^^^^^^^^^^^^^^^
The vhost-user-device is a generic development device intended for
expert use while developing new backends. The user needs to specify
all the required parameters including:
- Device ``virtio-id``
- The ``num_vqs`` it needs and their ``vq_size``
- The ``config_size`` if needed
.. note::
To prevent user confusion you cannot currently instantiate
vhost-user-device without first patching out::
/* Reason: stop inexperienced users confusing themselves */
dc->user_creatable = false;
in ``vhost-user-device.c`` and ``vhost-user-device-pci.c`` file and
rebuilding.
vhost-user daemon
=================
@@ -23,6 +91,8 @@ following the :ref:`vhost_user_proto`. There are a number of daemons
that can be built when enabled by the project although any daemon that
meets the specification for a given device can be used.
.. _shared_memory_object:
Shared memory object
====================
hw/arm/smmu-common.c
+2
View File
@@ -675,6 +675,8 @@ static void smmu_base_reset_hold(Object *obj)
{
SMMUState *s = ARM_SMMU(obj);
memset(s->smmu_pcibus_by_bus_num, 0, sizeof(s->smmu_pcibus_by_bus_num));
g_hash_table_remove_all(s->configs);
g_hash_table_remove_all(s->iotlb);
}
hw/block/fdc-internal.h
-4
View File
@@ -25,8 +25,6 @@
#ifndef HW_BLOCK_FDC_INTERNAL_H
#define HW_BLOCK_FDC_INTERNAL_H
#include "exec/memory.h"
#include "exec/ioport.h"
#include "hw/block/block.h"
#include "hw/block/fdc.h"
#include "qapi/qapi-types-block.h"
@@ -92,7 +90,6 @@ typedef struct FDrive {
} FDrive;
struct FDCtrl {
MemoryRegion iomem;
qemu_irq irq;
/* Controller state */
QEMUTimer *result_timer;
@@ -140,7 +137,6 @@ struct FDCtrl {
/* Timers state */
uint8_t timer0;
uint8_t timer1;
PortioList portio_list;
};
extern const FDFormat fd_formats[];
hw/block/fdc-isa.c
+17 -1
View File
@@ -42,6 +42,7 @@
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "sysemu/sysemu.h"
#include "exec/ioport.h"
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
@@ -60,6 +61,7 @@ struct FDCtrlISABus {
uint32_t irq;
uint32_t dma;
struct FDCtrl state;
PortioList portio_list;
int32_t bootindexA;
int32_t bootindexB;
};
@@ -91,7 +93,7 @@ static void isabus_fdc_realize(DeviceState *dev, Error **errp)
FDCtrl *fdctrl = &isa->state;
Error *err = NULL;
isa_register_portio_list(isadev, &fdctrl->portio_list,
isa_register_portio_list(isadev, &isa->portio_list,
isa->iobase, fdc_portio_list, fdctrl,
"fdc");
@@ -190,6 +192,20 @@ static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
return dev;
}
void isa_fdc_set_iobase(ISADevice *fdc, hwaddr iobase)
{
FDCtrlISABus *isa = ISA_FDC(fdc);
fdc->ioport_id = iobase;
isa->iobase = iobase;
portio_list_set_address(&isa->portio_list, isa->iobase);
}
void isa_fdc_set_enabled(ISADevice *fdc, bool enabled)
{
portio_list_set_enabled(&ISA_FDC(fdc)->portio_list, enabled);
}
int cmos_get_fd_drive_type(FloppyDriveType fd0)
{
int val;
hw/block/fdc-sysbus.c
+4 -2
View File
@@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qom/object.h"
#include "exec/memory.h"
#include "hw/sysbus.h"
#include "hw/block/fdc.h"
#include "migration/vmstate.h"
@@ -52,6 +53,7 @@ struct FDCtrlSysBus {
/*< public >*/
struct FDCtrl state;
MemoryRegion iomem;
};
static uint64_t fdctrl_read_mem(void *opaque, hwaddr reg, unsigned ize)
@@ -146,11 +148,11 @@ static void sysbus_fdc_common_instance_init(Object *obj)
qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
memory_region_init_io(&fdctrl->iomem, obj,
memory_region_init_io(&sys->iomem, obj,
sbdc->use_strict_io ? &fdctrl_mem_strict_ops
: &fdctrl_mem_ops,
fdctrl, "fdc", 0x08);
sysbus_init_mmio(sbd, &fdctrl->iomem);
sysbus_init_mmio(sbd, &sys->iomem);
sysbus_init_irq(sbd, &fdctrl->irq);
qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
hw/char/parallel-isa.c
+14
View File
@@ -41,3 +41,17 @@ void parallel_hds_isa_init(ISABus *bus, int n)
}
}
}
void isa_parallel_set_iobase(ISADevice *parallel, hwaddr iobase)
{
ISAParallelState *s = ISA_PARALLEL(parallel);
parallel->ioport_id = iobase;
s->iobase = iobase;
portio_list_set_address(&s->portio_list, s->iobase);
}
void isa_parallel_set_enabled(ISADevice *parallel, bool enabled)
{
portio_list_set_enabled(&ISA_PARALLEL(parallel)->portio_list, enabled);
}
hw/char/parallel.c
+1 -1
View File
@@ -532,7 +532,7 @@ static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
s->status = dummy;
}
isa_register_portio_list(isadev, &s->portio_list, base,
isa_register_portio_list(isadev, &isa->portio_list, base,
(s->hw_driver
? &isa_parallel_portio_hw_list[0]
: &isa_parallel_portio_sw_list[0]),
hw/char/serial-isa.c
+14
View File
@@ -184,3 +184,17 @@ void serial_hds_isa_init(ISABus *bus, int from, int to)
}
}
}
void isa_serial_set_iobase(ISADevice *serial, hwaddr iobase)
{
ISASerialState *s = ISA_SERIAL(serial);
serial->ioport_id = iobase;
s->iobase = iobase;
memory_region_set_address(&s->state.io, s->iobase);
}
void isa_serial_set_enabled(ISADevice *serial, bool enabled)
{
memory_region_set_enabled(&ISA_SERIAL(serial)->state.io, enabled);
}
hw/cxl/cxl-cdat.c
+8 -3
View File
@@ -49,6 +49,7 @@ static void ct3_build_cdat(CDATObject *cdat, Error **errp)
g_autofree CDATTableHeader *cdat_header = NULL;
g_autofree CDATEntry *cdat_st = NULL;
uint8_t sum = 0;
uint8_t *hdr_buf;
int ent, i;
/* Use default table if fopen == NULL */
@@ -63,7 +64,7 @@ static void ct3_build_cdat(CDATObject *cdat, Error **errp)
cdat->built_buf_len = cdat->build_cdat_table(&cdat->built_buf,
cdat->private);
if (!cdat->built_buf_len) {
if (cdat->built_buf_len <= 0) {
/* Build later as not all data available yet */
cdat->to_update = true;
return;
@@ -95,8 +96,12 @@ static void ct3_build_cdat(CDATObject *cdat, Error **errp)
/* For now, no runtime updates */
cdat_header->sequence = 0;
cdat_header->length += sizeof(CDATTableHeader);
sum += cdat_header->revision + cdat_header->sequence +
cdat_header->length;
hdr_buf = (uint8_t *)cdat_header;
for (i = 0; i < sizeof(*cdat_header); i++) {
sum += hdr_buf[i];
}
/* Sum of all bytes including checksum must be 0 */
cdat_header->checksum = ~sum + 1;
hw/cxl/cxl-component-utils.c
+21 -12
View File
@@ -13,7 +13,7 @@
#include "hw/pci/pci.h"
#include "hw/cxl/cxl.h"
/* CXL r3.0 Section 8.2.4.19.1 CXL HDM Decoder Capability Register */
/* CXL r3.1 Section 8.2.4.20.1 CXL HDM Decoder Capability Register */
int cxl_decoder_count_enc(int count)
{
switch (count) {
@@ -160,11 +160,11 @@ static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
}
/*
* 8.2.3
* CXL r3.1 Section 8.2.3: Component Register Layout and Definition
* The access restrictions specified in Section 8.2.2 also apply to CXL 2.0
* Component Registers.
*
* 8.2.2
* CXL r3.1 Section 8.2.2: Accessing Component Registers
* • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial
* reads are not permitted.
* • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial
@@ -197,9 +197,9 @@ void cxl_component_register_block_init(Object *obj,
CXL2_COMPONENT_BLOCK_SIZE);
/* io registers controls link which we don't care about in QEMU */
memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io",
memory_region_init_io(&cregs->io, obj, NULL, NULL, ".io",
CXL2_COMPONENT_IO_REGION_SIZE);
memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs,
memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate,
".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE);
memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);
@@ -243,6 +243,14 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
POISON_ON_ERR_CAP, 0);
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0);
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0);
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0);
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
UIO_DECODER_COUNT, 0);
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 0);
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
SUPPORTED_COHERENCY_MODEL, 0); /* Unknown */
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,
HDM_DECODER_ENABLE, 0);
write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3;
@@ -300,7 +308,8 @@ void cxl_component_register_init_common(uint32_t *reg_state,
/* CXL Capability Header Register */
ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1);
ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1);
ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION,
CXL_CAPABILITY_VERSION);
ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1);
ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps);
@@ -317,24 +326,24 @@ void cxl_component_register_init_common(uint32_t *reg_state,
CXL_##reg##_REGISTERS_OFFSET); \
} while (0)
init_cap_reg(RAS, 2, 2);
init_cap_reg(RAS, 2, CXL_RAS_CAPABILITY_VERSION);
ras_init_common(reg_state, write_msk);
init_cap_reg(LINK, 4, 2);
init_cap_reg(LINK, 4, CXL_LINK_CAPABILITY_VERSION);
if (caps < 3) {
return;
}
init_cap_reg(HDM, 5, 1);
init_cap_reg(HDM, 5, CXL_HDM_CAPABILITY_VERSION);
hdm_init_common(reg_state, write_msk, type);
if (caps < 5) {
return;
}
init_cap_reg(EXTSEC, 6, 1);
init_cap_reg(SNOOP, 8, 1);
init_cap_reg(EXTSEC, 6, CXL_EXTSEC_CAP_VERSION);
init_cap_reg(SNOOP, 8, CXL_SNOOP_CAP_VERSION);
#undef init_cap_reg
}
@@ -459,7 +468,7 @@ void cxl_component_create_dvsec(CXLComponentState *cxl,
cxl->dvsec_offset += length;
}
/* CXL r3.0 Section 8.2.4.19.7 CXL HDM Decoder n Control Register */
/* CXL r3.1 Section 8.2.4.20.7 CXL HDM Decoder n Control Register */
uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
{
switch (iw) {
hw/cxl/cxl-device-utils.c
+21 -10
View File
@@ -13,7 +13,7 @@
/*
* Device registers have no restrictions per the spec, and so fall back to the
* default memory mapped register rules in 8.2:
* default memory mapped register rules in CXL r3.1 Section 8.2:
* Software shall use CXL.io Memory Read and Write to access memory mapped
* register defined in this section. Unless otherwise specified, software
* shall restrict the accesses width based on the following:
@@ -229,12 +229,9 @@ static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value,
static uint64_t mdev_reg_read(void *opaque, hwaddr offset, unsigned size)
{
uint64_t retval = 0;
CXLDeviceState *cxl_dstate = opaque;
retval = FIELD_DP64(retval, CXL_MEM_DEV_STS, MEDIA_STATUS, 1);
retval = FIELD_DP64(retval, CXL_MEM_DEV_STS, MBOX_READY, 1);
return retval;
return cxl_dstate->memdev_status;
}
static void ro_reg_write(void *opaque, hwaddr offset, uint64_t value,
@@ -369,9 +366,21 @@ static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
MSI_N, msi_n);
cxl_dstate->mbox_msi_n = msi_n;
ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
MBOX_READY_TIME, 0); /* Not reported */
ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
TYPE, 0); /* Inferred from class code */
}
static void memdev_reg_init_common(CXLDeviceState *cxl_dstate) { }
static void memdev_reg_init_common(CXLDeviceState *cxl_dstate)
{
uint64_t memdev_status_reg;
memdev_status_reg = FIELD_DP64(0, CXL_MEM_DEV_STS, MEDIA_STATUS, 1);
memdev_status_reg = FIELD_DP64(memdev_status_reg, CXL_MEM_DEV_STS,
MBOX_READY, 1);
cxl_dstate->memdev_status = memdev_status_reg;
}
void cxl_device_register_init_t3(CXLType3Dev *ct3d)
{
@@ -384,13 +393,15 @@ void cxl_device_register_init_t3(CXLType3Dev *ct3d)
ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1);
ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_COUNT, cap_count);
cxl_device_cap_init(cxl_dstate, DEVICE_STATUS, 1, 2);
cxl_device_cap_init(cxl_dstate, DEVICE_STATUS, 1,
CXL_DEVICE_STATUS_VERSION);
device_reg_init_common(cxl_dstate);
cxl_device_cap_init(cxl_dstate, MAILBOX, 2, 1);
cxl_device_cap_init(cxl_dstate, MAILBOX, 2, CXL_DEV_MAILBOX_VERSION);
mailbox_reg_init_common(cxl_dstate);
cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000, 1);
cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000,
CXL_MEM_DEV_STATUS_VERSION);
memdev_reg_init_common(cxl_dstate);
cxl_initialize_mailbox_t3(&ct3d->cci, DEVICE(ct3d),
hw/cxl/cxl-events.c
+1 -1
View File
@@ -204,7 +204,7 @@ CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds,
* record that will not be cleared when Clear Event Records is executed,
* the device shall return the Invalid Handle return code and shall not
* clear any of the specified event records."
* -- CXL 3.0 8.2.9.2.3
* -- CXL r3.1 Section 8.2.9.2.3: Clear Event Records (0101h)
*/
entry = cxl_event_get_head(log);
for (nr = 0; entry && nr < pl->nr_recs; nr++) {

Some files were not shown because too many files have changed in this diff Show More