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Merge tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu into staging

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Sixth RISC-V PR for QEMU 6.2

 - Fix build for riscv hosts
 - Soft code alphabetically

# gpg: Signature made Wed 17 Nov 2021 10:19:25 AM CET
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]

* tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu:
  meson.build: Merge riscv32 and riscv64 cpu family
  target/riscv: machine: Sort the .subsections

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2021-11-17 10:51:29 +01:00
parent 8d5fcb1990 c94c239496
commit 52cebbfc13
2 changed files with 56 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files
meson.build
+6
View File
@@ -59,6 +59,12 @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64',
'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64']
cpu = host_machine.cpu_family()
# Unify riscv* to a single family.
if cpu in ['riscv32', 'riscv64']
cpu = 'riscv'
endif
targetos = host_machine.system()
if cpu in ['x86', 'x86_64']
target/riscv/machine.c
+50 -50
View File
@@ -76,56 +76,6 @@ static bool hyper_needed(void *opaque)
return riscv_has_ext(env, RVH);
}
static bool vector_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
return riscv_has_ext(env, RVV);
}
static bool pointermasking_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
return riscv_has_ext(env, RVJ);
}
static const VMStateDescription vmstate_vector = {
.name = "cpu/vector",
.version_id = 1,
.minimum_version_id = 1,
.needed = vector_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
VMSTATE_UINTTL(env.vxrm, RISCVCPU),
VMSTATE_UINTTL(env.vxsat, RISCVCPU),
VMSTATE_UINTTL(env.vl, RISCVCPU),
VMSTATE_UINTTL(env.vstart, RISCVCPU),
VMSTATE_UINTTL(env.vtype, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_pointermasking = {
.name = "cpu/pointer_masking",
.version_id = 1,
.minimum_version_id = 1,
.needed = pointermasking_needed,
.fields = (VMStateField[]) {
VMSTATE_UINTTL(env.mmte, RISCVCPU),
VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
VMSTATE_UINTTL(env.spmmask, RISCVCPU),
VMSTATE_UINTTL(env.spmbase, RISCVCPU),
VMSTATE_UINTTL(env.upmmask, RISCVCPU),
VMSTATE_UINTTL(env.upmbase, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
.version_id = 1,
@@ -164,6 +114,56 @@ static const VMStateDescription vmstate_hyper = {
}
};
static bool vector_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
return riscv_has_ext(env, RVV);
}
static const VMStateDescription vmstate_vector = {
.name = "cpu/vector",
.version_id = 1,
.minimum_version_id = 1,
.needed = vector_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
VMSTATE_UINTTL(env.vxrm, RISCVCPU),
VMSTATE_UINTTL(env.vxsat, RISCVCPU),
VMSTATE_UINTTL(env.vl, RISCVCPU),
VMSTATE_UINTTL(env.vstart, RISCVCPU),
VMSTATE_UINTTL(env.vtype, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
static bool pointermasking_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
return riscv_has_ext(env, RVJ);
}
static const VMStateDescription vmstate_pointermasking = {
.name = "cpu/pointer_masking",
.version_id = 1,
.minimum_version_id = 1,
.needed = pointermasking_needed,
.fields = (VMStateField[]) {
VMSTATE_UINTTL(env.mmte, RISCVCPU),
VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
VMSTATE_UINTTL(env.spmmask, RISCVCPU),
VMSTATE_UINTTL(env.spmbase, RISCVCPU),
VMSTATE_UINTTL(env.upmmask, RISCVCPU),
VMSTATE_UINTTL(env.upmbase, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,