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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386/tcg: conversion of one byte opcodes to table-based decoder # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmY5z/QUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroP1YQf/WMAoB/lR31fzu/Uh36hF1Ke/NHNU # gefqKRAol6xJXxavKH8ym9QMlCTzrCLVt0e8RalZH76gLqYOjRhSLSSL+gUo5HEo # lsGSfkDAH2pHO0ZjQUkXcjJQQKkH+4+Et8xtyPc0qmq4uT1pqQZRgOeI/X/DIFNb # sMoKaRKfj+dB7TSp3qCSOp77RqL13f4QTP8mUQ4XIfzDDXdTX5n8WNLnyEIKjoar # ge4U6/KHjM35hAjCG9Av/zYQx0E084r2N2OEy0ESYNwswFZ8XYzTuL4SatN/Otf3 # F6eQZ7Q7n6lQbTA+k3J/jR9dxiSqVzFQnL1ePGoe9483UnxVavoWd0PSgw== # =jCyB # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 May 2024 11:53:40 PM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (26 commits) target/i386: remove duplicate prefix decoding target/i386: split legacy decoder into a separate function target/i386: decode x87 instructions in a separate function target/i386: remove now-converted opcodes from old decoder target/i386: port extensions of one-byte opcodes to new decoder target/i386: move BSWAP to new decoder target/i386: move remaining conditional operations to new decoder target/i386: merge and enlarge a few ranges for call to disas_insn_new target/i386: move C0-FF opcodes to new decoder (except for x87) target/i386: generalize gen_movl_seg_T0 target/i386: move 60-BF opcodes to new decoder target/i386: allow instructions with more than one immediate target/i386: extract gen_far_call/jmp, reordering temporaries target/i386: move 00-5F opcodes to new decoder target/i386: reintroduce debugging mechanism target/i386: cleanup *gen_eob* target/i386: clarify the "reg" argument of functions returning CCPrepare target/i386: do not use s->T0 and s->T1 as scratch registers for CCPrepare target/i386: extend cc_* when using them to compute flags target/i386: pull cc_op update to callers of gen_jmp_rel{,_csize} ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
@@ -81,6 +81,7 @@
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GlobalProperty pc_compat_9_0[] = {
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{ TYPE_X86_CPU, "guest-phys-bits", "0" },
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{ "sev-guest", "legacy-vm-type", "true" },
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{ TYPE_X86_CPU, "legacy-multi-node", "on" },
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};
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const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0);
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+10
-8
@@ -398,12 +398,9 @@ static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
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* 31:11 Reserved.
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* 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
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* ValidValues:
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* Value Description
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* 000b 1 node per processor.
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* 001b 2 nodes per processor.
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* 010b Reserved.
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* 011b 4 nodes per processor.
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* 111b-100b Reserved.
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* Value Description
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* 0h 1 node per processor.
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* 7h-1h Reserved.
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* 7:0 NodeId: Node ID. Read-only. Reset: XXh.
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*
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* NOTE: Hardware reserves 3 bits for number of nodes per processor.
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@@ -412,8 +409,12 @@ static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
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* NodeId is combination of node and socket_id which is already decoded
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* in apic_id. Just use it by shifting.
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*/
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*ecx = ((topo_info->dies_per_pkg - 1) << 8) |
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((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
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if (cpu->legacy_multi_node) {
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*ecx = ((topo_info->dies_per_pkg - 1) << 8) |
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((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
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} else {
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*ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF;
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}
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*edx = 0;
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}
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@@ -8084,6 +8085,7 @@ static Property x86_cpu_properties[] = {
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* own cache information (see x86_cpu_load_def()).
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*/
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DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
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DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false),
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DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false),
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/*
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@@ -1994,6 +1994,12 @@ struct ArchCPU {
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*/
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bool legacy_cache;
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/* Compatibility bits for old machine types.
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* If true decode the CPUID Function 0x8000001E_ECX to support multiple
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* nodes per processor
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*/
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bool legacy_multi_node;
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/* Compatibility bits for old machine types: */
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bool enable_cpuid_0xb;
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@@ -207,15 +207,4 @@ DEF_HELPER_1(emms, void, env)
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#define SHIFT 2
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#include "tcg/ops_sse_header.h.inc"
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DEF_HELPER_3(rclb, tl, env, tl, tl)
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DEF_HELPER_3(rclw, tl, env, tl, tl)
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DEF_HELPER_3(rcll, tl, env, tl, tl)
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DEF_HELPER_3(rcrb, tl, env, tl, tl)
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DEF_HELPER_3(rcrw, tl, env, tl, tl)
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DEF_HELPER_3(rcrl, tl, env, tl, tl)
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#ifdef TARGET_X86_64
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DEF_HELPER_3(rclq, tl, env, tl, tl)
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DEF_HELPER_3(rcrq, tl, env, tl, tl)
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#endif
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DEF_HELPER_1(rdrand, tl, env)
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File diff suppressed because it is too large
Load Diff
@@ -47,7 +47,9 @@ typedef enum X86OpType {
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X86_TYPE_Y, /* string destination */
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/* Custom */
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X86_TYPE_EM, /* modrm byte selects an ALU memory operand */
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X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */
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X86_TYPE_I_unsigned, /* Immediate, zero-extended */
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X86_TYPE_2op, /* 2-operand RMW instruction */
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X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
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X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
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@@ -88,6 +90,7 @@ typedef enum X86OpSize {
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X86_SIZE_x, /* 128/256-bit, based on operand size */
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X86_SIZE_y, /* 32/64-bit, based on operand size */
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X86_SIZE_z, /* 16-bit for 16-bit operand size, else 32-bit */
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X86_SIZE_z_f64, /* 32-bit for 32-bit operand size or 64-bit mode, else 16-bit */
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/* Custom */
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X86_SIZE_d64,
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@@ -104,6 +107,7 @@ typedef enum X86CPUIDFeature {
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X86_FEAT_AVX2,
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X86_FEAT_BMI1,
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X86_FEAT_BMI2,
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X86_FEAT_CMOV,
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X86_FEAT_CMPCCXADD,
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X86_FEAT_F16C,
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X86_FEAT_FMA,
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@@ -165,6 +169,8 @@ typedef enum X86InsnSpecial {
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/* Always locked if it has a memory operand (XCHG) */
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X86_SPECIAL_Locked,
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/* Do not apply segment base to effective address */
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X86_SPECIAL_NoSeg,
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/*
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* Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 bits
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* (and writeback zero-extends it to 64 bits if applicable). PREFIX_DATA
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@@ -271,16 +277,23 @@ typedef struct X86DecodedOp {
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bool has_ea;
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int offset; /* For MMX and SSE */
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/*
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* This field is used internally by macros OP0_PTR/OP1_PTR/OP2_PTR,
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* do not access directly!
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*/
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TCGv_ptr v_ptr;
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union {
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target_ulong imm;
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/*
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* This field is used internally by macros OP0_PTR/OP1_PTR/OP2_PTR,
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* do not access directly!
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*/
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TCGv_ptr v_ptr;
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};
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} X86DecodedOp;
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struct X86DecodedInsn {
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X86OpEntry e;
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X86DecodedOp op[3];
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/*
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* Rightmost immediate, for convenience since most instructions have
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* one (and also for 4-operand instructions).
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*/
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target_ulong immediate;
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AddressParts mem;
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+1583
-12
File diff suppressed because it is too large
Load Diff
@@ -29,22 +29,6 @@
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//#define DEBUG_MULDIV
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/* modulo 9 table */
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static const uint8_t rclb_table[32] = {
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0, 1, 2, 3, 4, 5, 6, 7,
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8, 0, 1, 2, 3, 4, 5, 6,
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7, 8, 0, 1, 2, 3, 4, 5,
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6, 7, 8, 0, 1, 2, 3, 4,
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};
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/* modulo 17 table */
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static const uint8_t rclw_table[32] = {
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0, 1, 2, 3, 4, 5, 6, 7,
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 0, 1, 2, 3, 4, 5, 6,
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7, 8, 9, 10, 11, 12, 13, 14,
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};
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/* division, flags are undefined */
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void helper_divb_AL(CPUX86State *env, target_ulong t0)
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@@ -447,24 +431,6 @@ target_ulong helper_pext(target_ulong src, target_ulong mask)
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return dest;
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}
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#define SHIFT 0
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#include "shift_helper_template.h.inc"
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#undef SHIFT
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#define SHIFT 1
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#include "shift_helper_template.h.inc"
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#undef SHIFT
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#define SHIFT 2
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#include "shift_helper_template.h.inc"
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#undef SHIFT
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#ifdef TARGET_X86_64
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#define SHIFT 3
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#include "shift_helper_template.h.inc"
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#undef SHIFT
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#endif
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/* Test that BIT is enabled in CR4. If not, raise an illegal opcode
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exception. This reduces the requirements for rare CR4 bits being
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mapped into HFLAGS. */
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@@ -1,108 +0,0 @@
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/*
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* x86 shift helpers
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#define DATA_BITS (1 << (3 + SHIFT))
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#define SHIFT_MASK (DATA_BITS - 1)
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#if DATA_BITS <= 32
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#define SHIFT1_MASK 0x1f
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#else
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#define SHIFT1_MASK 0x3f
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#endif
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#if DATA_BITS == 8
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#define SUFFIX b
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#define DATA_MASK 0xff
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#elif DATA_BITS == 16
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#define SUFFIX w
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#define DATA_MASK 0xffff
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#elif DATA_BITS == 32
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#define SUFFIX l
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#define DATA_MASK 0xffffffff
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#elif DATA_BITS == 64
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#define SUFFIX q
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#define DATA_MASK 0xffffffffffffffffULL
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#else
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#error unhandled operand size
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#endif
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target_ulong glue(helper_rcl, SUFFIX)(CPUX86State *env, target_ulong t0,
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target_ulong t1)
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{
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int count, eflags;
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target_ulong src;
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target_long res;
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count = t1 & SHIFT1_MASK;
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#if DATA_BITS == 16
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count = rclw_table[count];
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#elif DATA_BITS == 8
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count = rclb_table[count];
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#endif
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if (count) {
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eflags = env->cc_src;
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t0 &= DATA_MASK;
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src = t0;
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res = (t0 << count) | ((target_ulong)(eflags & CC_C) << (count - 1));
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if (count > 1) {
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res |= t0 >> (DATA_BITS + 1 - count);
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}
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t0 = res;
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env->cc_src = (eflags & ~(CC_C | CC_O)) |
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(lshift(src ^ t0, 11 - (DATA_BITS - 1)) & CC_O) |
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((src >> (DATA_BITS - count)) & CC_C);
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}
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return t0;
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}
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target_ulong glue(helper_rcr, SUFFIX)(CPUX86State *env, target_ulong t0,
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target_ulong t1)
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{
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int count, eflags;
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target_ulong src;
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target_long res;
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count = t1 & SHIFT1_MASK;
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#if DATA_BITS == 16
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count = rclw_table[count];
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#elif DATA_BITS == 8
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count = rclb_table[count];
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#endif
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if (count) {
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eflags = env->cc_src;
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t0 &= DATA_MASK;
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src = t0;
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res = (t0 >> count) |
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((target_ulong)(eflags & CC_C) << (DATA_BITS - count));
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if (count > 1) {
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res |= t0 << (DATA_BITS + 1 - count);
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}
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t0 = res;
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env->cc_src = (eflags & ~(CC_C | CC_O)) |
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(lshift(src ^ t0, 11 - (DATA_BITS - 1)) & CC_O) |
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((src >> (count - 1)) & CC_C);
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}
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return t0;
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}
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#undef DATA_BITS
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#undef SHIFT_MASK
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#undef SHIFT1_MASK
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#undef DATA_TYPE
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#undef DATA_MASK
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#undef SUFFIX
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+776
-3005
File diff suppressed because it is too large
Load Diff
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