Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging

Hexagon bug fixes and test improvements

1) Fixes a bug in qemu-hexagon
2) Fixes a bug in a test case
3) Adds reference file for float_convd test case

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmLnDw8ACgkQewJE+xLe
# RCIwVgf/bPvX2cbmAECNJ5y/Galy5n1sMttwyrlwR4VVf8jQbCESDritIiWVn5gw
# zvM1Ba4MGH6YSkr/1Om7kBkEp+hqX5eDpUW1Q1qFa6SyF3oIu25MVBq8fkrrU1+f
# kJcTKdW7eQ2TfGupUW6Dj/QdoVknBnoIPk7T9lkT/qtmn9YwDyrqDSFnJTgVbrAv
# W/gGFzT4HskKuJ5Fy0wzeca7BfR9fl8rencuqyUfDehLk5hbjiR9vGG9Xt1mJyae
# LRFaqdy4/OsZHAVad4fnSOvYJp7EN4fR7zmkRfPi7kTNwnQ6ewBOZnUUoK3VQ0bk
# TViBl7kNjxdcO4DFjBeLYJUGxVUoww==
# =a+hi
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 31 Jul 2022 04:23:59 PM PDT
# gpg:                using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5  9AB4 7B02 44FB 12DE 4422

* tag 'pull-hex-20220731' of https://github.com/quic/qemu:
  Hexagon (tests/tcg/hexagon) reference file for float_convd
  Hexagon (tests/tcg/hexagon) Fix alignment in load_unpack.c
  Hexagon (target/hexagon) make VyV operands use a unique temp

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hexagon/gen_tcg_funcs.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+##  Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -164,7 +164,9 @@ def genptr_decl(f, tag, regtype, regid, regno):
                 (regtype, regid, regno))
             f.write("    const intptr_t %s%sV_off =\n" % \
                 (regtype, regid))
-            if (hex_common.is_tmp_result(tag)):
+            if (regid == "y"):
+                f.write("        offsetof(CPUHexagonState, vtmp);\n")
+            elif (hex_common.is_tmp_result(tag)):
                 f.write("        ctx_tmp_vreg_off(ctx, %s%sN, 1, true);\n" % \
                     (regtype, regid))
             else:
@@ -379,9 +381,6 @@ def genptr_src_read(f, tag, regtype, regid):
             f.write("        vreg_src_off(ctx, %s%sN),\n" % \
                              (regtype, regid))
             f.write("        sizeof(MMVector), sizeof(MMVector));\n")
-            if (not hex_common.skip_qemu_helper(tag)):
-                f.write("    tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
-                                 (regtype, regid, regtype, regid))
         else:
             print("Bad register parse: ", regtype, regid)
     elif (regtype == "Q"):

tests/tcg/hexagon/hvx_misc.c

@@ -498,6 +498,49 @@ static void test_vsubuwsat_dv(void)
     check_output_w(__LINE__, 2);
 }
 
+static void test_vshuff(void)
+{
+    /* Test that vshuff works when the two operands are the same register */
+    const uint32_t splat = 0x089be55c;
+    const uint32_t shuff = 0x454fa926;
+    MMVector v0, v1;
+
+    memset(expect, 0x12, sizeof(MMVector));
+    memset(output, 0x34, sizeof(MMVector));
+
+    asm volatile("v25 = vsplat(%0)\n\t"
+                 "vshuff(v25, v25, %1)\n\t"
+                 "vmem(%2 + #0) = v25\n\t"
+                 : /* no outputs */
+                 : "r"(splat), "r"(shuff), "r"(output)
+                 : "v25", "memory");
+
+    /*
+     * The semantics of Hexagon are the operands are pass-by-value, so create
+     * two copies of the vsplat result.
+     */
+    for (int i = 0; i < MAX_VEC_SIZE_BYTES / 4; i++) {
+        v0.uw[i] = splat;
+        v1.uw[i] = splat;
+    }
+    /* Do the vshuff operation */
+    for (int offset = 1; offset < MAX_VEC_SIZE_BYTES; offset <<= 1) {
+        if (shuff & offset) {
+            for (int k = 0; k < MAX_VEC_SIZE_BYTES; k++) {
+                if (!(k & offset)) {
+                    uint8_t tmp = v0.ub[k];
+                    v0.ub[k] = v1.ub[k + offset];
+                    v1.ub[k + offset] = tmp;
+                }
+            }
+        }
+    }
+    /* Put the result in the expect buffer for verification */
+    expect[0] = v1;
+
+    check_output_b(__LINE__, 1);
+}
+
 int main()
 {
     init_buffers();
@@ -533,6 +576,8 @@ int main()
     test_vadduwsat();
     test_vsubuwsat_dv();
 
+    test_vshuff();
+
     puts(err ? "FAIL" : "PASS");
     return err ? 1 : 0;
 }

tests/tcg/hexagon/load_unpack.c

@@ -245,7 +245,7 @@ TEST_pr(loadbsw4_pr, long long, S, 4, 0x0000ff000000ff00LL,
  */
 #define BxW_LOAD_pbr(SZ, RES, PTR) \
     __asm__( \
-        "r4 = #(1 << (16 - 3))\n\t" \
+        "r4 = #(1 << (16 - 4))\n\t" \
         "m0 = r4\n\t" \
         "%0 = mem" #SZ "(%1++m0:brev)\n\t" \
         : "=r"(RES), "+r"(PTR) \
@@ -273,15 +273,15 @@ void test_##NAME(void) \
 }
 
 TEST_pbr(loadbzw2_pbr, int, Z, 0x00000000,
-    0x00020081, 0x00060085, 0x00040083, 0x00080087)
+    0x00020081, 0x000a0089, 0x00060085, 0x000e008d)
 TEST_pbr(loadbsw2_pbr, int, S, 0x0000ff00,
-    0x00020081, 0x00060085, 0x00040083, 0x00080087)
+    0x00020081, 0x000aff89, 0x0006ff85, 0x000eff8d)
 TEST_pbr(loadbzw4_pbr, long long, Z, 0x0000000000000000LL,
-    0x0004008300020081LL, 0x0008008700060085LL,
-    0x0006008500040083LL, 0x000a008900080087LL)
+    0x0004008300020081LL, 0x000c008b000a0089LL,
+    0x0008008700060085LL, 0x0010008f000e008dLL)
 TEST_pbr(loadbsw4_pbr, long long, S, 0x0000ff000000ff00LL,
-    0x0004008300020081LL, 0x0008008700060085LL,
-    0x0006008500040083LL, 0x000a008900080087LL)
+    0x0004008300020081LL, 0x000cff8b000aff89LL,
+    0x0008ff870006ff85LL, 0x0010ff8f000eff8dLL)
 
 /*
  ****************************************************************************