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hw/arm/allwinner-r40: add SDRAM controller device
Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner R40 SDRAM controller. This driver only support 256M, 512M and 1024M memory now. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
qianfan Zhao
committed by
Peter Maydell
Peter Maydell
parent
a954543092
commit
4a52ef61d9
+19
-2
@@ -31,6 +31,7 @@
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#include "hw/loader.h"
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#include "sysemu/sysemu.h"
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#include "hw/arm/allwinner-r40.h"
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#include "hw/misc/allwinner-r40-dramc.h"
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/* Memory map */
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const hwaddr allwinner_r40_memmap[] = {
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@@ -53,6 +54,9 @@ const hwaddr allwinner_r40_memmap[] = {
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[AW_R40_DEV_UART6] = 0x01c29800,
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[AW_R40_DEV_UART7] = 0x01c29c00,
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[AW_R40_DEV_TWI0] = 0x01c2ac00,
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[AW_R40_DEV_DRAMCOM] = 0x01c62000,
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[AW_R40_DEV_DRAMCTL] = 0x01c63000,
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[AW_R40_DEV_DRAMPHY] = 0x01c65000,
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[AW_R40_DEV_GIC_DIST] = 0x01c81000,
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[AW_R40_DEV_GIC_CPU] = 0x01c82000,
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[AW_R40_DEV_GIC_HYP] = 0x01c84000,
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@@ -129,8 +133,6 @@ static struct AwR40Unimplemented r40_unimplemented[] = {
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{ "gpu", 0x01c40000, 64 * KiB },
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{ "gmac", 0x01c50000, 64 * KiB },
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{ "hstmr", 0x01c60000, 4 * KiB },
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{ "dram-com", 0x01c62000, 4 * KiB },
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{ "dram-ctl", 0x01c63000, 4 * KiB },
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{ "tcon-top", 0x01c70000, 4 * KiB },
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{ "lcd0", 0x01c71000, 4 * KiB },
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{ "lcd1", 0x01c72000, 4 * KiB },
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@@ -273,6 +275,12 @@ static void allwinner_r40_init(Object *obj)
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}
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object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
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object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_R40_DRAMC);
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object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
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"ram-addr");
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object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
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"ram-size");
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}
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static void allwinner_r40_realize(DeviceState *dev, Error **errp)
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@@ -425,6 +433,15 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
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qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI0));
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/* DRAMC */
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sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0,
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s->memmap[AW_R40_DEV_DRAMCOM]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1,
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s->memmap[AW_R40_DEV_DRAMCTL]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2,
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s->memmap[AW_R40_DEV_DRAMPHY]);
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/* Unimplemented devices */
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for (i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
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create_unimplemented_device(r40_unimplemented[i].device_name,
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@@ -85,6 +85,13 @@ static void bpim2u_init(MachineState *machine)
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object_property_set_int(OBJECT(r40), "clk1-freq", 24 * 1000 * 1000,
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&error_abort);
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/* DRAMC */
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r40->ram_size = machine->ram_size / MiB;
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object_property_set_uint(OBJECT(r40), "ram-addr",
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r40->memmap[AW_R40_DEV_SDRAM], &error_abort);
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object_property_set_int(OBJECT(r40), "ram-size",
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r40->ram_size, &error_abort);
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/* Mark R40 object realized */
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qdev_realize(DEVICE(r40), NULL, &error_abort);
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File diff suppressed because it is too large
Load Diff
@@ -45,6 +45,7 @@ softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c
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softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-sysctrl.c'))
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softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.c'))
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softmmu_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40-ccu.c'))
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softmmu_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40-dramc.c'))
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softmmu_ss.add(when: 'CONFIG_AXP2XX_PMU', if_true: files('axp2xx.c'))
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softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
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softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c'))
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@@ -15,6 +15,20 @@ allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write
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allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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# allwinner-r40-dramc.c
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allwinner_r40_dramc_detect_cells_disable(void) "Disable detect cells"
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allwinner_r40_dramc_detect_cells_enable(void) "Enable detect cells"
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allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) "DRAM layout: row_bits %d, bank_bits %d, col_bits %d"
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allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) "offset 0x%" PRIx64 " row %d bank %d col %d"
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allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 ""
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allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 ""
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allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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# allwinner-sid.c
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allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
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@@ -26,6 +26,7 @@
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#include "hw/intc/arm_gic.h"
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#include "hw/sd/allwinner-sdhost.h"
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#include "hw/misc/allwinner-r40-ccu.h"
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#include "hw/misc/allwinner-r40-dramc.h"
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#include "hw/i2c/allwinner-i2c.h"
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#include "target/arm/cpu.h"
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#include "sysemu/block-backend.h"
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@@ -54,7 +55,10 @@ enum {
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AW_R40_DEV_GIC_CPU,
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AW_R40_DEV_GIC_HYP,
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AW_R40_DEV_GIC_VCPU,
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AW_R40_DEV_SDRAM
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AW_R40_DEV_SDRAM,
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AW_R40_DEV_DRAMCOM,
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AW_R40_DEV_DRAMCTL,
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AW_R40_DEV_DRAMPHY,
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};
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#define AW_R40_NUM_CPUS (4)
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@@ -86,11 +90,18 @@ struct AwR40State {
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DeviceState parent_obj;
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/*< public >*/
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/** Physical base address for start of RAM */
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hwaddr ram_addr;
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/** Total RAM size in megabytes */
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uint32_t ram_size;
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ARMCPU cpus[AW_R40_NUM_CPUS];
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const hwaddr *memmap;
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AwA10PITState timer;
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AwSdHostState mmc[AW_R40_NUM_MMCS];
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AwR40ClockCtlState ccu;
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AwR40DramCtlState dramc;
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AWI2CState i2c0;
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GICState gic;
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MemoryRegion sram_a1;
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@@ -0,0 +1,108 @@
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/*
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* Allwinner R40 SDRAM Controller emulation
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*
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* Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_MISC_ALLWINNER_R40_DRAMC_H
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#define HW_MISC_ALLWINNER_R40_DRAMC_H
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#include "qom/object.h"
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#include "hw/sysbus.h"
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#include "exec/hwaddr.h"
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/**
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* Constants
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* @{
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*/
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/** Highest register address used by DRAMCOM module */
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#define AW_R40_DRAMCOM_REGS_MAXADDR (0x804)
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/** Total number of known DRAMCOM registers */
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#define AW_R40_DRAMCOM_REGS_NUM (AW_R40_DRAMCOM_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** Highest register address used by DRAMCTL module */
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#define AW_R40_DRAMCTL_REGS_MAXADDR (0x88c)
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/** Total number of known DRAMCTL registers */
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#define AW_R40_DRAMCTL_REGS_NUM (AW_R40_DRAMCTL_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** Highest register address used by DRAMPHY module */
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#define AW_R40_DRAMPHY_REGS_MAXADDR (0x4)
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/** Total number of known DRAMPHY registers */
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#define AW_R40_DRAMPHY_REGS_NUM (AW_R40_DRAMPHY_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** @} */
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/**
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* Object model
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* @{
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*/
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#define TYPE_AW_R40_DRAMC "allwinner-r40-dramc"
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OBJECT_DECLARE_SIMPLE_TYPE(AwR40DramCtlState, AW_R40_DRAMC)
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/** @} */
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/**
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* Allwinner R40 SDRAM Controller object instance state.
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*/
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struct AwR40DramCtlState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/** Physical base address for start of RAM */
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hwaddr ram_addr;
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/** Total RAM size in megabytes */
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uint32_t ram_size;
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uint8_t set_row_bits;
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uint8_t set_bank_bits;
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uint8_t set_col_bits;
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/**
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* @name Memory Regions
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* @{
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*/
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MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
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MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
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MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
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MemoryRegion dram_high; /**< The high 1G dram for dualrank detect */
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MemoryRegion detect_cells; /**< DRAM memory cells for auto detect */
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/** @} */
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/**
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* @name Hardware Registers
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* @{
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*/
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uint32_t dramcom[AW_R40_DRAMCOM_REGS_NUM]; /**< DRAMCOM registers */
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uint32_t dramctl[AW_R40_DRAMCTL_REGS_NUM]; /**< DRAMCTL registers */
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uint32_t dramphy[AW_R40_DRAMPHY_REGS_NUM] ;/**< DRAMPHY registers */
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/** @} */
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};
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#endif /* HW_MISC_ALLWINNER_R40_DRAMC_H */
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