izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-09-2020' into staging

Browse Source 
MIPS queue for June 9th, 2020

# gpg: Signature made Tue 09 Jun 2020 17:18:59 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full]
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-jun-09-2020:
  target/mips: Enable hardware page table walker and CMGCR features for P5600
  target/mips: Add Loongson-3 CPU definition
  target/mips: fpu: Refactor conversion from ieee to mips exception flags
  target/mips: fpu: Name better paired-single variables
  target/mips: fpu: Remove now unused FLOAT_RINT macro
  target/mips: fpu: Demacro RINT.<D|S>
  target/mips: fpu: Remove now unused FLOAT_CLASS macro
  target/mips: fpu: Demacro CLASS.<D|S>
  target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros
  target/mips: fpu: Demacro NMSUB.<D|S|PS>
  target/mips: fpu: Demacro NMADD.<D|S|PS>
  target/mips: fpu: Demacro MSUB.<D|S|PS>
  target/mips: fpu: Demacro MADD.<D|S|PS>
  target/mips: fpu: Remove now unused macro FLOAT_BINOP
  target/mips: fpu: Demacro DIV.<D|S|PS>
  target/mips: fpu: Demacro MUL.<D|S|PS>
  target/mips: fpu: Demacro SUB.<D|S|PS>
  target/mips: fpu: Demacro ADD.<D|S|PS>
  mailmap: Change email address of Stefan Brankovic
  mailmap: Change email address of Filip Bozuta

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2020-06-11 13:07:34 +01:00
parent c291aca63d 6db06115d2
commit 470dd165d1
10 changed files with 651 additions and 251 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.mailmap
+2
View File
@@ -45,12 +45,14 @@ Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <amarkovic@wavecomp.com>
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <arikalo@wavecomp.com>
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <aleksandar.rikalo@rt-rk.com>
Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
Filip Bozuta <filip.bozuta@syrmia.com> <filip.bozuta@rt-rk.com.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>
Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>
Philippe Mathieu-Daudé <philmd@redhat.com> <f4bug@amsat.org>
Stefan Brankovic <stefan.brankovic@syrmia.com> <stefan.brankovic@rt-rk.com.com>
Yongbok Kim <yongbok.kim@mips.com> <yongbok.kim@imgtec.com>
# Also list preferred name forms where people have changed their
target/mips/Makefile.objs
+1 -1
View File
@@ -1,6 +1,6 @@
obj-y += translate.o cpu.o gdbstub.o helper.o
obj-y += op_helper.o cp0_helper.o fpu_helper.o
obj-y += dsp_helper.o lmi_helper.o msa_helper.o
obj-y += dsp_helper.o lmmi_helper.o msa_helper.o
obj-$(CONFIG_SOFTMMU) += mips-semi.o
obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o
obj-$(CONFIG_KVM) += kvm.o
target/mips/cpu.h
+30 -2
View File
@@ -198,8 +198,8 @@ typedef struct mips_def_t mips_def_t;
* 3 Config3 WatchLo3 WatchHi
* 4 Config4 WatchLo4 WatchHi
* 5 Config5 WatchLo5 WatchHi
* 6 WatchLo6 WatchHi
* 7 WatchLo7 WatchHi
* 6 Config6 WatchLo6 WatchHi
* 7 Config7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
@@ -940,7 +940,35 @@ struct CPUMIPSState {
#define CP0C5_UFR 2
#define CP0C5_NFExists 0
int32_t CP0_Config6;
int32_t CP0_Config6_rw_bitmask;
#define CP0C6_BPPASS 31
#define CP0C6_KPOS 24
#define CP0C6_KE 23
#define CP0C6_VTLBONLY 22
#define CP0C6_LASX 21
#define CP0C6_SSEN 20
#define CP0C6_DISDRTIME 19
#define CP0C6_PIXNUEN 18
#define CP0C6_SCRAND 17
#define CP0C6_LLEXCEN 16
#define CP0C6_DISVC 15
#define CP0C6_VCLRU 14
#define CP0C6_DCLRU 13
#define CP0C6_PIXUEN 12
#define CP0C6_DISBLKLYEN 11
#define CP0C6_UMEMUALEN 10
#define CP0C6_SFBEN 8
#define CP0C6_FLTINT 7
#define CP0C6_VLTINT 6
#define CP0C6_DISBTB 5
#define CP0C6_STPREFCTL 2
#define CP0C6_INSTPREF 1
#define CP0C6_DATAPREF 0
int32_t CP0_Config7;
int64_t CP0_Config7_rw_bitmask;
#define CP0C7_NAPCGEN 2
#define CP0C7_UNIMUEN 1
#define CP0C7_VFPUCGEN 0
uint64_t CP0_LLAddr;
uint64_t CP0_MAAR[MIPS_MAAR_MAX];
int32_t CP0_MAARI;
target/mips/fpu_helper.c
+446 -198
View File
File diff suppressed because it is too large Load Diff
target/mips/internal.h
+2 -1
View File
@@ -36,7 +36,9 @@ struct mips_def_t {
int32_t CP0_Config5;
int32_t CP0_Config5_rw_bitmask;
int32_t CP0_Config6;
int32_t CP0_Config6_rw_bitmask;
int32_t CP0_Config7;
int32_t CP0_Config7_rw_bitmask;
target_ulong CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
int32_t SYNCI_Step;
@@ -224,7 +226,6 @@ uint32_t float_class_s(uint32_t arg, float_status *fst);
uint64_t float_class_d(uint64_t arg, float_status *fst);
extern unsigned int ieee_rm[];
int ieee_ex_to_mips(int xcpt);
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
static inline void restore_rounding_mode(CPUMIPSState *env)
target/mips/lmi_helper.c → target/mips/lmmi_helper.c
View File
target/mips/mips-defs.h
+25 -20
View File
@@ -15,7 +15,7 @@
* ------------------------------------------------
*/
/*
* bits 0-31: MIPS base instruction sets
* bits 0-23: MIPS base instruction sets
*/
#define ISA_MIPS1 0x0000000000000001ULL
#define ISA_MIPS2 0x0000000000000002ULL
@@ -34,30 +34,33 @@
#define ISA_MIPS64R6 0x0000000000004000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
* bits 32-47: MIPS ASEs
* bits 24-39: MIPS ASEs
*/
#define ASE_MIPS16 0x0000000100000000ULL
#define ASE_MIPS3D 0x0000000200000000ULL
#define ASE_MDMX 0x0000000400000000ULL
#define ASE_DSP 0x0000000800000000ULL
#define ASE_DSP_R2 0x0000001000000000ULL
#define ASE_DSP_R3 0x0000002000000000ULL
#define ASE_MT 0x0000004000000000ULL
#define ASE_SMARTMIPS 0x0000008000000000ULL
#define ASE_MICROMIPS 0x0000010000000000ULL
#define ASE_MSA 0x0000020000000000ULL
#define ASE_MIPS16 0x0000000001000000ULL
#define ASE_MIPS3D 0x0000000002000000ULL
#define ASE_MDMX 0x0000000004000000ULL
#define ASE_DSP 0x0000000008000000ULL
#define ASE_DSP_R2 0x0000000010000000ULL
#define ASE_DSP_R3 0x0000000020000000ULL
#define ASE_MT 0x0000000040000000ULL
#define ASE_SMARTMIPS 0x0000000080000000ULL
#define ASE_MICROMIPS 0x0000000100000000ULL
#define ASE_MSA 0x0000000200000000ULL
/*
* bits 48-55: vendor-specific base instruction sets
* bits 40-51: vendor-specific base instruction sets
*/
#define INSN_LOONGSON2E 0x0001000000000000ULL
#define INSN_LOONGSON2F 0x0002000000000000ULL
#define INSN_VR54XX 0x0004000000000000ULL
#define INSN_R5900 0x0008000000000000ULL
#define INSN_VR54XX 0x0000010000000000ULL
#define INSN_R5900 0x0000020000000000ULL
#define INSN_LOONGSON2E 0x0000040000000000ULL
#define INSN_LOONGSON2F 0x0000080000000000ULL
#define INSN_LOONGSON3A 0x0000100000000000ULL
/*
* bits 56-63: vendor-specific ASEs
* bits 52-63: vendor-specific ASEs
*/
#define ASE_MMI 0x0100000000000000ULL
#define ASE_MXU 0x0200000000000000ULL
#define ASE_MMI 0x0010000000000000ULL
#define ASE_MXU 0x0020000000000000ULL
#define ASE_LMMI 0x0040000000000000ULL
#define ASE_LEXT 0x0080000000000000ULL
/* MIPS CPU defines. */
#define CPU_MIPS1 (ISA_MIPS1)
@@ -94,6 +97,8 @@
/* Wave Computing: "nanoMIPS" */
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A)
/*
* Strictly follow the architecture standard:
* - Disallow "special" instruction handling for PMON/SPIM.
target/mips/msa_helper.c
+52 -25
View File
@@ -5419,54 +5419,81 @@ static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
#define CLEAR_IS_INEXACT 2
#define RECIPROCAL_INEXACT 4
static inline int ieee_to_mips_xcpt_msa(int ieee_xcpt)
{
int mips_xcpt = 0;
if (ieee_xcpt & float_flag_invalid) {
mips_xcpt |= FP_INVALID;
}
if (ieee_xcpt & float_flag_overflow) {
mips_xcpt |= FP_OVERFLOW;
}
if (ieee_xcpt & float_flag_underflow) {
mips_xcpt |= FP_UNDERFLOW;
}
if (ieee_xcpt & float_flag_divbyzero) {
mips_xcpt |= FP_DIV0;
}
if (ieee_xcpt & float_flag_inexact) {
mips_xcpt |= FP_INEXACT;
}
return mips_xcpt;
}
static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
{
int ieee_ex;
int c;
int ieee_exception_flags;
int mips_exception_flags = 0;
int cause;
int enable;
ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
ieee_exception_flags = get_float_exception_flags(
&env->active_tc.msa_fp_status);
/* QEMU softfloat does not signal all underflow cases */
if (denormal) {
ieee_ex |= float_flag_underflow;
ieee_exception_flags |= float_flag_underflow;
}
if (ieee_exception_flags) {
mips_exception_flags = ieee_to_mips_xcpt_msa(ieee_exception_flags);
}
c = ieee_ex_to_mips(ieee_ex);
enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
/* Set Inexact (I) when flushing inputs to zero */
if ((ieee_ex & float_flag_input_denormal) &&
if ((ieee_exception_flags & float_flag_input_denormal) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
if (action & CLEAR_IS_INEXACT) {
c &= ~FP_INEXACT;
mips_exception_flags &= ~FP_INEXACT;
} else {
c |= FP_INEXACT;
mips_exception_flags |= FP_INEXACT;
}
}
/* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
if ((ieee_ex & float_flag_output_denormal) &&
if ((ieee_exception_flags & float_flag_output_denormal) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
c |= FP_INEXACT;
mips_exception_flags |= FP_INEXACT;
if (action & CLEAR_FS_UNDERFLOW) {
c &= ~FP_UNDERFLOW;
mips_exception_flags &= ~FP_UNDERFLOW;
} else {
c |= FP_UNDERFLOW;
mips_exception_flags |= FP_UNDERFLOW;
}
}
/* Set Inexact (I) when Overflow (O) is not enabled */
if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
c |= FP_INEXACT;
if ((mips_exception_flags & FP_OVERFLOW) != 0 &&
(enable & FP_OVERFLOW) == 0) {
mips_exception_flags |= FP_INEXACT;
}
/* Clear Exact Underflow when Underflow (U) is not enabled */
if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
(c & FP_INEXACT) == 0) {
c &= ~FP_UNDERFLOW;
if ((mips_exception_flags & FP_UNDERFLOW) != 0 &&
(enable & FP_UNDERFLOW) == 0 &&
(mips_exception_flags & FP_INEXACT) == 0) {
mips_exception_flags &= ~FP_UNDERFLOW;
}
/*
@@ -5474,11 +5501,11 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
* divide by zero
*/
if ((action & RECIPROCAL_INEXACT) &&
(c & (FP_INVALID | FP_DIV0)) == 0) {
c = FP_INEXACT;
(mips_exception_flags & (FP_INVALID | FP_DIV0)) == 0) {
mips_exception_flags = FP_INEXACT;
}
cause = c & enable; /* all current enabled exceptions */
cause = mips_exception_flags & enable; /* all current enabled exceptions */
if (cause == 0) {
/*
@@ -5486,7 +5513,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
* with all current exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
(GET_FP_CAUSE(env->active_tc.msacsr) | c));
(GET_FP_CAUSE(env->active_tc.msacsr) | mips_exception_flags));
} else {
/* Current exceptions are enabled */
if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
@@ -5495,11 +5522,11 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
* with all enabled exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
(GET_FP_CAUSE(env->active_tc.msacsr) | c));
(GET_FP_CAUSE(env->active_tc.msacsr) | mips_exception_flags));
}
}
return c;
return mips_exception_flags;
}
static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
target/mips/translate.c
+2
View File
@@ -31206,7 +31206,9 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Config5 = env->cpu_model->CP0_Config5;
env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
env->CP0_Config6 = env->cpu_model->CP0_Config6;
env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
env->CP0_Config7 = env->cpu_model->CP0_Config7;
env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
<< env->cpu_model->CP0_LLAddr_shift;
env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
target/mips/translate_init.inc.c
+91 -4
View File
@@ -366,7 +366,7 @@ const mips_def_t mips_defs[] =
},
{
/* FIXME:
* Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL
* Config3: VZ, CTXTC, CDMM, TL
* Config4: MMUExtDef
* Config5: MRP
* FIR(FCR0): Has2008
@@ -380,10 +380,11 @@ const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_FP),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
(1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
(1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) |
(1 << CP0C3_VInt),
(1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
(1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
(0x1c << CP0C4_KScrExist),
.CP0_Config4_rw_bitmask = 0,
@@ -801,6 +802,92 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_LOONGSON2F,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "Loongson-3A1000",
.CP0_PRid = 0x6305,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
(MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
(3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
(3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
(3 << CP0C2_SA),
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
.CP0_LLAddr_rw_bitmask = 0,
.SYNCI_Step = 32,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x74D8FFFF,
.CP0_PageGrain = (1 << CP0PG_ELPA),
.CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
(0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
(0x1 << FCR0_D) | (0x1 << FCR0_S),
.CP1_fcr31 = 0,
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 48,
.insn_flags = CPU_LOONGSON3A,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "Loongson-3A4000",
.CP0_PRid = 0x14C000,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
(MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
(2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
(2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
(15 << CP0C2_SA),
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
(1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
.CP0_Config4_rw_bitmask = 0,
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
.CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
(1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
(1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
.CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
(1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
(1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
.CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
(1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
(1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
(1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
(1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
(1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
(1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
(1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
(1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
(1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
(3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
(1 << CP0C6_DATAPREF),
.CP0_Config7 = 0,
.CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
(1 << CP0C7_VFPUCGEN),
.CP0_LLAddr_rw_bitmask = 1,
.SYNCI_Step = 16,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x7DDBFFFF,
.CP0_PageGrain = (1 << CP0PG_ELPA),
.CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
(1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
(0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
(0x1 << FCR0_D) | (0x1 << FCR0_S),
.CP1_fcr31 = 0,
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 48,
.PABITS = 48,
.insn_flags = CPU_LOONGSON3A,
.mmu_type = MMU_TYPE_R4000,
},
{
/* A generic CPU providing MIPS64 DSP R2 ASE features.
FIXME: Eventually this should be replaced by a real CPU model. */