mirror of
https://github.com/izzy2lost/xemu.git
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Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into staging
Hexagon update # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmRmgQgACgkQewJE+xLe # RCJLtAf8C/0kQRa4mjnbsztXuFyca53UxAv3BSBEDla4ZcMfFBoVJsGB3OP7IPXd # KBQpkLyJAVye9idex5xqdp9nIfoGKDTsc6YtCfGujZ17cDpzLRDpHdUTex8PcZYK # wpfM3hoVJsYRBMsojZ4OaxatjFQ+FWzrIH6FcgH086Q8TH4w9dZLNEJzHC4lOj0s # 7qOuw2tgm+vOVlzsk/fv6/YD/BTeZTON3jgTPvAnvdRLb/482UpM9JkJ8E4rbte3 # Ss5PUK8QTQHU0yamspGy/PfsYxiptM+jIWGd836fAGzwF12Ug27mSc1enndRtQVW # pQTdnOnWuuRzOwEpd7x3xh9upACm4g== # =1CyJ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 May 2023 12:48:24 PM PDT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230518-1' of https://github.com/quic/qemu: (44 commits) Hexagon (linux-user/hexagon): handle breakpoints Hexagon (gdbstub): add HVX support Hexagon (gdbstub): fix p3:0 read and write via stub Hexagon: add core gdbstub xml data for LLDB gdbstub: add test for untimely stop-reply packets gdbstub: only send stop-reply packets when allowed to Remove test_vshuff from hvx_misc tests Hexagon (decode): look for pkts with multiple insns at the same slot Hexagon (iclass): update J4_hintjumpr slot constraints Hexagon: append eflags to unknown cpu model string Hexagon: list available CPUs with `-cpu help` Hexagon (target/hexagon/*.py): raise exception on reg parsing error target/hexagon: fix = vs. == mishap Hexagon (target/hexagon) Additional instructions handled by idef-parser Hexagon (target/hexagon) Move items to DisasContext Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext Hexagon (target/hexagon) Move pred_written to DisasContext Hexagon (target/hexagon) Move new_pred_value to DisasContext Hexagon (target/hexagon) Move new_value to DisasContext Hexagon (target/hexagon) Make special new_value for USR ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
@@ -225,6 +225,7 @@ F: tests/tcg/hexagon/
|
||||
F: disas/hexagon.c
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||||
F: configs/targets/hexagon-linux-user/default.mak
|
||||
F: docker/dockerfiles/debian-hexagon-cross.docker
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||||
F: gdb-xml/hexagon*.xml
|
||||
|
||||
Hexagon idef-parser
|
||||
M: Alessandro Di Federico <ale@rev.ng>
|
||||
|
||||
@@ -1 +1,2 @@
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||||
TARGET_ARCH=hexagon
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||||
TARGET_XML_FILES=gdb-xml/hexagon-core.xml gdb-xml/hexagon-hvx.xml
|
||||
|
||||
@@ -1269,7 +1269,7 @@ fi
|
||||
: ${cross_cc_armeb="$cross_cc_arm"}
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: ${cross_cc_cflags_armeb="-mbig-endian"}
|
||||
: ${cross_cc_hexagon="hexagon-unknown-linux-musl-clang"}
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: ${cross_cc_cflags_hexagon="-mv67 -O2 -static"}
|
||||
: ${cross_cc_cflags_hexagon="-mv73 -O2 -static"}
|
||||
: ${cross_cc_cflags_i386="-m32"}
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||||
: ${cross_cc_cflags_ppc="-m32 -mbig-endian"}
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: ${cross_cc_cflags_ppc64="-m64 -mbig-endian"}
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||||
|
||||
@@ -0,0 +1,84 @@
|
||||
<?xml version="1.0"?>
|
||||
<!--
|
||||
Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
|
||||
This work is licensed under the terms of the GNU GPL, version 2 or
|
||||
(at your option) any later version. See the COPYING file in the
|
||||
top-level directory.
|
||||
|
||||
Note: this file is intended to be use with LLDB, so it contains fields
|
||||
that may be unknown to GDB. For more information on such fields, please
|
||||
see:
|
||||
https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb-gdb-remote.txt#L738-L860
|
||||
https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp#L4275-L4335
|
||||
-->
|
||||
|
||||
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
|
||||
<feature name="org.gnu.gdb.hexagon.core">
|
||||
|
||||
<reg name="r00" altname="r0" bitsize="32" offset="0" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="0" generic="r00"/>
|
||||
<reg name="r01" altname="r1" bitsize="32" offset="4" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="1" generic="r01"/>
|
||||
<reg name="r02" altname="r2" bitsize="32" offset="8" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="2" generic="r02"/>
|
||||
<reg name="r03" altname="r3" bitsize="32" offset="12" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="3" generic="r03"/>
|
||||
<reg name="r04" altname="r4" bitsize="32" offset="16" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="4" generic="r04"/>
|
||||
<reg name="r05" altname="r5" bitsize="32" offset="20" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="5" generic="r05"/>
|
||||
<reg name="r06" altname="r6" bitsize="32" offset="24" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="6" generic="r06"/>
|
||||
<reg name="r07" altname="r7" bitsize="32" offset="28" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="7" generic="r07"/>
|
||||
<reg name="r08" altname="r8" bitsize="32" offset="32" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="8" generic="r08"/>
|
||||
<reg name="r09" altname="r9" bitsize="32" offset="36" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="9" generic="r09"/>
|
||||
<reg name="r10" bitsize="32" offset="40" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="10"/>
|
||||
<reg name="r11" bitsize="32" offset="44" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="11"/>
|
||||
<reg name="r12" bitsize="32" offset="48" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="12"/>
|
||||
<reg name="r13" bitsize="32" offset="52" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="13"/>
|
||||
<reg name="r14" bitsize="32" offset="56" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="14"/>
|
||||
<reg name="r15" bitsize="32" offset="60" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="15"/>
|
||||
<reg name="r16" bitsize="32" offset="64" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="16"/>
|
||||
<reg name="r17" bitsize="32" offset="68" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="17"/>
|
||||
<reg name="r18" bitsize="32" offset="72" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="18"/>
|
||||
<reg name="r19" bitsize="32" offset="76" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="19"/>
|
||||
<reg name="r20" bitsize="32" offset="80" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="20"/>
|
||||
<reg name="r21" bitsize="32" offset="84" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="21"/>
|
||||
<reg name="r22" bitsize="32" offset="88" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="22"/>
|
||||
<reg name="r23" bitsize="32" offset="92" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="23"/>
|
||||
<reg name="r24" bitsize="32" offset="96" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="24"/>
|
||||
<reg name="r25" bitsize="32" offset="100" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="25"/>
|
||||
<reg name="r26" bitsize="32" offset="104" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="26"/>
|
||||
<reg name="r27" bitsize="32" offset="108" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="27"/>
|
||||
<reg name="r28" bitsize="32" offset="112" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="28"/>
|
||||
<reg name="r29" altname="sp" bitsize="32" offset="116" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="29" generic="sp"/>
|
||||
<reg name="r30" altname="fp" bitsize="32" offset="120" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="30" generic="fp"/>
|
||||
<reg name="r31" altname="ra" bitsize="32" offset="124" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="31" generic="ra"/>
|
||||
<reg name="sa0" bitsize="32" offset="128" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="32"/>
|
||||
<reg name="lc0" bitsize="32" offset="132" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="33"/>
|
||||
<reg name="sa1" bitsize="32" offset="136" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="34"/>
|
||||
<reg name="lc1" bitsize="32" offset="140" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="35"/>
|
||||
<reg name="p3_0" bitsize="32" offset="144" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="36"/>
|
||||
<reg name="c5" bitsize="32" offset="148" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="37"/>
|
||||
<reg name="m0" bitsize="32" offset="152" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="38"/>
|
||||
<reg name="m1" bitsize="32" offset="156" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="39"/>
|
||||
<reg name="usr" bitsize="32" offset="160" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="40"/>
|
||||
<reg name="pc" bitsize="32" offset="164" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="41" generic="pc"/>
|
||||
<reg name="ugp" bitsize="32" offset="168" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="42"/>
|
||||
<reg name="gp" bitsize="32" offset="172" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="43"/>
|
||||
<reg name="cs0" bitsize="32" offset="176" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="44"/>
|
||||
<reg name="cs1" bitsize="32" offset="180" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="45"/>
|
||||
<reg name="upcyclelo" bitsize="32" offset="184" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="46"/>
|
||||
<reg name="upcyclehi" bitsize="32" offset="188" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="47"/>
|
||||
<reg name="framelimit" bitsize="32" offset="192" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="48"/>
|
||||
<reg name="framekey" bitsize="32" offset="196" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="49"/>
|
||||
<reg name="pktcountlo" bitsize="32" offset="200" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="50"/>
|
||||
<reg name="pktcounthi" bitsize="32" offset="204" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="51"/>
|
||||
<reg name="pkt_cnt" bitsize="32" offset="208" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="52"/>
|
||||
<reg name="insn_cnt" bitsize="32" offset="212" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="53"/>
|
||||
<reg name="hvx_cnt" bitsize="32" offset="216" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="54"/>
|
||||
<reg name="c23" bitsize="32" offset="220" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="55"/>
|
||||
<reg name="c24" bitsize="32" offset="224" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="56"/>
|
||||
<reg name="c25" bitsize="32" offset="228" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="57"/>
|
||||
<reg name="c26" bitsize="32" offset="232" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="58"/>
|
||||
<reg name="c27" bitsize="32" offset="236" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="59"/>
|
||||
<reg name="c28" bitsize="32" offset="240" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="60"/>
|
||||
<reg name="c29" bitsize="32" offset="244" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="61"/>
|
||||
<reg name="utimerlo" bitsize="32" offset="248" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="62"/>
|
||||
<reg name="utimerhi" bitsize="32" offset="252" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="63"/>
|
||||
|
||||
</feature>
|
||||
@@ -0,0 +1,96 @@
|
||||
<?xml version="1.0"?>
|
||||
<!--
|
||||
Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
|
||||
This work is licensed under the terms of the GNU GPL, version 2 or
|
||||
(at your option) any later version. See the COPYING file in the
|
||||
top-level directory.
|
||||
|
||||
Note: this file is intended to be use with LLDB, so it contains fields
|
||||
that may be unknown to GDB. For more information on such fields, please
|
||||
see:
|
||||
https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb-gdb-remote.txt#L738-L860
|
||||
https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp#L4275-L4335
|
||||
-->
|
||||
|
||||
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
|
||||
<feature name="org.gnu.gdb.hexagon.hvx">
|
||||
|
||||
<vector id="vud" type="uint64" count="16"/>
|
||||
<vector id="vd" type="int64" count="16"/>
|
||||
<vector id="vuw" type="uint32" count="32"/>
|
||||
<vector id="vw" type="int32" count="32"/>
|
||||
<vector id="vuh" type="uint16" count="64"/>
|
||||
<vector id="vh" type="int16" count="64"/>
|
||||
<vector id="vub" type="uint8" count="128"/>
|
||||
<vector id="vb" type="int8" count="128"/>
|
||||
<union id="hex_vec">
|
||||
<field name="ud" type="vud"/>
|
||||
<field name="d" type="vd"/>
|
||||
<field name="uw" type="vuw"/>
|
||||
<field name="w" type="vw"/>
|
||||
<field name="uh" type="vuh"/>
|
||||
<field name="h" type="vh"/>
|
||||
<field name="ub" type="vub"/>
|
||||
<field name="b" type="vb"/>
|
||||
</union>
|
||||
|
||||
<flags id="ui2" size="1">
|
||||
<field name="0" start="0" end="0"/>
|
||||
<field name="1" start="1" end="1"/>
|
||||
</flags>
|
||||
<flags id="ui4" size="1">
|
||||
<field name="0" start="0" end="0"/>
|
||||
<field name="1" start="1" end="1"/>
|
||||
<field name="2" start="2" end="2"/>
|
||||
<field name="3" start="3" end="3"/>
|
||||
</flags>
|
||||
<vector id="vpd" type="uint8" count="16"/>
|
||||
<vector id="vpw" type="ui4" count="32"/>
|
||||
<vector id="vph" type="ui2" count="64"/>
|
||||
<vector id="vpb" type="bool" count="128"/>
|
||||
<union id="hex_vec_pred">
|
||||
<field name="d" type="vpd"/>
|
||||
<field name="w" type="vpw"/>
|
||||
<field name="h" type="vph"/>
|
||||
<field name="b" type="vpb"/>
|
||||
</union>
|
||||
|
||||
<reg name="v0" bitsize="1024" offset="256" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="88"/>
|
||||
<reg name="v1" bitsize="1024" offset="384" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="89"/>
|
||||
<reg name="v2" bitsize="1024" offset="512" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="90"/>
|
||||
<reg name="v3" bitsize="1024" offset="640" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="91"/>
|
||||
<reg name="v4" bitsize="1024" offset="768" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="92"/>
|
||||
<reg name="v5" bitsize="1024" offset="896" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="93"/>
|
||||
<reg name="v6" bitsize="1024" offset="1024" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="94"/>
|
||||
<reg name="v7" bitsize="1024" offset="1152" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="95"/>
|
||||
<reg name="v8" bitsize="1024" offset="1280" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="96"/>
|
||||
<reg name="v9" bitsize="1024" offset="1408" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="97"/>
|
||||
<reg name="v10" bitsize="1024" offset="1536" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="98"/>
|
||||
<reg name="v11" bitsize="1024" offset="1664" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="99"/>
|
||||
<reg name="v12" bitsize="1024" offset="1792" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="100"/>
|
||||
<reg name="v13" bitsize="1024" offset="1920" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="101"/>
|
||||
<reg name="v14" bitsize="1024" offset="2048" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="102"/>
|
||||
<reg name="v15" bitsize="1024" offset="2176" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="103"/>
|
||||
<reg name="v16" bitsize="1024" offset="2304" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="104"/>
|
||||
<reg name="v17" bitsize="1024" offset="2432" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="105"/>
|
||||
<reg name="v18" bitsize="1024" offset="2560" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="106"/>
|
||||
<reg name="v19" bitsize="1024" offset="2688" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="107"/>
|
||||
<reg name="v20" bitsize="1024" offset="2816" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="108"/>
|
||||
<reg name="v21" bitsize="1024" offset="2944" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="109"/>
|
||||
<reg name="v22" bitsize="1024" offset="3072" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="110"/>
|
||||
<reg name="v23" bitsize="1024" offset="3200" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="111"/>
|
||||
<reg name="v24" bitsize="1024" offset="3328" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="112"/>
|
||||
<reg name="v25" bitsize="1024" offset="3456" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="113"/>
|
||||
<reg name="v26" bitsize="1024" offset="3584" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="114"/>
|
||||
<reg name="v27" bitsize="1024" offset="3712" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="115"/>
|
||||
<reg name="v28" bitsize="1024" offset="3840" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="116"/>
|
||||
<reg name="v29" bitsize="1024" offset="3968" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="117"/>
|
||||
<reg name="v30" bitsize="1024" offset="4096" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="118"/>
|
||||
<reg name="v31" bitsize="1024" offset="4224" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="119"/>
|
||||
<reg name="q0" bitsize="128" offset="4352" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="120"/>
|
||||
<reg name="q1" bitsize="128" offset="4368" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="121"/>
|
||||
<reg name="q2" bitsize="128" offset="4384" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="122"/>
|
||||
<reg name="q3" bitsize="128" offset="4400" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="123"/>
|
||||
|
||||
</feature>
|
||||
+28
-9
@@ -777,6 +777,10 @@ typedef void (*GdbCmdHandler)(GArray *params, void *user_ctx);
|
||||
/*
|
||||
* cmd_startswith -> cmd is compared using startswith
|
||||
*
|
||||
* allow_stop_reply -> true iff the gdbstub can respond to this command with a
|
||||
* "stop reply" packet. The list of commands that accept such response is
|
||||
* defined at the GDB Remote Serial Protocol documentation. see:
|
||||
* https://sourceware.org/gdb/onlinedocs/gdb/Stop-Reply-Packets.html#Stop-Reply-Packets.
|
||||
*
|
||||
* schema definitions:
|
||||
* Each schema parameter entry consists of 2 chars,
|
||||
@@ -802,6 +806,7 @@ typedef struct GdbCmdParseEntry {
|
||||
const char *cmd;
|
||||
bool cmd_startswith;
|
||||
const char *schema;
|
||||
bool allow_stop_reply;
|
||||
} GdbCmdParseEntry;
|
||||
|
||||
static inline int startswith(const char *string, const char *pattern)
|
||||
@@ -835,6 +840,7 @@ static int process_string_cmd(void *user_ctx, const char *data,
|
||||
}
|
||||
}
|
||||
|
||||
gdbserver_state.allow_stop_reply = cmd->allow_stop_reply;
|
||||
cmd->handler(params, user_ctx);
|
||||
return 0;
|
||||
}
|
||||
@@ -1283,11 +1289,14 @@ static void handle_v_attach(GArray *params, void *user_ctx)
|
||||
gdbserver_state.g_cpu = cpu;
|
||||
gdbserver_state.c_cpu = cpu;
|
||||
|
||||
g_string_printf(gdbserver_state.str_buf, "T%02xthread:", GDB_SIGNAL_TRAP);
|
||||
gdb_append_thread_id(cpu, gdbserver_state.str_buf);
|
||||
g_string_append_c(gdbserver_state.str_buf, ';');
|
||||
if (gdbserver_state.allow_stop_reply) {
|
||||
g_string_printf(gdbserver_state.str_buf, "T%02xthread:", GDB_SIGNAL_TRAP);
|
||||
gdb_append_thread_id(cpu, gdbserver_state.str_buf);
|
||||
g_string_append_c(gdbserver_state.str_buf, ';');
|
||||
gdbserver_state.allow_stop_reply = false;
|
||||
cleanup:
|
||||
gdb_put_strbuf();
|
||||
gdb_put_strbuf();
|
||||
}
|
||||
}
|
||||
|
||||
static void handle_v_kill(GArray *params, void *user_ctx)
|
||||
@@ -1310,12 +1319,14 @@ static const GdbCmdParseEntry gdb_v_commands_table[] = {
|
||||
.handler = handle_v_cont,
|
||||
.cmd = "Cont",
|
||||
.cmd_startswith = 1,
|
||||
.allow_stop_reply = true,
|
||||
.schema = "s0"
|
||||
},
|
||||
{
|
||||
.handler = handle_v_attach,
|
||||
.cmd = "Attach;",
|
||||
.cmd_startswith = 1,
|
||||
.allow_stop_reply = true,
|
||||
.schema = "l0"
|
||||
},
|
||||
{
|
||||
@@ -1698,10 +1709,13 @@ static void handle_gen_set(GArray *params, void *user_ctx)
|
||||
|
||||
static void handle_target_halt(GArray *params, void *user_ctx)
|
||||
{
|
||||
g_string_printf(gdbserver_state.str_buf, "T%02xthread:", GDB_SIGNAL_TRAP);
|
||||
gdb_append_thread_id(gdbserver_state.c_cpu, gdbserver_state.str_buf);
|
||||
g_string_append_c(gdbserver_state.str_buf, ';');
|
||||
gdb_put_strbuf();
|
||||
if (gdbserver_state.allow_stop_reply) {
|
||||
g_string_printf(gdbserver_state.str_buf, "T%02xthread:", GDB_SIGNAL_TRAP);
|
||||
gdb_append_thread_id(gdbserver_state.c_cpu, gdbserver_state.str_buf);
|
||||
g_string_append_c(gdbserver_state.str_buf, ';');
|
||||
gdb_put_strbuf();
|
||||
gdbserver_state.allow_stop_reply = false;
|
||||
}
|
||||
/*
|
||||
* Remove all the breakpoints when this query is issued,
|
||||
* because gdb is doing an initial connect and the state
|
||||
@@ -1725,7 +1739,8 @@ static int gdb_handle_packet(const char *line_buf)
|
||||
static const GdbCmdParseEntry target_halted_cmd_desc = {
|
||||
.handler = handle_target_halt,
|
||||
.cmd = "?",
|
||||
.cmd_startswith = 1
|
||||
.cmd_startswith = 1,
|
||||
.allow_stop_reply = true,
|
||||
};
|
||||
cmd_parser = &target_halted_cmd_desc;
|
||||
}
|
||||
@@ -1736,6 +1751,7 @@ static int gdb_handle_packet(const char *line_buf)
|
||||
.handler = handle_continue,
|
||||
.cmd = "c",
|
||||
.cmd_startswith = 1,
|
||||
.allow_stop_reply = true,
|
||||
.schema = "L0"
|
||||
};
|
||||
cmd_parser = &continue_cmd_desc;
|
||||
@@ -1747,6 +1763,7 @@ static int gdb_handle_packet(const char *line_buf)
|
||||
.handler = handle_cont_with_sig,
|
||||
.cmd = "C",
|
||||
.cmd_startswith = 1,
|
||||
.allow_stop_reply = true,
|
||||
.schema = "l0"
|
||||
};
|
||||
cmd_parser = &cont_with_sig_cmd_desc;
|
||||
@@ -1785,6 +1802,7 @@ static int gdb_handle_packet(const char *line_buf)
|
||||
.handler = handle_step,
|
||||
.cmd = "s",
|
||||
.cmd_startswith = 1,
|
||||
.allow_stop_reply = true,
|
||||
.schema = "L0"
|
||||
};
|
||||
cmd_parser = &step_cmd_desc;
|
||||
@@ -1976,6 +1994,7 @@ void gdb_read_byte(uint8_t ch)
|
||||
{
|
||||
uint8_t reply;
|
||||
|
||||
gdbserver_state.allow_stop_reply = false;
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
if (gdbserver_state.last_packet->len) {
|
||||
/* Waiting for a response to the last packet. If we see the start
|
||||
|
||||
@@ -65,6 +65,11 @@ typedef struct GDBState {
|
||||
GByteArray *mem_buf;
|
||||
int sstep_flags;
|
||||
int supported_sstep_flags;
|
||||
/*
|
||||
* Whether we are allowed to send a stop reply packet at this moment.
|
||||
* Must be set off after sending the stop reply itself.
|
||||
*/
|
||||
bool allow_stop_reply;
|
||||
} GDBState;
|
||||
|
||||
/* lives in main gdbstub.c */
|
||||
|
||||
+11
-2
@@ -43,6 +43,7 @@ static void reset_gdbserver_state(void)
|
||||
g_free(gdbserver_state.processes);
|
||||
gdbserver_state.processes = NULL;
|
||||
gdbserver_state.process_num = 0;
|
||||
gdbserver_state.allow_stop_reply = false;
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -139,6 +140,10 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state)
|
||||
return;
|
||||
}
|
||||
|
||||
if (!gdbserver_state.allow_stop_reply) {
|
||||
return;
|
||||
}
|
||||
|
||||
gdb_append_thread_id(cpu, tid);
|
||||
|
||||
switch (state) {
|
||||
@@ -205,6 +210,7 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state)
|
||||
|
||||
send_packet:
|
||||
gdb_put_packet(buf->str);
|
||||
gdbserver_state.allow_stop_reply = false;
|
||||
|
||||
/* disable single step if it was enabled */
|
||||
cpu_single_step(cpu, 0);
|
||||
@@ -422,8 +428,11 @@ void gdb_exit(int code)
|
||||
|
||||
trace_gdbstub_op_exiting((uint8_t)code);
|
||||
|
||||
snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
|
||||
gdb_put_packet(buf);
|
||||
if (gdbserver_state.allow_stop_reply) {
|
||||
snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
|
||||
gdb_put_packet(buf);
|
||||
gdbserver_state.allow_stop_reply = false;
|
||||
}
|
||||
|
||||
qemu_chr_fe_deinit(&gdbserver_system_state.chr, true);
|
||||
}
|
||||
|
||||
+16
-8
@@ -108,8 +108,11 @@ void gdb_exit(int code)
|
||||
|
||||
trace_gdbstub_op_exiting((uint8_t)code);
|
||||
|
||||
snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
|
||||
gdb_put_packet(buf);
|
||||
if (gdbserver_state.allow_stop_reply) {
|
||||
snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
|
||||
gdb_put_packet(buf);
|
||||
gdbserver_state.allow_stop_reply = false;
|
||||
}
|
||||
}
|
||||
|
||||
int gdb_handlesig(CPUState *cpu, int sig)
|
||||
@@ -127,11 +130,14 @@ int gdb_handlesig(CPUState *cpu, int sig)
|
||||
|
||||
if (sig != 0) {
|
||||
gdb_set_stop_cpu(cpu);
|
||||
g_string_printf(gdbserver_state.str_buf,
|
||||
"T%02xthread:", gdb_target_signal_to_gdb(sig));
|
||||
gdb_append_thread_id(cpu, gdbserver_state.str_buf);
|
||||
g_string_append_c(gdbserver_state.str_buf, ';');
|
||||
gdb_put_strbuf();
|
||||
if (gdbserver_state.allow_stop_reply) {
|
||||
g_string_printf(gdbserver_state.str_buf,
|
||||
"T%02xthread:", gdb_target_signal_to_gdb(sig));
|
||||
gdb_append_thread_id(cpu, gdbserver_state.str_buf);
|
||||
g_string_append_c(gdbserver_state.str_buf, ';');
|
||||
gdb_put_strbuf();
|
||||
gdbserver_state.allow_stop_reply = false;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* gdb_put_packet() might have detected that the peer terminated the
|
||||
@@ -174,12 +180,14 @@ void gdb_signalled(CPUArchState *env, int sig)
|
||||
{
|
||||
char buf[4];
|
||||
|
||||
if (!gdbserver_state.init || gdbserver_user_state.fd < 0) {
|
||||
if (!gdbserver_state.init || gdbserver_user_state.fd < 0 ||
|
||||
!gdbserver_state.allow_stop_reply) {
|
||||
return;
|
||||
}
|
||||
|
||||
snprintf(buf, sizeof(buf), "X%02x", gdb_target_signal_to_gdb(sig));
|
||||
gdb_put_packet(buf);
|
||||
gdbserver_state.allow_stop_reply = false;
|
||||
}
|
||||
|
||||
static void gdb_accept_init(int fd)
|
||||
|
||||
@@ -63,6 +63,9 @@ void cpu_loop(CPUHexagonState *env)
|
||||
case EXCP_ATOMIC:
|
||||
cpu_exec_step_atomic(cs);
|
||||
break;
|
||||
case EXCP_DEBUG:
|
||||
force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, 0);
|
||||
break;
|
||||
default:
|
||||
EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
|
||||
trapnr);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@@ -20,7 +20,10 @@
|
||||
|
||||
static inline const char *cpu_get_model(uint32_t eflags)
|
||||
{
|
||||
/* For now, treat anything newer than v5 as a v67 */
|
||||
static char buf[32];
|
||||
int err;
|
||||
|
||||
/* For now, treat anything newer than v5 as a v73 */
|
||||
/* FIXME - Disable instructions that are newer than the specified arch */
|
||||
if (eflags == 0x04 || /* v5 */
|
||||
eflags == 0x05 || /* v55 */
|
||||
@@ -30,11 +33,18 @@ static inline const char *cpu_get_model(uint32_t eflags)
|
||||
eflags == 0x65 || /* v65 */
|
||||
eflags == 0x66 || /* v66 */
|
||||
eflags == 0x67 || /* v67 */
|
||||
eflags == 0x8067 /* v67t */
|
||||
eflags == 0x8067 || /* v67t */
|
||||
eflags == 0x68 || /* v68 */
|
||||
eflags == 0x69 || /* v69 */
|
||||
eflags == 0x71 || /* v71 */
|
||||
eflags == 0x8071 || /* v71t */
|
||||
eflags == 0x73 /* v73 */
|
||||
) {
|
||||
return "v67";
|
||||
return "v73";
|
||||
}
|
||||
return "unknown";
|
||||
|
||||
err = snprintf(buf, sizeof(buf), "unknown (0x%x)", eflags);
|
||||
return err >= 0 && err < sizeof(buf) ? buf : "unknown";
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -2105,6 +2105,7 @@ endif
|
||||
config_host_data.set('CONFIG_GTK', gtk.found())
|
||||
config_host_data.set('CONFIG_VTE', vte.found())
|
||||
config_host_data.set('CONFIG_GTK_CLIPBOARD', have_gtk_clipboard)
|
||||
config_host_data.set('CONFIG_HEXAGON_IDEF_PARSER', get_option('hexagon_idef_parser'))
|
||||
config_host_data.set('CONFIG_LIBATTR', have_old_libattr)
|
||||
config_host_data.set('CONFIG_LIBCAP_NG', libcap_ng.found())
|
||||
config_host_data.set('CONFIG_EBPF', libbpf.found())
|
||||
|
||||
@@ -4,10 +4,10 @@ is a wide vector coprocessor designed for high performance computer vision,
|
||||
image processing, machine learning, and other workloads.
|
||||
|
||||
The following versions of the Hexagon core are supported
|
||||
Scalar core: v67
|
||||
https://developer.qualcomm.com/downloads/qualcomm-hexagon-v67-programmer-s-reference-manual
|
||||
HVX extension: v66
|
||||
https://developer.qualcomm.com/downloads/qualcomm-hexagon-v66-hvx-programmer-s-reference-manual
|
||||
Scalar core: v73
|
||||
https://developer.qualcomm.com/downloads/qualcomm-hexagon-v73-programmers-reference-manual-rev-aa
|
||||
HVX extension: v73
|
||||
https://developer.qualcomm.com/downloads/qualcomm-hexagon-v73-hvx-programmers-reference-manual-rev-aa
|
||||
|
||||
We presented an overview of the project at the 2019 KVM Forum.
|
||||
https://kvmforum2019.sched.com/event/Tmwc/qemu-hexagon-automatic-translation-of-the-isa-manual-pseudcode-to-tiny-code-instructions-of-a-vliw-architecture-niccolo-izzo-revng-taylor-simpson-qualcomm-innovation-center
|
||||
@@ -87,7 +87,7 @@ tcg_funcs_generated.c.inc
|
||||
TCGv RsV = hex_gpr[insn->regno[1]];
|
||||
TCGv RtV = hex_gpr[insn->regno[2]];
|
||||
gen_helper_A2_add(RdV, cpu_env, RsV, RtV);
|
||||
gen_log_reg_write(RdN, RdV);
|
||||
gen_log_reg_write(ctx, RdN, RdV);
|
||||
}
|
||||
|
||||
helper_funcs_generated.c.inc
|
||||
@@ -186,7 +186,7 @@ We also generate an analyze_<tag> function for each instruction. Currently,
|
||||
these functions record the writes to registers by calling ctx_log_*. During
|
||||
gen_start_packet, we invoke the analyze_<tag> function for each instruction in
|
||||
the packet, and we mark the implicit writes. After the analysis is performed,
|
||||
we initialize hex_new_value for each of the predicated assignments.
|
||||
we initialize the result register for each of the predicated assignments.
|
||||
|
||||
In addition to instruction semantics, we use a generator to create the decode
|
||||
tree. This generation is also a two step process. The first step is to run
|
||||
@@ -304,4 +304,4 @@ Here are some handy places to set breakpoints
|
||||
At the start of execution of a packet for a given PC
|
||||
br helper_debug_start_packet if env->gpr[41] == 0xdeadbeef
|
||||
At the end of execution of a packet for a given PC
|
||||
br helper_debug_commit_end if env->this_PC == 0xdeadbeef
|
||||
br helper_debug_commit_end if this_PC == 0xdeadbeef
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@@ -224,6 +224,7 @@ void arch_fpop_start(CPUHexagonState *env)
|
||||
|
||||
void arch_fpop_end(CPUHexagonState *env)
|
||||
{
|
||||
const bool pkt_need_commit = true;
|
||||
int flags = get_float_exception_flags(&env->fp_status);
|
||||
if (flags != 0) {
|
||||
SOFTFLOAT_TEST_FLAG(float_flag_inexact, FPINPF, FPINPE);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@@ -52,6 +52,12 @@ DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "")
|
||||
DEF_ATTRIB(REGWRSIZE_8B, "Memory width is 8 bytes", "", "")
|
||||
DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "")
|
||||
DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "")
|
||||
DEF_ATTRIB(RELEASE, "Releases a lock", "", "")
|
||||
DEF_ATTRIB(ACQUIRE, "Acquires a lock", "", "")
|
||||
|
||||
DEF_ATTRIB(RLS_INNER, "Store release inner visibility", "", "")
|
||||
DEF_ATTRIB(RLS_ALL_THREAD, "Store release among all threads", "", "")
|
||||
DEF_ATTRIB(RLS_SAME_THREAD, "Store release with the same thread", "", "")
|
||||
|
||||
/* V6 Vector attributes */
|
||||
DEF_ATTRIB(CVI, "Executes on the HVX extension", "", "")
|
||||
@@ -63,23 +69,27 @@ DEF_ATTRIB(CVI_VP_VS, "Double vector permute/shft insn executes on HVX", "", "")
|
||||
DEF_ATTRIB(CVI_VX, "Multiply instruction executes on HVX", "", "")
|
||||
DEF_ATTRIB(CVI_VX_DV, "Double vector multiply insn executes on HVX", "", "")
|
||||
DEF_ATTRIB(CVI_VS, "Shift instruction executes on HVX", "", "")
|
||||
DEF_ATTRIB(CVI_VS_3SRC, "This shift needs to borrow a source register", "", "")
|
||||
DEF_ATTRIB(CVI_VS_VX, "Permute/shift and multiply insn executes on HVX", "", "")
|
||||
DEF_ATTRIB(CVI_VA, "ALU instruction executes on HVX", "", "")
|
||||
DEF_ATTRIB(CVI_VA_DV, "Double vector alu instruction executes on HVX", "", "")
|
||||
DEF_ATTRIB(CVI_4SLOT, "Consumes all the vector execution resources", "", "")
|
||||
DEF_ATTRIB(CVI_TMP, "Transient Memory Load not written to register", "", "")
|
||||
DEF_ATTRIB(CVI_REMAP, "Register Renaming not written to register file", "", "")
|
||||
DEF_ATTRIB(CVI_GATHER, "CVI Gather operation", "", "")
|
||||
DEF_ATTRIB(CVI_SCATTER, "CVI Scatter operation", "", "")
|
||||
DEF_ATTRIB(CVI_SCATTER_RELEASE, "CVI Store Release for scatter", "", "")
|
||||
DEF_ATTRIB(CVI_TMP_DST, "CVI instruction that doesn't write a register", "", "")
|
||||
DEF_ATTRIB(CVI_SLOT23, "Can execute in slot 2 or slot 3 (HVX)", "", "")
|
||||
|
||||
DEF_ATTRIB(VTCM_ALLBANK_ACCESS, "Allocates in all VTCM schedulers.", "", "")
|
||||
|
||||
/* Change-of-flow attributes */
|
||||
DEF_ATTRIB(JUMP, "Jump-type instruction", "", "")
|
||||
DEF_ATTRIB(INDIRECT, "Absolute register jump", "", "")
|
||||
DEF_ATTRIB(CALL, "Function call instruction", "", "")
|
||||
DEF_ATTRIB(COF, "Change-of-flow instruction", "", "")
|
||||
DEF_ATTRIB(HINTED_COF, "This instruction is a hinted change-of-flow", "", "")
|
||||
DEF_ATTRIB(CONDEXEC, "May be cancelled by a predicate", "", "")
|
||||
DEF_ATTRIB(DOTNEWVALUE, "Uses a register value generated in this pkt", "", "")
|
||||
DEF_ATTRIB(NEWCMPJUMP, "Compound compare and jump", "", "")
|
||||
@@ -102,6 +112,10 @@ DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1")
|
||||
DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2")
|
||||
DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3")
|
||||
DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "")
|
||||
DEF_ATTRIB(IMPLICIT_READS_P0, "Reads the P0 register", "", "")
|
||||
DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1 register", "", "")
|
||||
DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
|
||||
DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
|
||||
DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
|
||||
DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
|
||||
DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
|
||||
@@ -140,6 +154,8 @@ DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "", "")
|
||||
DEF_ATTRIB(ICINVA, "icinva", "", "")
|
||||
DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "")
|
||||
|
||||
DEF_ATTRIB(NO_INTRINSIC, "Don't generate an intrisic", "", "")
|
||||
|
||||
/* Documentation Notes */
|
||||
DEF_ATTRIB(NOTE_CONDITIONAL, "can be conditionally executed", "", "")
|
||||
DEF_ATTRIB(NOTE_NEWVAL_SLOT0, "New-value oprnd must execute on slot 0", "", "")
|
||||
@@ -148,7 +164,11 @@ DEF_ATTRIB(NOTE_NOPACKET, "solo instruction", "", "")
|
||||
DEF_ATTRIB(NOTE_AXOK, "May only be grouped with ALU32 or non-FP XTYPE.", "", "")
|
||||
DEF_ATTRIB(NOTE_LATEPRED, "The predicate can not be used as a .new", "", "")
|
||||
DEF_ATTRIB(NOTE_NVSLOT0, "Can execute only in slot 0 (ST)", "", "")
|
||||
DEF_ATTRIB(NOTE_NOVP, "Cannot be paired with a HVX permute instruction", "", "")
|
||||
DEF_ATTRIB(NOTE_VA_UNARY, "Combined with HVX ALU op (must be unary)", "", "")
|
||||
|
||||
/* V6 MMVector Notes for Documentation */
|
||||
DEF_ATTRIB(NOTE_SHIFT_RESOURCE, "Uses the HVX shift resource.", "", "")
|
||||
/* Restrictions to make note of */
|
||||
DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, "Packet must not have slot 1 store", "", "")
|
||||
DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be used as a .new.", "", "")
|
||||
|
||||
+39
-3
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@@ -24,9 +24,32 @@
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "fpu/softfloat-helpers.h"
|
||||
#include "tcg/tcg.h"
|
||||
#include "exec/gdbstub.h"
|
||||
|
||||
static void hexagon_v67_cpu_init(Object *obj)
|
||||
static void hexagon_v67_cpu_init(Object *obj) { }
|
||||
static void hexagon_v68_cpu_init(Object *obj) { }
|
||||
static void hexagon_v69_cpu_init(Object *obj) { }
|
||||
static void hexagon_v71_cpu_init(Object *obj) { }
|
||||
static void hexagon_v73_cpu_init(Object *obj) { }
|
||||
|
||||
static void hexagon_cpu_list_entry(gpointer data, gpointer user_data)
|
||||
{
|
||||
ObjectClass *oc = data;
|
||||
char *name = g_strdup(object_class_get_name(oc));
|
||||
if (g_str_has_suffix(name, HEXAGON_CPU_TYPE_SUFFIX)) {
|
||||
name[strlen(name) - strlen(HEXAGON_CPU_TYPE_SUFFIX)] = '\0';
|
||||
}
|
||||
qemu_printf(" %s\n", name);
|
||||
g_free(name);
|
||||
}
|
||||
|
||||
void hexagon_cpu_list(void)
|
||||
{
|
||||
GSList *list;
|
||||
list = object_class_get_list_sorted(TYPE_HEXAGON_CPU, false);
|
||||
qemu_printf("Available CPUs:\n");
|
||||
g_slist_foreach(list, hexagon_cpu_list_entry, NULL);
|
||||
g_slist_free(list);
|
||||
}
|
||||
|
||||
static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
|
||||
@@ -52,6 +75,8 @@ static Property hexagon_lldb_compat_property =
|
||||
static Property hexagon_lldb_stack_adjust_property =
|
||||
DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust,
|
||||
0, qdev_prop_uint32, target_ulong);
|
||||
static Property hexagon_short_circuit_property =
|
||||
DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true);
|
||||
|
||||
const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {
|
||||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
||||
@@ -315,6 +340,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
|
||||
return;
|
||||
}
|
||||
|
||||
gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register,
|
||||
hexagon_hvx_gdb_write_register,
|
||||
NUM_VREGS + NUM_QREGS,
|
||||
"hexagon-hvx.xml", 0);
|
||||
|
||||
qemu_init_vcpu(cs);
|
||||
cpu_reset(cs);
|
||||
|
||||
@@ -328,6 +358,7 @@ static void hexagon_cpu_init(Object *obj)
|
||||
cpu_set_cpustate_pointers(cpu);
|
||||
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property);
|
||||
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
|
||||
qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property);
|
||||
}
|
||||
|
||||
#include "hw/core/tcg-cpu-ops.h"
|
||||
@@ -358,8 +389,9 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
|
||||
cc->get_pc = hexagon_cpu_get_pc;
|
||||
cc->gdb_read_register = hexagon_gdb_read_register;
|
||||
cc->gdb_write_register = hexagon_gdb_write_register;
|
||||
cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREGS;
|
||||
cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS;
|
||||
cc->gdb_stop_before_watchpoint = true;
|
||||
cc->gdb_core_xml_file = "hexagon-core.xml";
|
||||
cc->disas_set_info = hexagon_cpu_disas_set_info;
|
||||
cc->tcg_ops = &hexagon_tcg_ops;
|
||||
}
|
||||
@@ -382,6 +414,10 @@ static const TypeInfo hexagon_cpu_type_infos[] = {
|
||||
.class_init = hexagon_cpu_class_init,
|
||||
},
|
||||
DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init),
|
||||
DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init),
|
||||
DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init),
|
||||
DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init),
|
||||
DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init),
|
||||
};
|
||||
|
||||
DEFINE_TYPES(hexagon_cpu_type_infos)
|
||||
|
||||
@@ -43,6 +43,13 @@
|
||||
#define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
|
||||
|
||||
#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
|
||||
#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
|
||||
#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
|
||||
#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
|
||||
#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
|
||||
|
||||
void hexagon_cpu_list(void);
|
||||
#define cpu_list hexagon_cpu_list
|
||||
|
||||
#define MMU_USER_IDX 0
|
||||
|
||||
@@ -78,28 +85,21 @@ typedef struct {
|
||||
typedef struct CPUArchState {
|
||||
target_ulong gpr[TOTAL_PER_THREAD_REGS];
|
||||
target_ulong pred[NUM_PREGS];
|
||||
target_ulong branch_taken;
|
||||
|
||||
/* For comparing with LLDB on target - see adjust_stack_ptrs function */
|
||||
target_ulong last_pc_dumped;
|
||||
target_ulong stack_start;
|
||||
|
||||
uint8_t slot_cancelled;
|
||||
target_ulong new_value[TOTAL_PER_THREAD_REGS];
|
||||
target_ulong new_value_usr;
|
||||
|
||||
/*
|
||||
* Only used when HEX_DEBUG is on, but unconditionally included
|
||||
* to reduce recompile time when turning HEX_DEBUG on/off.
|
||||
*/
|
||||
target_ulong this_PC;
|
||||
target_ulong reg_written[TOTAL_PER_THREAD_REGS];
|
||||
|
||||
target_ulong new_pred_value[NUM_PREGS];
|
||||
target_ulong pred_written;
|
||||
|
||||
MemLog mem_log_stores[STORES_MAX];
|
||||
target_ulong pkt_has_store_s1;
|
||||
target_ulong dczero_addr;
|
||||
|
||||
float_status fp_status;
|
||||
|
||||
@@ -146,6 +146,7 @@ struct ArchCPU {
|
||||
|
||||
bool lldb_compat;
|
||||
target_ulong lldb_stack_adjust;
|
||||
bool short_circuit;
|
||||
};
|
||||
|
||||
#include "cpu_bits.h"
|
||||
|
||||
+27
-3
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@@ -797,7 +797,26 @@ static bool decode_parsebits_is_loopend(uint32_t encoding32)
|
||||
return bits == 0x2;
|
||||
}
|
||||
|
||||
static void
|
||||
static bool has_valid_slot_assignment(Packet *pkt)
|
||||
{
|
||||
int used_slots = 0;
|
||||
for (int i = 0; i < pkt->num_insns; i++) {
|
||||
int slot_mask;
|
||||
Insn *insn = &pkt->insn[i];
|
||||
if (decode_opcode_ends_loop(insn->opcode)) {
|
||||
/* We overload slot 0 for endloop. */
|
||||
continue;
|
||||
}
|
||||
slot_mask = 1 << insn->slot;
|
||||
if (used_slots & slot_mask) {
|
||||
return false;
|
||||
}
|
||||
used_slots |= slot_mask;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool
|
||||
decode_set_slot_number(Packet *pkt)
|
||||
{
|
||||
int slot;
|
||||
@@ -886,6 +905,8 @@ decode_set_slot_number(Packet *pkt)
|
||||
/* Then push it to slot0 */
|
||||
pkt->insn[slot1_iidx].slot = 0;
|
||||
}
|
||||
|
||||
return has_valid_slot_assignment(pkt);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -961,8 +982,11 @@ int decode_packet(int max_words, const uint32_t *words, Packet *pkt,
|
||||
decode_apply_extenders(pkt);
|
||||
if (!disas_only) {
|
||||
decode_remove_extenders(pkt);
|
||||
if (!decode_set_slot_number(pkt)) {
|
||||
/* Invalid packet */
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
decode_set_slot_number(pkt);
|
||||
decode_fill_newvalue_regno(pkt);
|
||||
|
||||
if (pkt->pkt_has_hvx) {
|
||||
|
||||
@@ -25,6 +25,14 @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
|
||||
HexagonCPU *cpu = HEXAGON_CPU(cs);
|
||||
CPUHexagonState *env = &cpu->env;
|
||||
|
||||
if (n == HEX_REG_P3_0_ALIASED) {
|
||||
uint32_t p3_0 = 0;
|
||||
for (int i = 0; i < NUM_PREGS; i++) {
|
||||
p3_0 = deposit32(p3_0, i * 8, 8, env->pred[i]);
|
||||
}
|
||||
return gdb_get_regl(mem_buf, p3_0);
|
||||
}
|
||||
|
||||
if (n < TOTAL_PER_THREAD_REGS) {
|
||||
return gdb_get_regl(mem_buf, env->gpr[n]);
|
||||
}
|
||||
@@ -37,6 +45,14 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
|
||||
HexagonCPU *cpu = HEXAGON_CPU(cs);
|
||||
CPUHexagonState *env = &cpu->env;
|
||||
|
||||
if (n == HEX_REG_P3_0_ALIASED) {
|
||||
uint32_t p3_0 = ldtul_p(mem_buf);
|
||||
for (int i = 0; i < NUM_PREGS; i++) {
|
||||
env->pred[i] = extract32(p3_0, i * 8, 8);
|
||||
}
|
||||
return sizeof(target_ulong);
|
||||
}
|
||||
|
||||
if (n < TOTAL_PER_THREAD_REGS) {
|
||||
env->gpr[n] = ldtul_p(mem_buf);
|
||||
return sizeof(target_ulong);
|
||||
@@ -44,3 +60,71 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
|
||||
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
static int gdb_get_vreg(CPUHexagonState *env, GByteArray *mem_buf, int n)
|
||||
{
|
||||
int total = 0;
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) {
|
||||
total += gdb_get_regl(mem_buf, env->VRegs[n].uw[i]);
|
||||
}
|
||||
return total;
|
||||
}
|
||||
|
||||
static int gdb_get_qreg(CPUHexagonState *env, GByteArray *mem_buf, int n)
|
||||
{
|
||||
int total = 0;
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) {
|
||||
total += gdb_get_regl(mem_buf, env->QRegs[n].uw[i]);
|
||||
}
|
||||
return total;
|
||||
}
|
||||
|
||||
int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n)
|
||||
{
|
||||
if (n < NUM_VREGS) {
|
||||
return gdb_get_vreg(env, mem_buf, n);
|
||||
}
|
||||
n -= NUM_VREGS;
|
||||
|
||||
if (n < NUM_QREGS) {
|
||||
return gdb_get_qreg(env, mem_buf, n);
|
||||
}
|
||||
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) {
|
||||
env->VRegs[n].uw[i] = ldtul_p(mem_buf);
|
||||
mem_buf += 4;
|
||||
}
|
||||
return MAX_VEC_SIZE_BYTES;
|
||||
}
|
||||
|
||||
static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) {
|
||||
env->QRegs[n].uw[i] = ldtul_p(mem_buf);
|
||||
mem_buf += 4;
|
||||
}
|
||||
return MAX_VEC_SIZE_BYTES / 8;
|
||||
}
|
||||
|
||||
int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n)
|
||||
{
|
||||
if (n < NUM_VREGS) {
|
||||
return gdb_put_vreg(env, mem_buf, n);
|
||||
}
|
||||
n -= NUM_VREGS;
|
||||
|
||||
if (n < NUM_QREGS) {
|
||||
return gdb_put_qreg(env, mem_buf, n);
|
||||
}
|
||||
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
@@ -35,47 +35,55 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
|
||||
predicated = "true" if is_predicated(tag) else "false"
|
||||
if regtype == "R":
|
||||
if regid in {"ss", "tt"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n")
|
||||
elif regid in {"dd", "ee", "xx", "yy"}:
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
|
||||
elif regid in {"s", "t", "u", "v"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
|
||||
elif regid in {"d", "e", "x", "y"}:
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
elif regtype == "P":
|
||||
if regid in {"s", "t", "u", "v"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_pred_read(ctx, {regN});\n")
|
||||
elif regid in {"d", "e", "x"}:
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_pred_write(ctx, {regN});\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
elif regtype == "C":
|
||||
if regid == "ss":
|
||||
f.write(
|
||||
f"// const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n"
|
||||
f" const int {regN} = insn->regno[{regno}] "
|
||||
"+ HEX_REG_SA0;\n"
|
||||
)
|
||||
f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n")
|
||||
elif regid == "dd":
|
||||
f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
|
||||
f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
|
||||
elif regid == "s":
|
||||
f.write(
|
||||
f"// const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n"
|
||||
f" const int {regN} = insn->regno[{regno}] "
|
||||
"+ HEX_REG_SA0;\n"
|
||||
)
|
||||
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
|
||||
elif regid == "d":
|
||||
f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
|
||||
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
elif regtype == "M":
|
||||
if regid == "u":
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
elif regtype == "V":
|
||||
newv = "EXT_DFL"
|
||||
if hex_common.is_new_result(tag):
|
||||
@@ -88,22 +96,25 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
|
||||
f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, " f"{predicated});\n"
|
||||
)
|
||||
elif regid in {"uu", "vv"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_vreg_read_pair(ctx, {regN});\n")
|
||||
elif regid in {"s", "u", "v", "w"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_vreg_read(ctx, {regN});\n")
|
||||
elif regid in {"d", "x", "y"}:
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, " f"{predicated});\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
elif regtype == "Q":
|
||||
if regid in {"d", "e", "x"}:
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_qreg_write(ctx, {regN});\n")
|
||||
elif regid in {"s", "t", "u", "v"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_qreg_read(ctx, {regN});\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
elif regtype == "G":
|
||||
if regid in {"dd"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
@@ -114,7 +125,7 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
|
||||
elif regid in {"s"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
elif regtype == "S":
|
||||
if regid in {"dd"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
@@ -125,30 +136,33 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
|
||||
elif regid in {"s"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
|
||||
|
||||
def analyze_opn_new(f, tag, regtype, regid, regno):
|
||||
regN = f"{regtype}{regid}N"
|
||||
if regtype == "N":
|
||||
if regid in {"s", "t"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
elif regtype == "P":
|
||||
if regid in {"t", "u", "v"}:
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_pred_read(ctx, {regN});\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
elif regtype == "O":
|
||||
if regid == "s":
|
||||
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" const int {regN} = insn->regno[{regno}];\n")
|
||||
f.write(f" ctx_log_vreg_read(ctx, {regN});\n")
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
hex_common.bad_register(regtype, regid)
|
||||
|
||||
|
||||
def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
|
||||
@@ -160,9 +174,9 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
|
||||
elif hex_common.is_new_val(regtype, regid, tag):
|
||||
analyze_opn_new(f, tag, regtype, regid, i)
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid, toss, numregs)
|
||||
hex_common.bad_register(regtype, regid, toss, numregs)
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid, toss, numregs)
|
||||
hex_common.bad_register(regtype, regid, toss, numregs)
|
||||
|
||||
|
||||
##
|
||||
@@ -174,8 +188,10 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
|
||||
## Insn *insn G_GNUC_UNUSED = ctx->insn;
|
||||
## const int RdN = insn->regno[0];
|
||||
## ctx_log_reg_write(ctx, RdN, false);
|
||||
## // const int RsN = insn->regno[1];
|
||||
## // const int RtN = insn->regno[2];
|
||||
## const int RsN = insn->regno[1];
|
||||
## ctx_log_reg_read(ctx, RsN);
|
||||
## const int RtN = insn->regno[2];
|
||||
## ctx_log_reg_read(ctx, RtN);
|
||||
## }
|
||||
##
|
||||
def gen_analyze_func(f, tag, regs, imms):
|
||||
@@ -193,8 +209,11 @@ def gen_analyze_func(f, tag, regs, imms):
|
||||
has_generated_helper = not hex_common.skip_qemu_helper(
|
||||
tag
|
||||
) and not hex_common.is_idef_parser_enabled(tag)
|
||||
if has_generated_helper and "A_SCALAR_LOAD" in hex_common.attribdict[tag]:
|
||||
f.write(" ctx->need_pkt_has_store_s1 = true;\n")
|
||||
|
||||
## Mark HVX instructions with generated helpers
|
||||
if (has_generated_helper and
|
||||
"A_CVI" in hex_common.attribdict[tag]):
|
||||
f.write(" ctx->has_hvx_helper = true;\n")
|
||||
|
||||
f.write("}\n\n")
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user