mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging
target/xtensa: FLIX support, various fixes and test improvements - add FLIX (flexible length instructions extension) support; - make testsuite runnable on wider range of xtensa cores; - add floating point opcode tests; - don't add duplicate 'static' in import_core.sh script; - fix undefined opcodes detection in test_mmuhifi_c3 overlay. # gpg: Signature made Thu 28 Feb 2019 12:53:23 GMT # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20190228-xtensa: (40 commits) tests/tcg/xtensa: add FPU2000 coprocessor tests tests/tcg/xtensa: add FP1 group tests tests/tcg/xtensa: add FP0 group conversion tests tests/tcg/xtensa: add FP0 group arithmetic tests tests/tcg/xtensa: add LSCI/LSCX group tests tests/tcg/xtensa: add test for FLIX tests/tcg/xtensa: conditionalize MMU-related tests tests/tcg/xtensa: conditionalize windowed register tests tests/tcg/xtensa: conditionalize and fix s32c1i tests tests/tcg/xtensa: fix SR tests for big endian configs tests/tcg/xtensa: conditionalize and expand SR tests tests/tcg/xtensa: conditionalize timer/CCOUNT tests tests/tcg/xtensa: conditionalize interrupt tests tests/tcg/xtensa: add straightforward conditionals tests/tcg/xtensa: conditionalize cache option tests tests/tcg/xtensa: conditionalize debug option tests tests/tcg/xtensa: enable boolean tests tests/tcg/xtensa: fix endianness issues in test_b tests/tcg/xtensa: don't use optional opcodes in generic code tests/tcg/xtensa: support configs with LITBASE ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
File diff suppressed because it is too large
Load Diff
+32
-8
@@ -131,6 +131,7 @@ enum {
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ACCLO = 16,
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ACCHI = 17,
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MR = 32,
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PREFCTL = 40,
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WINDOW_BASE = 72,
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WINDOW_START = 73,
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PTEVADDR = 83,
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@@ -345,14 +346,21 @@ typedef struct XtensaMemory {
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} location[MAX_NMEMORY];
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} XtensaMemory;
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typedef struct opcode_arg {
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uint32_t imm;
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uint32_t raw_imm;
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void *in;
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void *out;
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} OpcodeArg;
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typedef struct DisasContext DisasContext;
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typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[],
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typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[],
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const uint32_t par[]);
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typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc,
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const uint32_t arg[],
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const OpcodeArg arg[],
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const uint32_t par[]);
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typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc,
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const uint32_t arg[],
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const OpcodeArg arg[],
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const uint32_t par[]);
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enum {
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@@ -368,19 +376,34 @@ enum {
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XTENSA_OP_DIVIDE_BY_ZERO = 0x100,
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/* Postprocessing flags */
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XTENSA_OP_CHECK_INTERRUPTS = 0x200,
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XTENSA_OP_EXIT_TB_M1 = 0x400,
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XTENSA_OP_EXIT_TB_0 = 0x800,
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XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000,
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XTENSA_OP_POSTPROCESS =
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XTENSA_OP_CHECK_INTERRUPTS |
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XTENSA_OP_EXIT_TB_M1 |
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XTENSA_OP_EXIT_TB_0 |
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XTENSA_OP_SYNC_REGISTER_WINDOW,
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XTENSA_OP_NAME_ARRAY = 0x8000,
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XTENSA_OP_CONTROL_FLOW = 0x10000,
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XTENSA_OP_STORE = 0x20000,
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XTENSA_OP_LOAD = 0x40000,
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XTENSA_OP_LOAD_STORE =
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XTENSA_OP_LOAD | XTENSA_OP_STORE,
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};
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typedef struct XtensaOpcodeOps {
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const char *name;
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const void *name;
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XtensaOpcodeOp translate;
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XtensaOpcodeBoolTest test_ill;
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XtensaOpcodeUintTest test_overflow;
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const uint32_t *par;
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uint32_t op_flags;
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uint32_t windowed_register_op;
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uint32_t coprocessor;
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} XtensaOpcodeOps;
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@@ -438,6 +461,8 @@ struct XtensaConfig {
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xtensa_isa isa;
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XtensaOpcodeOps **opcode_ops;
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const XtensaOpcodeTranslators **opcode_translators;
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xtensa_regfile a_regfile;
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void ***regfile;
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uint32_t clock_freq_khz;
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@@ -474,6 +499,7 @@ typedef struct CPUXtensaState {
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float64 f64;
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} fregs[16];
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float_status fp_status;
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uint32_t windowbase_next;
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#ifndef CONFIG_USER_ONLY
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xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
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@@ -565,8 +591,8 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
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void xtensa_translate_init(void);
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void **xtensa_get_regfile_by_name(const char *name);
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void xtensa_breakpoint_handler(CPUState *cs);
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void xtensa_finalize_config(XtensaConfig *config);
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void xtensa_register_core(XtensaConfigList *node);
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void xtensa_sim_open_console(Chardev *chr);
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void check_interrupts(CPUXtensaState *s);
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@@ -588,8 +614,6 @@ static inline void xtensa_select_static_vectors(CPUXtensaState *env,
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env->static_vectors = n;
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}
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void xtensa_runstall(CPUXtensaState *env, bool runstall);
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XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
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const char *opcode);
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#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
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#define XTENSA_OPTION_ALL (~(uint64_t)0)
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+82
-12
@@ -30,24 +30,60 @@
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#include "exec/exec-all.h"
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#include "exec/gdbstub.h"
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#include "exec/helper-proto.h"
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#include "qemu/error-report.h"
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#include "qemu/host-utils.h"
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static struct XtensaConfigList *xtensa_cores;
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static void xtensa_core_class_init(ObjectClass *oc, void *data)
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static void add_translator_to_hash(GHashTable *translator,
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const char *name,
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const XtensaOpcodeOps *opcode)
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{
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CPUClass *cc = CPU_CLASS(oc);
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XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
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const XtensaConfig *config = data;
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if (!g_hash_table_insert(translator, (void *)name, (void *)opcode)) {
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error_report("Multiple definitions of '%s' opcode in a single table",
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name);
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}
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}
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xcc->config = config;
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static GHashTable *hash_opcode_translators(const XtensaOpcodeTranslators *t)
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{
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unsigned i, j;
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GHashTable *translator = g_hash_table_new(g_str_hash, g_str_equal);
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/* Use num_core_regs to see only non-privileged registers in an unmodified
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* gdb. Use num_regs to see all registers. gdb modification is required
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* for that: reset bit 0 in the 'flags' field of the registers definitions
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* in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
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*/
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cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
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for (i = 0; i < t->num_opcodes; ++i) {
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if (t->opcode[i].op_flags & XTENSA_OP_NAME_ARRAY) {
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const char * const *name = t->opcode[i].name;
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for (j = 0; name[j]; ++j) {
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add_translator_to_hash(translator,
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(void *)name[j],
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(void *)(t->opcode + i));
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}
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} else {
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add_translator_to_hash(translator,
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(void *)t->opcode[i].name,
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(void *)(t->opcode + i));
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}
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}
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return translator;
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}
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static XtensaOpcodeOps *
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xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
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const char *name)
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{
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static GHashTable *translators;
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GHashTable *translator;
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if (translators == NULL) {
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translators = g_hash_table_new(g_direct_hash, g_direct_equal);
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}
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translator = g_hash_table_lookup(translators, t);
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if (translator == NULL) {
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translator = hash_opcode_translators(t);
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g_hash_table_insert(translators, (void *)t, translator);
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}
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return g_hash_table_lookup(translator, name);
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}
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static void init_libisa(XtensaConfig *config)
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@@ -55,11 +91,13 @@ static void init_libisa(XtensaConfig *config)
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unsigned i, j;
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unsigned opcodes;
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unsigned formats;
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unsigned regfiles;
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config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL);
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assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH);
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opcodes = xtensa_isa_num_opcodes(config->isa);
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formats = xtensa_isa_num_formats(config->isa);
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regfiles = xtensa_isa_num_regfiles(config->isa);
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config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes);
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for (i = 0; i < formats; ++i) {
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@@ -88,9 +126,23 @@ static void init_libisa(XtensaConfig *config)
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#endif
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config->opcode_ops[i] = ops;
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}
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config->a_regfile = xtensa_regfile_lookup(config->isa, "AR");
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config->regfile = g_new(void **, regfiles);
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for (i = 0; i < regfiles; ++i) {
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const char *name = xtensa_regfile_name(config->isa, i);
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config->regfile[i] = xtensa_get_regfile_by_name(name);
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#ifdef DEBUG
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if (config->regfile[i] == NULL) {
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fprintf(stderr, "regfile '%s' not found for %s\n",
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name, config->name);
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}
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#endif
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}
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}
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void xtensa_finalize_config(XtensaConfig *config)
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static void xtensa_finalize_config(XtensaConfig *config)
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{
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if (config->isa_internal) {
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init_libisa(config);
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@@ -111,6 +163,24 @@ void xtensa_finalize_config(XtensaConfig *config)
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}
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}
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static void xtensa_core_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
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XtensaConfig *config = data;
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xtensa_finalize_config(config);
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xcc->config = config;
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/*
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* Use num_core_regs to see only non-privileged registers in an unmodified
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||||
* gdb. Use num_regs to see all registers. gdb modification is required
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||||
* for that: reset bit 0 in the 'flags' field of the registers definitions
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||||
* in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
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||||
*/
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cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
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}
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void xtensa_register_core(XtensaConfigList *node)
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{
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TypeInfo type = {
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@@ -3,12 +3,11 @@ DEF_HELPER_3(exception_cause, noreturn, env, i32, i32)
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DEF_HELPER_4(exception_cause_vaddr, noreturn, env, i32, i32, i32)
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DEF_HELPER_3(debug_exception, noreturn, env, i32, i32)
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|
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DEF_HELPER_2(wsr_windowbase, void, env, i32)
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DEF_HELPER_1(sync_windowbase, void, env)
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DEF_HELPER_4(entry, void, env, i32, i32, i32)
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DEF_HELPER_2(test_ill_retw, void, env, i32)
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DEF_HELPER_2(test_underflow_retw, void, env, i32)
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DEF_HELPER_2(retw, i32, env, i32)
|
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DEF_HELPER_2(rotw, void, env, i32)
|
||||
DEF_HELPER_2(retw, void, env, i32)
|
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DEF_HELPER_3(window_check, noreturn, env, i32, i32)
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DEF_HELPER_1(restore_owb, void, env)
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DEF_HELPER_2(movsp, void, env, i32)
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|
||||
@@ -27,7 +27,7 @@ tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
|
||||
# Fix up known issues in the xtensa-modules.c
|
||||
#
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tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \
|
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sed -e 's/\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \
|
||||
sed -e 's/^\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \
|
||||
-e '/^int num_bypass_groups()/,/}/d' \
|
||||
-e '/^int num_bypass_group_chunks()/,/}/d' \
|
||||
-e '/^uint32 \*bypass_entry(int i)/,/}/d' \
|
||||
|
||||
@@ -377,7 +377,6 @@
|
||||
static XtensaConfigList node = { \
|
||||
.config = &core, \
|
||||
}; \
|
||||
xtensa_finalize_config(&core); \
|
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xtensa_register_core(&node); \
|
||||
}
|
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#else
|
||||
|
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+1075
-1047
File diff suppressed because it is too large
Load Diff
@@ -96,9 +96,9 @@ void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta)
|
||||
xtensa_rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
|
||||
}
|
||||
|
||||
void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
|
||||
void HELPER(sync_windowbase)(CPUXtensaState *env)
|
||||
{
|
||||
xtensa_rotate_window_abs(env, v);
|
||||
xtensa_rotate_window_abs(env, env->windowbase_next);
|
||||
}
|
||||
|
||||
void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
|
||||
@@ -106,9 +106,8 @@ void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
|
||||
int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
|
||||
|
||||
env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm;
|
||||
xtensa_rotate_window(env, callinc);
|
||||
env->sregs[WINDOW_START] |=
|
||||
windowstart_bit(env->sregs[WINDOW_BASE], env);
|
||||
env->windowbase_next = env->sregs[WINDOW_BASE] + callinc;
|
||||
env->sregs[WINDOW_START] |= windowstart_bit(env->windowbase_next, env);
|
||||
}
|
||||
|
||||
void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
|
||||
@@ -185,20 +184,11 @@ void HELPER(test_underflow_retw)(CPUXtensaState *env, uint32_t pc)
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
|
||||
void HELPER(retw)(CPUXtensaState *env, uint32_t a0)
|
||||
{
|
||||
int n = (env->regs[0] >> 30) & 0x3;
|
||||
uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
|
||||
uint32_t ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
|
||||
int n = (a0 >> 30) & 0x3;
|
||||
|
||||
xtensa_rotate_window(env, -n);
|
||||
env->sregs[WINDOW_START] &= ~windowstart_bit(windowbase, env);
|
||||
return ret_pc;
|
||||
}
|
||||
|
||||
void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
|
||||
{
|
||||
xtensa_rotate_window(env, imm4);
|
||||
}
|
||||
|
||||
void xtensa_restore_owb(CPUXtensaState *env)
|
||||
|
||||
@@ -18,6 +18,9 @@ CC = $(CROSS)gcc
|
||||
AS = $(CROSS)gcc -x assembler-with-cpp
|
||||
LD = $(CROSS)ld
|
||||
|
||||
ASFLAGS = -Wa,--no-absolute-literals
|
||||
vectors_ASFLAGS = -mtext-section-literals
|
||||
|
||||
XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa
|
||||
INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target/xtensa/core-$(CORE)
|
||||
XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS))
|
||||
@@ -28,15 +31,21 @@ CRT = crt.o vectors.o
|
||||
|
||||
TESTCASES += test_b.tst
|
||||
TESTCASES += test_bi.tst
|
||||
#TESTCASES += test_boolean.tst
|
||||
TESTCASES += test_boolean.tst
|
||||
TESTCASES += test_break.tst
|
||||
TESTCASES += test_bz.tst
|
||||
TESTCASES += test_cache.tst
|
||||
TESTCASES += test_clamps.tst
|
||||
TESTCASES += test_extui.tst
|
||||
TESTCASES += test_fail.tst
|
||||
TESTCASES += test_flix.tst
|
||||
TESTCASES += test_fp0_arith.tst
|
||||
TESTCASES += test_fp0_conv.tst
|
||||
TESTCASES += test_fp1.tst
|
||||
TESTCASES += test_fp_cpenable.tst
|
||||
TESTCASES += test_interrupt.tst
|
||||
TESTCASES += test_loop.tst
|
||||
TESTCASES += test_lsc.tst
|
||||
TESTCASES += test_mac16.tst
|
||||
TESTCASES += test_max.tst
|
||||
TESTCASES += test_min.tst
|
||||
@@ -68,7 +77,7 @@ linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S
|
||||
$(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@
|
||||
|
||||
%.o: $(XTENSA_SRC_PATH)/%.S
|
||||
$(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@
|
||||
$(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) -c $< -o $@
|
||||
|
||||
%.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
|
||||
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
|
||||
|
||||
@@ -1,17 +1,29 @@
|
||||
#include "core-isa.h"
|
||||
|
||||
#if XTENSA_HAVE_BE
|
||||
#ifndef XCHAL_VECBASE_RESET_VADDR
|
||||
#define XCHAL_VECBASE_RESET_VADDR XCHAL_WINDOW_VECTORS_VADDR
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#endif
|
||||
|
||||
#define RAM_SIZE 0x08000000 /* 128M */
|
||||
#define ROM_SIZE 0x00001000 /* 4k */
|
||||
#define VECTORS_RESERVED_SIZE 0x1000
|
||||
|
||||
#if XCHAL_HAVE_BE
|
||||
OUTPUT_FORMAT("elf32-xtensa-be")
|
||||
#else
|
||||
OUTPUT_FORMAT("elf32-xtensa-le")
|
||||
#endif
|
||||
ENTRY(_start)
|
||||
|
||||
__DYNAMIC = 0;
|
||||
|
||||
MEMORY {
|
||||
ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = 0x08000000 /* 128M */
|
||||
rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = 0x00001000 /* 4k */
|
||||
ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = RAM_SIZE
|
||||
rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = ROM_SIZE
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
@@ -22,9 +34,9 @@ SECTIONS
|
||||
*(.init.*)
|
||||
} > rom
|
||||
|
||||
.vector :
|
||||
{
|
||||
#if XCHAL_HAVE_WINDOWED
|
||||
.vector.window XCHAL_WINDOW_VECTORS_VADDR :
|
||||
{
|
||||
. = XCHAL_WINDOW_OF4_VECOFS;
|
||||
*(.vector.window_overflow_4)
|
||||
. = XCHAL_WINDOW_UF4_VECOFS;
|
||||
@@ -37,41 +49,58 @@ SECTIONS
|
||||
*(.vector.window_overflow_12)
|
||||
. = XCHAL_WINDOW_UF12_VECOFS;
|
||||
*(.vector.window_underflow_12)
|
||||
}
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
|
||||
. = XCHAL_INTLEVEL2_VECOFS;
|
||||
.vector.level2 XCHAL_INTLEVEL2_VECTOR_VADDR :
|
||||
{
|
||||
*(.vector.level2)
|
||||
}
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
|
||||
. = XCHAL_INTLEVEL3_VECOFS;
|
||||
.vector.level3 XCHAL_INTLEVEL3_VECTOR_VADDR :
|
||||
{
|
||||
*(.vector.level3)
|
||||
}
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
|
||||
. = XCHAL_INTLEVEL4_VECOFS;
|
||||
.vector.level4 XCHAL_INTLEVEL4_VECTOR_VADDR :
|
||||
{
|
||||
*(.vector.level4)
|
||||
}
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
|
||||
. = XCHAL_INTLEVEL5_VECOFS;
|
||||
.vector.level5 XCHAL_INTLEVEL5_VECTOR_VADDR :
|
||||
{
|
||||
*(.vector.level5)
|
||||
}
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
|
||||
. = XCHAL_INTLEVEL6_VECOFS;
|
||||
.vector.level6 XCHAL_INTLEVEL6_VECTOR_VADDR :
|
||||
{
|
||||
*(.vector.level6)
|
||||
}
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
|
||||
. = XCHAL_INTLEVEL7_VECOFS;
|
||||
.vector.level7 XCHAL_INTLEVEL7_VECTOR_VADDR :
|
||||
{
|
||||
*(.vector.level7)
|
||||
}
|
||||
#endif
|
||||
|
||||
. = XCHAL_KERNEL_VECOFS;
|
||||
.vector.kernel XCHAL_KERNEL_VECTOR_VADDR :
|
||||
{
|
||||
*(.vector.kernel)
|
||||
. = XCHAL_USER_VECOFS;
|
||||
}
|
||||
.vector.user XCHAL_USER_VECTOR_VADDR :
|
||||
{
|
||||
*(.vector.user)
|
||||
. = XCHAL_DOUBLEEXC_VECOFS;
|
||||
}
|
||||
.vector.double XCHAL_DOUBLEEXC_VECTOR_VADDR :
|
||||
{
|
||||
*(.vector.double)
|
||||
} > ram
|
||||
}
|
||||
|
||||
.vector.text :
|
||||
.vector.text XCHAL_VECBASE_RESET_VADDR + VECTORS_RESERVED_SIZE :
|
||||
{
|
||||
*(.vector.window_overflow_4.*)
|
||||
*(.vector.window_underflow_4.*)
|
||||
|
||||
@@ -23,11 +23,14 @@ main:
|
||||
movi a0, result
|
||||
sub a2, a2, a0
|
||||
movi a3, 0
|
||||
loopnez a2, 1f
|
||||
l8ui a2, a0, 0
|
||||
or a3, a3, a2
|
||||
addi a0, a0, 1
|
||||
beqz a2, 2f
|
||||
1:
|
||||
l8ui a1, a0, 0
|
||||
or a3, a3, a1
|
||||
addi a0, a0, 1
|
||||
addi a2, a2, -1
|
||||
bnez a2, 1b
|
||||
2:
|
||||
exit
|
||||
.endm
|
||||
|
||||
@@ -49,7 +52,9 @@ main:
|
||||
.endm
|
||||
|
||||
.macro test name
|
||||
//print test_\name
|
||||
#ifdef DEBUG
|
||||
print test_\name
|
||||
#endif
|
||||
test_init
|
||||
test_\name:
|
||||
.global test_\name
|
||||
@@ -74,6 +79,9 @@ test_\name:
|
||||
l32i a2, a2, 0
|
||||
movi a3, 1
|
||||
s8i a3, a2, 0
|
||||
#ifdef DEBUG
|
||||
print failed
|
||||
#endif
|
||||
j 99f
|
||||
.endm
|
||||
|
||||
@@ -89,3 +97,26 @@ test_\name:
|
||||
movi a3, \addr
|
||||
s32i a3, a2, 0
|
||||
.endm
|
||||
|
||||
.macro dump r
|
||||
#ifdef DEBUG
|
||||
.data
|
||||
.align 4
|
||||
1: .word 0
|
||||
.text
|
||||
movi a4, 1b
|
||||
s32i a2, a4, 0
|
||||
movi a2, 4
|
||||
movi a3, 1
|
||||
movi a5, 4
|
||||
simcall
|
||||
movi a4, 1b
|
||||
l32i a2, a4, 0
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#define glue(a, b) _glue(a, b)
|
||||
#define _glue(a, b) a ## b
|
||||
|
||||
#define glue3(a, b, c) _glue3(a, b, c)
|
||||
#define _glue3(a, b, c) a ## b ## c
|
||||
|
||||
@@ -84,12 +84,24 @@ test_end
|
||||
|
||||
test bbc
|
||||
movi a2, 0xfffffffd
|
||||
movi a3, 0xffffff01
|
||||
#undef BIT
|
||||
#if XCHAL_HAVE_BE
|
||||
#define BIT 0xfffffffe
|
||||
#else
|
||||
#define BIT 0xffffff01
|
||||
#endif
|
||||
movi a3, BIT
|
||||
bbc a2, a3, 1f
|
||||
test_fail
|
||||
1:
|
||||
movi a2, 8
|
||||
movi a3, 0xffffff03
|
||||
#undef BIT
|
||||
#if XCHAL_HAVE_BE
|
||||
#define BIT 0xfffffffc
|
||||
#else
|
||||
#define BIT 0xffffff03
|
||||
#endif
|
||||
movi a3, BIT
|
||||
bbc a2, a3, 1f
|
||||
j 2f
|
||||
1:
|
||||
@@ -99,11 +111,11 @@ test_end
|
||||
|
||||
test bbci
|
||||
movi a2, 0xfffdffff
|
||||
bbci a2, 17, 1f
|
||||
bbci.l a2, 17, 1f
|
||||
test_fail
|
||||
1:
|
||||
movi a2, 0x00020000
|
||||
bbci a2, 17, 1f
|
||||
bbci.l a2, 17, 1f
|
||||
j 2f
|
||||
1:
|
||||
test_fail
|
||||
@@ -192,12 +204,24 @@ test_end
|
||||
|
||||
test bbs
|
||||
movi a2, 8
|
||||
movi a3, 0xffffff03
|
||||
#undef BIT
|
||||
#if XCHAL_HAVE_BE
|
||||
#define BIT 0xfffffffc
|
||||
#else
|
||||
#define BIT 0xffffff03
|
||||
#endif
|
||||
movi a3, BIT
|
||||
bbs a2, a3, 1f
|
||||
test_fail
|
||||
1:
|
||||
movi a2, 0xfffffffd
|
||||
movi a3, 0xffffff01
|
||||
#undef BIT
|
||||
#if XCHAL_HAVE_BE
|
||||
#define BIT 0xfffffffe
|
||||
#else
|
||||
#define BIT 0xffffff01
|
||||
#endif
|
||||
movi a3, BIT
|
||||
bbs a2, a3, 1f
|
||||
j 2f
|
||||
1:
|
||||
@@ -207,11 +231,11 @@ test_end
|
||||
|
||||
test bbsi
|
||||
movi a2, 0x00020000
|
||||
bbsi a2, 17, 1f
|
||||
bbsi.l a2, 17, 1f
|
||||
test_fail
|
||||
1:
|
||||
movi a2, 0xfffdffff
|
||||
bbsi a2, 17, 1f
|
||||
bbsi.l a2, 17, 1f
|
||||
j 2f
|
||||
1:
|
||||
test_fail
|
||||
|
||||
@@ -2,6 +2,8 @@
|
||||
|
||||
test_suite boolean
|
||||
|
||||
#if XCHAL_HAVE_BOOLEANS
|
||||
|
||||
test all4
|
||||
movi a2, 0xfec0
|
||||
wsr a2, br
|
||||
@@ -20,4 +22,6 @@ test all4
|
||||
assert eq, a2, a3
|
||||
test_end
|
||||
|
||||
#endif
|
||||
|
||||
test_suite_end
|
||||
|
||||
@@ -1,10 +1,13 @@
|
||||
#include "macros.inc"
|
||||
|
||||
#define debug_level 6
|
||||
#define debug_vector level6
|
||||
|
||||
test_suite break
|
||||
|
||||
#if XCHAL_HAVE_DEBUG
|
||||
|
||||
#define debug_level XCHAL_DEBUGLEVEL
|
||||
#define debug_vector glue(level, XCHAL_DEBUGLEVEL)
|
||||
#define EPC_DEBUG glue(epc, XCHAL_DEBUGLEVEL)
|
||||
|
||||
test break
|
||||
set_vector debug_vector, 0
|
||||
rsil a2, debug_level
|
||||
@@ -21,7 +24,7 @@ test break
|
||||
and a2, a2, a3
|
||||
movi a3, 0x10 | debug_level
|
||||
assert eq, a2, a3
|
||||
rsr a2, epc6
|
||||
rsr a2, EPC_DEBUG
|
||||
movi a3, 1b
|
||||
assert eq, a2, a3
|
||||
rsr a2, debugcause
|
||||
@@ -45,7 +48,7 @@ test breakn
|
||||
and a2, a2, a3
|
||||
movi a3, 0x10 | debug_level
|
||||
assert eq, a2, a3
|
||||
rsr a2, epc6
|
||||
rsr a2, EPC_DEBUG
|
||||
movi a3, 1b
|
||||
assert eq, a2, a3
|
||||
rsr a2, debugcause
|
||||
@@ -53,6 +56,7 @@ test breakn
|
||||
assert eq, a2, a3
|
||||
test_end
|
||||
|
||||
#if XCHAL_NUM_IBREAK
|
||||
test ibreak
|
||||
set_vector debug_vector, 0
|
||||
rsil a2, debug_level
|
||||
@@ -83,7 +87,7 @@ test ibreak
|
||||
and a2, a2, a3
|
||||
movi a3, 0x10 | debug_level
|
||||
assert eq, a2, a3
|
||||
rsr a2, epc6
|
||||
rsr a2, EPC_DEBUG
|
||||
movi a3, 1b
|
||||
assert eq, a2, a3
|
||||
rsr a2, debugcause
|
||||
@@ -110,7 +114,7 @@ test ibreak_remove
|
||||
and a2, a2, a3
|
||||
movi a3, 0x10 | debug_level
|
||||
assert eq, a2, a3
|
||||
rsr a2, epc6
|
||||
rsr a2, EPC_DEBUG
|
||||
movi a3, 2b
|
||||
assert eq, a2, a3
|
||||
rsr a2, debugcause
|
||||
@@ -141,6 +145,7 @@ test ibreak_priority
|
||||
movi a3, 0x2
|
||||
assert eq, a2, a3
|
||||
test_end
|
||||
#endif
|
||||
|
||||
test icount
|
||||
set_vector debug_vector, 2f
|
||||
@@ -158,7 +163,7 @@ test icount
|
||||
2:
|
||||
movi a2, 0
|
||||
wsr a2, icountlevel
|
||||
rsr a2, epc6
|
||||
rsr a2, EPC_DEBUG
|
||||
movi a3, 1b
|
||||
assert eq, a2, a3
|
||||
rsr a2, debugcause
|
||||
@@ -167,7 +172,7 @@ test icount
|
||||
test_end
|
||||
|
||||
.macro check_dbreak dr
|
||||
rsr a2, epc6
|
||||
rsr a2, EPC_DEBUG
|
||||
movi a3, 1b
|
||||
assert eq, a2, a3
|
||||
rsr a2, debugcause
|
||||
@@ -194,6 +199,7 @@ test_end
|
||||
reset_ps
|
||||
.endm
|
||||
|
||||
#if XCHAL_NUM_DBREAK
|
||||
test dbreak_exact
|
||||
dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
|
||||
dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
|
||||
@@ -253,5 +259,8 @@ test dbreak_invalid
|
||||
dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
|
||||
dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i
|
||||
test_end
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
test_suite_end
|
||||
|
||||
@@ -7,6 +7,8 @@
|
||||
|
||||
test_suite cache
|
||||
|
||||
#if XCHAL_HAVE_PTP_MMU
|
||||
|
||||
.macro pf_op op
|
||||
\op a2, 0
|
||||
\op a3, 0
|
||||
@@ -18,14 +20,23 @@ test prefetch
|
||||
movi a3, 0xd8000000 /* non-cacheable */
|
||||
movi a4, 0x00001235 /* unmapped */
|
||||
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
pf_op dpfr
|
||||
pf_op dpfro
|
||||
pf_op dpfw
|
||||
pf_op dpfwo
|
||||
#endif
|
||||
#ifdef XCHAL_ICACHE_SIZE
|
||||
pf_op ipf
|
||||
|
||||
#endif
|
||||
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
|
||||
#if XCHAL_DCACHE_LINE_LOCKABLE
|
||||
dpfl a2, 0
|
||||
#endif
|
||||
#if XCHAL_ICACHE_LINE_LOCKABLE
|
||||
ipfl a2, 0
|
||||
#endif
|
||||
#endif
|
||||
test_end
|
||||
|
||||
.macro cache_fault op, addr, exc_code
|
||||
@@ -46,10 +57,16 @@ test_end
|
||||
assert eq, a2, a3
|
||||
.endm
|
||||
|
||||
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
|
||||
|
||||
#if XCHAL_DCACHE_LINE_LOCKABLE
|
||||
test dpfl_tlb_miss
|
||||
cache_fault dpfl, 0x00002345, 24
|
||||
test_end
|
||||
#endif
|
||||
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
#if XCHAL_DCACHE_IS_WRITEBACK
|
||||
test dhwb_tlb_miss
|
||||
cache_fault dhwb, 0x00002345, 24
|
||||
test_end
|
||||
@@ -57,16 +74,21 @@ test_end
|
||||
test dhwbi_tlb_miss
|
||||
cache_fault dhwbi, 0x00002345, 24
|
||||
test_end
|
||||
#endif
|
||||
|
||||
test dhi_tlb_miss
|
||||
cache_fault dhi, 0x00002345, 24
|
||||
test_end
|
||||
|
||||
#if XCHAL_DCACHE_LINE_LOCKABLE
|
||||
test dhu_tlb_miss
|
||||
cache_fault dhu, 0x00002345, 24
|
||||
test_end
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#if XCHAL_ICACHE_SIZE
|
||||
#if XCHAL_ICACHE_LINE_LOCKABLE
|
||||
test ipfl_tlb_miss
|
||||
cache_fault ipfl, 0x00002345, 16
|
||||
test_end
|
||||
@@ -74,24 +96,40 @@ test_end
|
||||
test ihu_tlb_miss
|
||||
cache_fault ihu, 0x00002345, 16
|
||||
test_end
|
||||
#endif
|
||||
|
||||
test ihi_tlb_miss
|
||||
cache_fault ihi, 0x00002345, 16
|
||||
test_end
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
test_suite_end
|
||||
|
||||
.macro cache_all op1, op2, size, linesize
|
||||
movi a2, 0
|
||||
movi a3, \size
|
||||
1:
|
||||
\op1 a2, 0
|
||||
\op2 a2, 0
|
||||
addi a2, a2, \linesize
|
||||
bltu a2, a3, 1b
|
||||
.endm
|
||||
|
||||
cache_unlock_invalidate:
|
||||
cache_all diu, dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE
|
||||
cache_all iiu, iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
movi a2, 0
|
||||
movi a3, XCHAL_DCACHE_SIZE
|
||||
1:
|
||||
#if XCHAL_DCACHE_LINE_LOCKABLE
|
||||
diu a2, 0
|
||||
#endif
|
||||
dii a2, 0
|
||||
addi a2, a2, XCHAL_DCACHE_LINESIZE
|
||||
bltu a2, a3, 1b
|
||||
#endif
|
||||
#if XCHAL_ICACHE_SIZE
|
||||
movi a2, 0
|
||||
movi a3, XCHAL_ICACHE_SIZE
|
||||
1:
|
||||
#if XCHAL_ICACHE_LINE_LOCKABLE
|
||||
iiu a2, 0
|
||||
#endif
|
||||
iii a2, 0
|
||||
addi a2, a2, XCHAL_ICACHE_LINESIZE
|
||||
bltu a2, a3, 1b
|
||||
#endif
|
||||
ret
|
||||
|
||||
@@ -2,6 +2,8 @@
|
||||
|
||||
test_suite clamps
|
||||
|
||||
#if XCHAL_HAVE_CLAMPS
|
||||
|
||||
test clamps
|
||||
movi a2, 0
|
||||
movi a3, 0
|
||||
@@ -39,4 +41,6 @@ test clamps
|
||||
assert eq, a3, a2
|
||||
test_end
|
||||
|
||||
#endif
|
||||
|
||||
test_suite_end
|
||||
|
||||
@@ -0,0 +1,60 @@
|
||||
#include "macros.inc"
|
||||
|
||||
test_suite flix
|
||||
|
||||
#if XCHAL_HAVE_FLIX3
|
||||
|
||||
test misc
|
||||
{
|
||||
mov a3, a4
|
||||
mov a2, a3
|
||||
nop
|
||||
}
|
||||
{
|
||||
nop
|
||||
bne.w18 a2, a3, 1f
|
||||
}
|
||||
movi a2, 1f
|
||||
{
|
||||
mov a2, a3
|
||||
mov a3, a2
|
||||
nop
|
||||
}
|
||||
{
|
||||
l32i a2, a3, 0
|
||||
add a4, a4, a2
|
||||
nop
|
||||
}
|
||||
{
|
||||
mov a3, a4
|
||||
jx a3
|
||||
nop
|
||||
}
|
||||
1:
|
||||
test_end
|
||||
|
||||
test sum
|
||||
|
||||
movi a2, 0
|
||||
movi a3, 2f
|
||||
movi a4, 0
|
||||
movi a5, 4
|
||||
|
||||
loop a5, 1f
|
||||
{
|
||||
l32i a2, a3, 0
|
||||
addi a3, a3, 4
|
||||
add a4, a4, a2
|
||||
}
|
||||
1:
|
||||
add a4, a4, a2
|
||||
assert eqi, a4, 10
|
||||
.data
|
||||
2:
|
||||
.word 1, 2, 3, 4
|
||||
.previous
|
||||
test_end
|
||||
|
||||
#endif
|
||||
|
||||
test_suite_end
|
||||
@@ -0,0 +1,173 @@
|
||||
#include "macros.inc"
|
||||
|
||||
test_suite fp0_arith
|
||||
|
||||
#if XCHAL_HAVE_FP
|
||||
|
||||
.macro movfp fr, v
|
||||
movi a2, \v
|
||||
wfr \fr, a2
|
||||
.endm
|
||||
|
||||
.macro check_res fr, r
|
||||
rfr a2, \fr
|
||||
dump a2
|
||||
movi a3, \r
|
||||
assert eq, a2, a3
|
||||
rur a2, fsr
|
||||
assert eqi, a2, 0
|
||||
.endm
|
||||
|
||||
.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r
|
||||
movi a2, 0
|
||||
wur a2, fsr
|
||||
movfp \fr0, \v0
|
||||
movfp \fr1, \v1
|
||||
\op \fr2, \fr0, \fr1
|
||||
check_res \fr2, \r
|
||||
.endm
|
||||
|
||||
.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r
|
||||
movi a2, 0
|
||||
wur a2, fsr
|
||||
movfp \fr0, \v0
|
||||
movfp \fr1, \v1
|
||||
movfp \fr2, \v2
|
||||
\op \fr0, \fr1, \fr2
|
||||
check_res \fr3, \r
|
||||
.endm
|
||||
|
||||
.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r
|
||||
movi a2, \rm
|
||||
wur a2, fcr
|
||||
test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
|
||||
movi a2, (\rm) | 0x7c
|
||||
wur a2, fcr
|
||||
test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
|
||||
.endm
|
||||
|
||||
.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r
|
||||
movi a2, \rm
|
||||
wur a2, fcr
|
||||
test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
|
||||
movi a2, (\rm) | 0x7c
|
||||
wur a2, fcr
|
||||
test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
|
||||
.endm
|
||||
|
||||
.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3
|
||||
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0
|
||||
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1
|
||||
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2
|
||||
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3
|
||||
.endm
|
||||
|
||||
.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3
|
||||
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0
|
||||
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1
|
||||
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2
|
||||
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3
|
||||
.endm
|
||||
|
||||
.macro test_op2_cpe op
|
||||
set_vector kernel, 2f
|
||||
movi a2, 0
|
||||
wsr a2, cpenable
|
||||
1:
|
||||
\op f2, f0, f1
|
||||
test_fail
|
||||
2:
|
||||
rsr a2, excvaddr
|
||||
movi a3, 1b
|
||||
assert eq, a2, a3
|
||||
rsr a2, exccause
|
||||
movi a3, 32
|
||||
assert eq, a2, a3
|
||||
|
||||
set_vector kernel, 0
|
||||
movi a2, 1
|
||||
wsr a2, cpenable
|
||||
.endm
|
||||
|
||||
test add_s
|
||||
movi a2, 1
|
||||
wsr a2, cpenable
|
||||
|
||||
test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \
|
||||
0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001
|
||||
test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \
|
||||
0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002
|
||||
|
||||
/* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
|
||||
test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \
|
||||
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
|
||||
test_end
|
||||
|
||||
test add_s_inf
|
||||
/* 1 + +inf = +inf */
|
||||
test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \
|
||||
0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000
|
||||
|
||||
/* +inf + -inf = default NaN */
|
||||
test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \
|
||||
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
|
||||
test_end
|
||||
|
||||
test add_s_nan
|
||||
/* 1 + NaN = NaN */
|
||||
test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
|
||||
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
|
||||
test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
|
||||
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
|
||||
|
||||
/* NaN1 + NaN2 = NaN1 */
|
||||
test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
|
||||
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
|
||||
test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
|
||||
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
|
||||
test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
|
||||
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
|
||||
test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
|
||||
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
|
||||
test_end
|
||||
|
||||
test sub_s
|
||||
test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \
|
||||
0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000
|
||||
test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \
|
||||
0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001
|
||||
|
||||
/* norm - norm = denorm */
|
||||
test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \
|
||||
0x00000001, 0x00000001, 0x00000001, 0x00000001
|
||||
test_end
|
||||
|
||||
test mul_s
|
||||
test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \
|
||||
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
|
||||
|
||||
/* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
|
||||
test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \
|
||||
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
|
||||
/* min norm * min norm = 0/denorm */
|
||||
test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \
|
||||
0x00000000, 0x00000000, 0x00000001, 0x00000000
|
||||
|
||||
/* inf * 0 = default NaN */
|
||||
test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \
|
||||
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
|
||||
test_end
|
||||
|
||||
test madd_s
|
||||
test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \
|
||||
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
|
||||
test_end
|
||||
|
||||
test msub_s
|
||||
test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
|
||||
0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001
|
||||
test_end
|
||||
|
||||
#endif
|
||||
|
||||
test_suite_end
|
||||
@@ -0,0 +1,304 @@
|
||||
#include "macros.inc"
|
||||
|
||||
test_suite fp0_conv
|
||||
|
||||
#if XCHAL_HAVE_FP
|
||||
|
||||
.macro movfp fr, v
|
||||
movi a2, \v
|
||||
wfr \fr, a2
|
||||
.endm
|
||||
|
||||
.macro test_ftoi_ex op, r0, fr0, v, c, r
|
||||
movi a2, 0
|
||||
wur a2, fsr
|
||||
movfp \fr0, \v
|
||||
\op \r0, \fr0, \c
|
||||
dump \r0
|
||||
movi a3, \r
|
||||
assert eq, \r0, a3
|
||||
rur a2, fsr
|
||||
assert eqi, a2, 0
|
||||
.endm
|
||||
|
||||
.macro test_ftoi op, r0, fr0, v, c, r
|
||||
movi a2, 0
|
||||
wur a2, fcr
|
||||
test_ftoi_ex \op, \r0, \fr0, \v, \c, \r
|
||||
movi a2, 0x7c
|
||||
wur a2, fcr
|
||||
test_ftoi_ex \op, \r0, \fr0, \v, \c, \r
|
||||
.endm
|
||||
|
||||
|
||||
.macro test_itof_ex op, fr0, ar0, v, c, r
|
||||
movi a2, 0
|
||||
wur a2, fsr
|
||||
movi \ar0, \v
|
||||
\op \fr0, \ar0, \c
|
||||
|
||||
rfr a2, \fr0
|
||||
dump a2
|
||||
movi a3, \r
|
||||
assert eq, a2, a3
|
||||
rur a2, fsr
|
||||
assert eqi, a2, 0
|
||||
.endm
|
||||
|
||||
.macro test_itof_rm op, fr0, ar0, v, c, rm, r
|
||||
movi a2, \rm
|
||||
wur a2, fcr
|
||||
test_itof_ex \op, \fr0, \ar0, \v, \c, \r
|
||||
movi a2, (\rm) | 0x7c
|
||||
wur a2, fcr
|
||||
test_itof_ex \op, \fr0, \ar0, \v, \c, \r
|
||||
.endm
|
||||
|
||||
.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3
|
||||
test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0
|
||||
test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1
|
||||
test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2
|
||||
test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3
|
||||
.endm
|
||||
|
||||
test round_s
|
||||
movi a2, 1
|
||||
wsr a2, cpenable
|
||||
|
||||
/* NaN */
|
||||
test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff
|
||||
test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff
|
||||
|
||||
/* -inf */
|
||||
test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000
|
||||
|
||||
/* negative overflow */
|
||||
test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000
|
||||
test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000
|
||||
test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080
|
||||
|
||||
/* negative */
|
||||
test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
|
||||
test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */
|
||||
test_ftoi round.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
|
||||
test_ftoi round.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
|
||||
test_ftoi round.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */
|
||||
test_ftoi round.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
|
||||
|
||||
/* positive */
|
||||
test_ftoi round.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
|
||||
test_ftoi round.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */
|
||||
test_ftoi round.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
|
||||
test_ftoi round.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
|
||||
test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */
|
||||
test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
|
||||
|
||||
/* positive overflow */
|
||||
test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80
|
||||
test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff
|
||||
test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff
|
||||
|
||||
/* +inf */
|
||||
test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff
|
||||
|
||||
/* NaN */
|
||||
test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff
|
||||
test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
|
||||
test_end
|
||||
|
||||
test trunc_s
|
||||
/* NaN */
|
||||
test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff
|
||||
test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff
|
||||
|
||||
/* -inf */
|
||||
test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000
|
||||
|
||||
/* negative overflow */
|
||||
test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000
|
||||
test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000
|
||||
test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080
|
||||
|
||||
/* negative */
|
||||
test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
|
||||
test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
|
||||
test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
|
||||
test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
|
||||
test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
|
||||
test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
|
||||
|
||||
/* positive */
|
||||
test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
|
||||
test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
|
||||
test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
|
||||
test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
|
||||
test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
|
||||
test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
|
||||
|
||||
/* positive overflow */
|
||||
test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80
|
||||
test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff
|
||||
test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff
|
||||
|
||||
/* +inf */
|
||||
test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff
|
||||
|
||||
/* NaN */
|
||||
test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff
|
||||
test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
|
||||
test_end
|
||||
|
||||
test floor_s
|
||||
/* NaN */
|
||||
test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff
|
||||
test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff
|
||||
|
||||
/* -inf */
|
||||
test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000
|
||||
|
||||
/* negative overflow */
|
||||
test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000
|
||||
test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000
|
||||
test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080
|
||||
|
||||
/* negative */
|
||||
test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3 /* -1.25 * 2 */
|
||||
test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */
|
||||
test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
|
||||
test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
|
||||
test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */
|
||||
test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1 /* -0.5 */
|
||||
|
||||
/* positive */
|
||||
test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
|
||||
test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
|
||||
test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
|
||||
test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
|
||||
test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
|
||||
test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
|
||||
|
||||
/* positive overflow */
|
||||
test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80
|
||||
test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff
|
||||
test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff
|
||||
|
||||
/* +inf */
|
||||
test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff
|
||||
|
||||
/* NaN */
|
||||
test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff
|
||||
test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
|
||||
test_end
|
||||
|
||||
test ceil_s
|
||||
/* NaN */
|
||||
test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff
|
||||
test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff
|
||||
|
||||
/* -inf */
|
||||
test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000
|
||||
|
||||
/* negative overflow */
|
||||
test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000
|
||||
test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000
|
||||
test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080
|
||||
|
||||
/* negative */
|
||||
test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
|
||||
test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
|
||||
test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
|
||||
test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
|
||||
test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
|
||||
test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
|
||||
|
||||
/* positive */
|
||||
test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1 /* 0.5 */
|
||||
test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */
|
||||
test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
|
||||
test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
|
||||
test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */
|
||||
test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3 /* 1.25 * 2 */
|
||||
|
||||
/* positive overflow */
|
||||
test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80
|
||||
test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff
|
||||
test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff
|
||||
|
||||
/* +inf */
|
||||
test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff
|
||||
|
||||
/* NaN */
|
||||
test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff
|
||||
test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
|
||||
test_end
|
||||
|
||||
test utrunc_s
|
||||
/* NaN */
|
||||
test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff
|
||||
test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff
|
||||
|
||||
/* -inf */
|
||||
test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000
|
||||
|
||||
/* negative overflow */
|
||||
test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000
|
||||
test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000
|
||||
test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080
|
||||
|
||||
/* negative */
|
||||
test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
|
||||
test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
|
||||
test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
|
||||
test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
|
||||
test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
|
||||
test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
|
||||
|
||||
/* positive */
|
||||
test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
|
||||
test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
|
||||
test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
|
||||
test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
|
||||
test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
|
||||
test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
|
||||
|
||||
/* positive overflow */
|
||||
test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80
|
||||
test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000
|
||||
test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00
|
||||
test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff
|
||||
|
||||
/* +inf */
|
||||
test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff
|
||||
|
||||
/* NaN */
|
||||
test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff
|
||||
test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff
|
||||
test_end
|
||||
|
||||
test float_s
|
||||
test_itof float.s, f0, a2, -1, 0, \
|
||||
0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000
|
||||
test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0
|
||||
test_itof float.s, f0, a2, 1, 1, \
|
||||
0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000
|
||||
test_itof float.s, f0, a2, 1, 0, \
|
||||
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000
|
||||
test_itof float.s, f0, a2, 0x7fffffff, 0, \
|
||||
0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff
|
||||
test_end
|
||||
|
||||
test ufloat_s
|
||||
test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0
|
||||
test_itof ufloat.s, f0, a2, 1, 1, \
|
||||
0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000
|
||||
test_itof ufloat.s, f0, a2, 1, 0, \
|
||||
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000
|
||||
test_itof ufloat.s, f0, a2, 0x7fffffff, 0, \
|
||||
0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff
|
||||
test_itof ufloat.s, f0, a2, 0xffffffff, 0, \
|
||||
0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff
|
||||
test_end
|
||||
|
||||
#endif
|
||||
|
||||
test_suite_end
|
||||
@@ -0,0 +1,141 @@
|
||||
#include "macros.inc"
|
||||
|
||||
test_suite fp1
|
||||
|
||||
#if XCHAL_HAVE_FP
|
||||
|
||||
.macro movfp fr, v
|
||||
movi a2, \v
|
||||
wfr \fr, a2
|
||||
.endm
|
||||
|
||||
.macro test_ord_ex op, br, fr0, fr1, v0, v1, r
|
||||
movi a2, 0
|
||||
wur a2, fsr
|
||||
movfp \fr0, \v0
|
||||
movfp \fr1, \v1
|
||||
\op \br, \fr0, \fr1
|
||||
movi a2, 0
|
||||
movi a3, 1
|
||||
movt a2, a3, \br
|
||||
assert eqi, a2, \r
|
||||
rur a2, fsr
|
||||
assert eqi, a2, 0
|
||||
.endm
|
||||
|
||||
.macro test_ord op, br, fr0, fr1, v0, v1, r
|
||||
movi a2, 0
|
||||
wur a2, fcr
|
||||
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
|
||||
movi a2, 0x7c
|
||||
wur a2, fcr
|
||||
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
|
||||
.endm
|
||||
|
||||
.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI
|
||||
test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa
|
||||
test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab
|
||||
test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba
|
||||
test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI
|
||||
test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa
|
||||
test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN
|
||||
test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN
|
||||
test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN
|
||||
test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN
|
||||
test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na
|
||||
test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na
|
||||
test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na
|
||||
test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na
|
||||
test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II
|
||||
test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN
|
||||
test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI
|
||||
.endm
|
||||
|
||||
test un_s
|
||||
movi a2, 1
|
||||
wsr a2, cpenable
|
||||
test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1
|
||||
test_end
|
||||
|
||||
test oeq_s
|
||||
test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0
|
||||
test_end
|
||||
|
||||
test ueq_s
|
||||
test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1
|
||||
test_end
|
||||
|
||||
test olt_s
|
||||
test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0
|
||||
test_end
|
||||
|
||||
test ult_s
|
||||
test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1
|
||||
test_end
|
||||
|
||||
test ole_s
|
||||
test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0
|
||||
test_end
|
||||
|
||||
test ule_s
|
||||
test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1
|
||||
test_end
|
||||
|
||||
.macro test_cond op, fr0, fr1, cr, v0, v1, r
|
||||
movfp \fr0, \v0
|
||||
movfp \fr1, \v1
|
||||
\op \fr0, \fr1, \cr
|
||||
rfr a2, \fr0
|
||||
movi a3, \r
|
||||
assert eq, a2, a3
|
||||
.endm
|
||||
|
||||
test moveqz_s
|
||||
movi a3, 0
|
||||
test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
|
||||
movi a3, 1
|
||||
test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0
|
||||
test_end
|
||||
|
||||
test movnez_s
|
||||
movi a3, 0
|
||||
test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0
|
||||
movi a3, 1
|
||||
test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
|
||||
test_end
|
||||
|
||||
test movltz_s
|
||||
movi a3, -1
|
||||
test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
|
||||
movi a3, 0
|
||||
test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
|
||||
movi a3, 1
|
||||
test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
|
||||
test_end
|
||||
|
||||
test movgez_s
|
||||
movi a3, -1
|
||||
test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0
|
||||
movi a3, 0
|
||||
test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
|
||||
movi a3, 1
|
||||
test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
|
||||
test_end
|
||||
|
||||
test movf_s
|
||||
olt.s b0, f0, f0
|
||||
test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000
|
||||
ueq.s b0, f0, f0
|
||||
test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0
|
||||
test_end
|
||||
|
||||
test movt_s
|
||||
ueq.s b0, f0, f0
|
||||
test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000
|
||||
olt.s b0, f0, f0
|
||||
test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0
|
||||
test_end
|
||||
|
||||
#endif
|
||||
|
||||
test_suite_end
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user