mirror of
https://github.com/izzy2lost/xemu.git
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Merge tag 'pull-target-arm-20251007' of https://gitlab.com/pm215/qemu into staging
target-arm queue: * target/arm: Don't set HCR.RW for AArch32 only CPUs * new board model: amd-versal2-virt * xlnx-zynqmp: model the GIC for the Cortex-R5 RPU cluster * hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header * Emulate FEAT_RME_GPC2 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmjlH0AZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gvaD/92LoDOIPQYCw72nwr/hiC8 # DAJddqKL1VvirtcrTuwytB1+w/tM2FdNx4ADzryHiNEDay2gXl0g4X4Pq6QFwu8B # u2gxQhZZc1XWJgvX06CDJZPIUoazQgri21359c+9mJrI94igq1Gisj+KJ2gaMJ/J # hrtsbovKuuKwMyCwCSK0hqvrUFyechfvJ0MzwVXyHn80lvSeYVbHf8ahdM72Lqdt # PFJuM6hM/bBbclMRrcgRZJ3gi6HGHdKQ+LyYeQkvpHtaO3FWBgyJE7dtzs3mj4c9 # zw7kFJi56/19G6Fx3CESCIjoUQxLPZ1wDljqcQ9+mIwhQ4Dm7cy/D5z018TotIws # mNLpMyEYiyC6dl1TxaJkha9jB6MB+nlglpbOGyRDYD1xwV8o5lidAahKxtmZUrGp # sErUqCL5f+e/inwkFLxKrA2Hk1mjFDzf9/aEF/CyA30JYzRrhCfMoffiqtpPpU5D # +OD1OAnj+W7HSBzO6N2I+4bfsaILw61YvckaBbO9+Br9yx8QseXHwXGh+RgsMhY4 # yJdde//tRusT32SAVoQKCMTJM5Rkrt4wu1D0F4LFL/4rJaqkAhqirNP4v5JEjrlk # UDNa19E1TfmLbCG0TfQBWd3kwLYizqjTO0006jpTMX+KIu5aInEIHzzVrKEKK4t5 # fCw9fUM8T4fSTV71wJ/28Q== # =jFB3 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Oct 2025 07:10:08 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [unknown] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [unknown] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [unknown] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20251007' of https://gitlab.com/pm215/qemu: (62 commits) target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rme target/arm: Implement APPSAA target/arm: Fix GPT fault type for address outside PPS target/arm: Implement SPAD, NSPAD, RLPAD target/arm: Implement GPT_NonSecureOnly target/arm: GPT_Secure is reserved without FEAT_SEL2 target/arm: Add cur_space to S1Translate target/arm: Enable FEAT_RME_GPC2 bits in gpccr_write target/arm: Add GPCCR fields from ARM revision L.b target/arm: Add isar feature test for FEAT_RME_GPC2 hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5 hw/arm/xlnx-zynqmp: introduce helper to compute RPU number hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header tests/functional/test_aarch64_xlnx_versal: test the versal2 machine hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine docs/system/arm/xlnx-versal-virt: add a note about dumpdtb docs/system/arm/xlnx-versal-virt: update supported devices hw/arm/xlnx-versal-virt: tidy up hw/arm/xlnx-versal-virt: split into base/concrete classes ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
@@ -1006,7 +1006,6 @@ S: Odd Fixes
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F: hw/arm/collie.c
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F: hw/arm/strongarm*
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F: hw/gpio/zaurus.c
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F: include/hw/arm/sharpsl.h
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F: docs/system/arm/collie.rst
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F: tests/functional/arm/test_collie.py
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@@ -120,6 +120,7 @@ the following architecture extensions:
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- FEAT_RASv1p1 (RAS Extension v1.1)
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- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
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- FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental)
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- FEAT_RME_GPC2 (RME Granule Protection Check 2 Extension)
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- FEAT_RNG (Random number generator)
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- FEAT_RPRES (Increased precision of FRECPE and FRSQRTE)
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- FEAT_S2FWB (Stage 2 forced Write-Back)
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@@ -1,29 +1,37 @@
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Xilinx Versal Virt (``xlnx-versal-virt``)
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=========================================
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AMD Versal Virt (``amd-versal-virt``, ``amd-versal2-virt``)
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===========================================================
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Xilinx Versal is a family of heterogeneous multi-core SoCs
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AMD Versal is a family of heterogeneous multi-core SoCs
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(System on Chip) that combine traditional hardened CPUs and I/O
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peripherals in a Processing System (PS) with runtime programmable
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FPGA logic (PL) and an Artificial Intelligence Engine (AIE).
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QEMU implements the following Versal SoCs variants:
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- Versal (the ``amd-versal-virt`` machine, the alias ``xlnx-versal-virt`` is
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kept for backward compatibility)
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- Versal Gen 2 (the ``amd-versal2-virt`` machine)
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More details here:
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https://www.xilinx.com/products/silicon-devices/acap/versal.html
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https://www.amd.com/en/products/adaptive-socs-and-fpgas/versal.html
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The family of Versal SoCs share a single architecture but come in
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different parts with different speed grades, amounts of PL and
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other differences.
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The Xilinx Versal Virt board in QEMU is a model of a virtual board
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The AMD Versal Virt board in QEMU is a model of a virtual board
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(does not exist in reality) with a virtual Versal SoC without I/O
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limitations. Currently, we support the following cores and devices:
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Versal
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""""""
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Implemented CPU cores:
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- 2 ACPUs (ARM Cortex-A72)
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- 2 ACPUs (ARM Cortex-A72) with their GICv3 and ITS
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- 2 RCPUs (ARM Cortex-R5F) with their GICv2
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Implemented devices:
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- Interrupt controller (ARM GICv3)
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- 2 UARTs (ARM PL011)
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- An RTC (Versal built-in)
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- 2 GEMs (Cadence MACB Ethernet MACs)
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@@ -35,6 +43,31 @@ Implemented devices:
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- BBRAM (36 bytes of Battery-backed RAM)
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- eFUSE (3072 bytes of one-time field-programmable bit array)
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- 2 CANFDs
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- USB controller
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- OSPI controller
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- TRNG controller
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Versal Gen 2
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""""""""""""
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Implemented CPU cores:
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- 8 ACPUs (ARM Cortex-A78AE) with their GICv3 and ITS
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- 10 RCPUs (ARM Cortex-R52) with their GICv3 (one per cluster)
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Implemented devices:
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- 2 UARTs (ARM PL011)
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- An RTC (Versal built-in)
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- 3 GEMs (Cadence MACB Ethernet MACs)
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- 8 ADMA (Xilinx zDMA) channels
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- 2 SD Controllers
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- OCM (256KB of On Chip Memory)
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- DDR memory
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- BBRAM (36 bytes of Battery-backed RAM)
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- 2 CANFDs
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- 2 USB controllers
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- OSPI controller
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- TRNG controller
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QEMU does not yet model any other devices, including the PL and the AI Engine.
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@@ -44,8 +77,8 @@ Other differences between the hardware and the QEMU model:
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``-m`` argument. If a DTB is provided on the command line then QEMU will
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edit it to include suitable entries describing the Versal DDR memory ranges.
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- QEMU provides 8 virtio-mmio virtio transports; these start at
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address ``0xa0000000`` and have IRQs from 111 and upwards.
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- QEMU provides 8 virtio-mmio virtio transports. They use reserved memory
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regions and IRQ pins to avoid conflicts with real SoC peripherals.
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Running
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"""""""
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@@ -58,7 +91,13 @@ When loading an OS, QEMU generates a DTB and selects an appropriate address
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where it gets loaded. This DTB will be passed to the kernel in register x0.
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If there's no ``-kernel`` option, we generate a DTB and place it at 0x1000
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for boot-loaders or firmware to pick it up.
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for boot-loaders or firmware to pick it up. To dump and observe the generated
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DTB, one can use the ``dumpdtb`` machine option:
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.. code-block:: bash
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$ qemu-system-aarch64 -M amd-versal-virt,dumpdtb=example.dtb -m 2G
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If users want to provide their own DTB, they can use the ``-dtb`` option.
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These DTBs will have their memory nodes modified to match QEMU's
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@@ -74,7 +113,7 @@ Direct Linux boot of a generic ARM64 upstream Linux kernel:
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.. code-block:: bash
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$ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \
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$ qemu-system-aarch64 -M amd-versal-virt -m 2G \
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-serial mon:stdio -display none \
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-kernel arch/arm64/boot/Image \
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-nic user -nic user \
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@@ -87,7 +126,7 @@ Direct Linux boot of PetaLinux 2019.2:
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.. code-block:: bash
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$ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \
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$ qemu-system-aarch64 -M amd-versal-virt -m 2G \
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-serial mon:stdio -display none \
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-kernel petalinux-v2019.2/Image \
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-append "rdinit=/sbin/init console=ttyAMA0,115200n8 earlycon=pl011,mmio,0xFF000000,115200n8" \
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@@ -100,7 +139,7 @@ version of ATF tries to configure the CCI which we don't model) and U-boot:
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.. code-block:: bash
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$ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \
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$ qemu-system-aarch64 -M amd-versal-virt -m 2G \
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-serial stdio -display none \
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-device loader,file=petalinux-v2018.3/bl31.elf,cpu-num=0 \
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-device loader,file=petalinux-v2019.2/u-boot.elf \
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@@ -125,7 +164,7 @@ Boot Linux as DOM0 on Xen via U-Boot:
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.. code-block:: bash
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$ qemu-system-aarch64 -M xlnx-versal-virt -m 4G \
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$ qemu-system-aarch64 -M amd-versal-virt -m 4G \
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-serial stdio -display none \
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-device loader,file=petalinux-v2019.2/u-boot.elf,cpu-num=0 \
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-device loader,addr=0x30000000,file=linux/2018-04-24/xen \
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@@ -153,7 +192,7 @@ Boot Linux as Dom0 on Xen via ARM Trusted Firmware and U-Boot:
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.. code-block:: bash
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$ qemu-system-aarch64 -M xlnx-versal-virt -m 4G \
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$ qemu-system-aarch64 -M amd-versal-virt -m 4G \
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-serial stdio -display none \
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-device loader,file=petalinux-v2018.3/bl31.elf,cpu-num=0 \
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-device loader,file=petalinux-v2019.2/u-boot.elf \
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@@ -201,6 +240,11 @@ To use a different index value, N, from default of 0, add:
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eFUSE File Backend
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""""""""""""""""""
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.. note::
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The eFUSE device is not implemented in the Versal Gen 2 QEMU model
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yet.
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eFUSE can have an optional file backend, which must be a seekable
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binary file with a size of 3072 bytes or larger. A file with all
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binary 0s is a 'blank'.
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@@ -227,7 +271,7 @@ To use a different index value, N, from default of 1, add:
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is highly recommended (albeit with usage complexity).
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Better yet, do not use actual product data when running guest image
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on this Xilinx Versal Virt board.
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on this AMD Versal Virt board.
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Using CANFDs for Versal Virt
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""""""""""""""""""""""""""""
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@@ -258,3 +302,7 @@ To connect CANFD0 and CANFD1 to host machine's CAN interface can0:
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-object can-bus,id=canbus -machine canbus0=canbus -machine canbus1=canbus
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-object can-host-socketcan,id=canhost0,if=can0,canbus=canbus
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.. note::
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Versal Gen 2 has 4 CAN controllers. ``canbus0`` to ``canbus3`` can
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be specified on the command line.
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+158
-583
File diff suppressed because it is too large
Load Diff
+1853
-693
File diff suppressed because it is too large
Load Diff
+93
-10
@@ -26,8 +26,6 @@
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#include "target/arm/cpu-qom.h"
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#include "target/arm/gtimer.h"
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#define GIC_NUM_SPI_INTR 160
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#define ARM_PHYS_TIMER_PPI 30
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#define ARM_VIRT_TIMER_PPI 27
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#define ARM_HYP_TIMER_PPI 26
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@@ -206,17 +204,26 @@ static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
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static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
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{
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return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
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return XLNX_ZYNQMP_GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
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}
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static unsigned int xlnx_zynqmp_get_rpu_number(MachineState *ms)
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{
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/*
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* RPUs will be created only if "-smp" is higher than the maximum
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* of APUs. Round it up to 0 to avoid dealing with negative values.
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*/
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return MAX(0, MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
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XLNX_ZYNQMP_NUM_RPU_CPUS));
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}
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static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
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const char *boot_cpu, Error **errp)
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{
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int i;
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int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
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XLNX_ZYNQMP_NUM_RPU_CPUS);
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int num_rpus = xlnx_zynqmp_get_rpu_number(ms);
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if (num_rpus <= 0) {
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if (!num_rpus) {
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/* Don't create rpu-cluster object if there's nothing to put in it */
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return;
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}
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@@ -377,6 +384,7 @@ static void xlnx_zynqmp_init(Object *obj)
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XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
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int i;
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int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
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int num_rpus = xlnx_zynqmp_get_rpu_number(ms);
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object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
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TYPE_CPU_CLUSTER);
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@@ -390,6 +398,12 @@ static void xlnx_zynqmp_init(Object *obj)
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object_initialize_child(obj, "gic", &s->gic, gic_class_name());
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if (num_rpus) {
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/* Do not create the rpu_gic if we don't have rpus */
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object_initialize_child(obj, "rpu_gic", &s->rpu_gic,
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gic_class_name());
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
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object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
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object_initialize_child(obj, "gem-irq-orgate[*]",
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@@ -439,6 +453,15 @@ static void xlnx_zynqmp_init(Object *obj)
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object_initialize_child(obj, "qspi-irq-orgate",
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&s->qspi_irq_orgate, TYPE_OR_IRQ);
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|
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if (num_rpus) {
|
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for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
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g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
|
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object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
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}
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}
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|
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|
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for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
|
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object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
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}
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@@ -452,9 +475,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
|
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uint8_t i;
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uint64_t ram_size;
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int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
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int num_rpus = xlnx_zynqmp_get_rpu_number(ms);
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const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
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ram_addr_t ddr_low_size, ddr_high_size;
|
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qemu_irq gic_spi[GIC_NUM_SPI_INTR];
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qemu_irq gic_spi[XLNX_ZYNQMP_GIC_NUM_SPI_INTR];
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Error *err = NULL;
|
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|
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ram_size = memory_region_size(s->ddr_ram);
|
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@@ -502,13 +526,22 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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g_free(ocm_name);
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}
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq",
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XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32);
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qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
|
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
|
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qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
|
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qdev_prop_set_bit(DEVICE(&s->gic),
|
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"has-virtualization-extensions", s->virt);
|
||||
|
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if (num_rpus) {
|
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qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-irq",
|
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XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32);
|
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qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "revision", 1);
|
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qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-cpu", num_rpus);
|
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qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "first-cpu-index", 4);
|
||||
}
|
||||
|
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qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
|
||||
|
||||
/* Realize APUs before realizing the GIC. KVM requires this. */
|
||||
@@ -608,13 +641,63 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
|
||||
return;
|
||||
}
|
||||
|
||||
if (num_rpus) {
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rpu_gic), errp)) {
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_rpus; i++) {
|
||||
qemu_irq irq;
|
||||
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), i + 1,
|
||||
GIC_BASE_ADDR + i * 0x1000);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i,
|
||||
qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
|
||||
ARM_CPU_IRQ));
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus,
|
||||
qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
|
||||
ARM_CPU_FIQ));
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus * 2,
|
||||
qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
|
||||
ARM_CPU_VIRQ));
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus * 3,
|
||||
qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
|
||||
ARM_CPU_VFIQ));
|
||||
irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
|
||||
arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
|
||||
qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_PHYS, irq);
|
||||
irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
|
||||
arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
|
||||
qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_VIRT, irq);
|
||||
irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
|
||||
arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
|
||||
qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_HYP, irq);
|
||||
irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
|
||||
arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
|
||||
qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_SEC, irq);
|
||||
}
|
||||
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), 0, GIC_BASE_ADDR);
|
||||
}
|
||||
|
||||
if (!s->boot_cpu_ptr) {
|
||||
error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
|
||||
gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
|
||||
for (i = 0; i < XLNX_ZYNQMP_GIC_NUM_SPI_INTR; i++) {
|
||||
if (num_rpus) {
|
||||
DeviceState *splitter = DEVICE(&s->splitter[i]);
|
||||
qdev_prop_set_uint16(splitter, "num-lines", 2);
|
||||
qdev_realize(splitter, NULL, &error_abort);
|
||||
gic_spi[i] = qdev_get_gpio_in(splitter, 0);
|
||||
qdev_connect_gpio_out(splitter, 0,
|
||||
qdev_get_gpio_in(DEVICE(&s->gic), i));
|
||||
qdev_connect_gpio_out(splitter, 1,
|
||||
qdev_get_gpio_in(DEVICE(&s->rpu_gic), i));
|
||||
} else {
|
||||
gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "hw/irq.h"
|
||||
#include "hw/arm/sharpsl.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "qemu/module.h"
|
||||
@@ -265,44 +264,3 @@ static void scoop_register_types(void)
|
||||
}
|
||||
|
||||
type_init(scoop_register_types)
|
||||
|
||||
/* Write the bootloader parameters memory area. */
|
||||
|
||||
#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
|
||||
|
||||
static struct QEMU_PACKED sl_param_info {
|
||||
uint32_t comadj_keyword;
|
||||
int32_t comadj;
|
||||
|
||||
uint32_t uuid_keyword;
|
||||
char uuid[16];
|
||||
|
||||
uint32_t touch_keyword;
|
||||
int32_t touch_xp;
|
||||
int32_t touch_yp;
|
||||
int32_t touch_xd;
|
||||
int32_t touch_yd;
|
||||
|
||||
uint32_t adadj_keyword;
|
||||
int32_t adadj;
|
||||
|
||||
uint32_t phad_keyword;
|
||||
int32_t phadadj;
|
||||
} zaurus_bootparam = {
|
||||
.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
|
||||
.comadj = 125,
|
||||
.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
|
||||
.uuid = { -1 },
|
||||
.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
|
||||
.touch_xp = -1,
|
||||
.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
|
||||
.adadj = -1,
|
||||
.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
|
||||
.phadadj = 0x01,
|
||||
};
|
||||
|
||||
void sl_bootparam_write(hwaddr ptr)
|
||||
{
|
||||
cpu_physical_memory_write(ptr, &zaurus_bootparam,
|
||||
sizeof(struct sl_param_info));
|
||||
}
|
||||
|
||||
@@ -436,7 +436,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
|
||||
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
|
||||
|
||||
for (i = 0; i < s->num_cpu; i++) {
|
||||
CPUState *cpu = qemu_get_cpu(i);
|
||||
CPUState *cpu = qemu_get_cpu(s->first_cpu_idx + i);
|
||||
uint64_t cpu_affid;
|
||||
|
||||
s->cpu[i].cpu = cpu;
|
||||
@@ -622,6 +622,7 @@ static const Property arm_gicv3_common_properties[] = {
|
||||
redist_region_count, qdev_prop_uint32, uint32_t),
|
||||
DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
|
||||
MemoryRegion *),
|
||||
DEFINE_PROP_UINT32("first-cpu-index", GICv3State, first_cpu_idx, 0),
|
||||
};
|
||||
|
||||
static void arm_gicv3_common_class_init(ObjectClass *klass, const void *data)
|
||||
|
||||
@@ -3024,7 +3024,7 @@ void gicv3_init_cpuif(GICv3State *s)
|
||||
int i;
|
||||
|
||||
for (i = 0; i < s->num_cpu; i++) {
|
||||
ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
|
||||
ARMCPU *cpu = ARM_CPU(qemu_get_cpu(s->first_cpu_idx + i));
|
||||
GICv3CPUState *cs = &s->cpu[i];
|
||||
|
||||
/*
|
||||
|
||||
@@ -821,6 +821,12 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
|
||||
return;
|
||||
}
|
||||
|
||||
if (s->first_cpu_idx != 0) {
|
||||
error_setg(errp, "Non-zero first-cpu-idx is unsupported with the "
|
||||
"in-kernel GIC");
|
||||
return;
|
||||
}
|
||||
|
||||
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
|
||||
|
||||
for (i = 0; i < s->num_cpu; i++) {
|
||||
|
||||
+513
-101
File diff suppressed because it is too large
Load Diff
@@ -1,17 +0,0 @@
|
||||
/*
|
||||
* Common declarations for the Zaurii.
|
||||
*
|
||||
* This file is licensed under the GNU GPL.
|
||||
*/
|
||||
|
||||
#ifndef QEMU_SHARPSL_H
|
||||
#define QEMU_SHARPSL_H
|
||||
|
||||
#include "exec/hwaddr.h"
|
||||
|
||||
/* zaurus.c */
|
||||
|
||||
#define SL_PXA_PARAM_BASE 0xa0000a00
|
||||
void sl_bootparam_write(hwaddr ptr);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* AMD Versal versions
|
||||
*
|
||||
* Copyright (c) 2025 Advanced Micro Devices, Inc.
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#ifndef HW_ARM_XLNX_VERSAL_VERSION_H
|
||||
#define HW_ARM_XLNX_VERSAL_VERSION_H
|
||||
|
||||
typedef enum VersalVersion {
|
||||
VERSAL_VER_VERSAL,
|
||||
VERSAL_VER_VERSAL2,
|
||||
} VersalVersion;
|
||||
|
||||
#endif
|
||||
+47
-295
@@ -1,7 +1,8 @@
|
||||
/*
|
||||
* Model of the Xilinx Versal
|
||||
* AMD/Xilinx Versal family SoC model.
|
||||
*
|
||||
* Copyright (c) 2018 Xilinx Inc.
|
||||
* Copyright (c) 2025 Advanced Micro Devices, Inc.
|
||||
* Written by Edgar E. Iglesias
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
@@ -13,326 +14,77 @@
|
||||
#define XLNX_VERSAL_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/cpu/cluster.h"
|
||||
#include "hw/or-irq.h"
|
||||
#include "hw/sd/sdhci.h"
|
||||
#include "hw/intc/arm_gicv3.h"
|
||||
#include "hw/char/pl011.h"
|
||||
#include "hw/dma/xlnx-zdma.h"
|
||||
#include "hw/net/cadence_gem.h"
|
||||
#include "hw/rtc/xlnx-zynqmp-rtc.h"
|
||||
#include "qom/object.h"
|
||||
#include "hw/usb/xlnx-usb-subsystem.h"
|
||||
#include "hw/misc/xlnx-versal-xramc.h"
|
||||
#include "hw/nvram/xlnx-bbram.h"
|
||||
#include "hw/nvram/xlnx-versal-efuse.h"
|
||||
#include "hw/ssi/xlnx-versal-ospi.h"
|
||||
#include "hw/dma/xlnx_csu_dma.h"
|
||||
#include "hw/misc/xlnx-versal-crl.h"
|
||||
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
|
||||
#include "hw/misc/xlnx-versal-trng.h"
|
||||
#include "hw/net/xlnx-versal-canfd.h"
|
||||
#include "hw/misc/xlnx-versal-cfu.h"
|
||||
#include "hw/misc/xlnx-versal-cframe-reg.h"
|
||||
#include "target/arm/cpu.h"
|
||||
#include "net/can_emu.h"
|
||||
#include "hw/arm/xlnx-versal-version.h"
|
||||
|
||||
#define TYPE_XLNX_VERSAL_BASE "xlnx-versal-base"
|
||||
OBJECT_DECLARE_TYPE(Versal, VersalClass, XLNX_VERSAL_BASE)
|
||||
|
||||
#define TYPE_XLNX_VERSAL "xlnx-versal"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
|
||||
|
||||
#define XLNX_VERSAL_NR_ACPUS 2
|
||||
#define XLNX_VERSAL_NR_RCPUS 2
|
||||
#define XLNX_VERSAL_NR_UARTS 2
|
||||
#define XLNX_VERSAL_NR_GEMS 2
|
||||
#define XLNX_VERSAL_NR_ADMAS 8
|
||||
#define XLNX_VERSAL_NR_SDS 2
|
||||
#define XLNX_VERSAL_NR_XRAM 4
|
||||
#define XLNX_VERSAL_NR_IRQS 192
|
||||
#define XLNX_VERSAL_NR_CANFD 2
|
||||
#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000)
|
||||
#define XLNX_VERSAL_NR_CFRAME 15
|
||||
#define TYPE_XLNX_VERSAL2 "xlnx-versal2"
|
||||
|
||||
struct Versal {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
struct {
|
||||
struct {
|
||||
MemoryRegion mr;
|
||||
CPUClusterState cluster;
|
||||
ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
|
||||
GICv3State gic;
|
||||
} apu;
|
||||
} fpd;
|
||||
|
||||
GArray *intc;
|
||||
MemoryRegion mr_ps;
|
||||
|
||||
struct {
|
||||
/* 4 ranges to access DDR. */
|
||||
MemoryRegion mr_ddr_ranges[4];
|
||||
} noc;
|
||||
|
||||
struct {
|
||||
MemoryRegion mr_ocm;
|
||||
|
||||
struct {
|
||||
PL011State uart[XLNX_VERSAL_NR_UARTS];
|
||||
CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
|
||||
OrIRQState gem_irq_orgate[XLNX_VERSAL_NR_GEMS];
|
||||
XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
|
||||
VersalUsb2 usb;
|
||||
CanBusState *canbus[XLNX_VERSAL_NR_CANFD];
|
||||
XlnxVersalCANFDState canfd[XLNX_VERSAL_NR_CANFD];
|
||||
} iou;
|
||||
|
||||
/* Real-time Processing Unit. */
|
||||
struct {
|
||||
MemoryRegion mr;
|
||||
MemoryRegion mr_ps_alias;
|
||||
|
||||
CPUClusterState cluster;
|
||||
ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
|
||||
} rpu;
|
||||
|
||||
struct {
|
||||
OrIRQState irq_orgate;
|
||||
XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
|
||||
} xram;
|
||||
|
||||
XlnxVersalCRL crl;
|
||||
} lpd;
|
||||
|
||||
/* The Platform Management Controller subsystem. */
|
||||
struct {
|
||||
struct {
|
||||
SDHCIState sd[XLNX_VERSAL_NR_SDS];
|
||||
XlnxVersalPmcIouSlcr slcr;
|
||||
|
||||
struct {
|
||||
XlnxVersalOspi ospi;
|
||||
XlnxCSUDMA dma_src;
|
||||
XlnxCSUDMA dma_dst;
|
||||
MemoryRegion linear_mr;
|
||||
OrIRQState irq_orgate;
|
||||
} ospi;
|
||||
} iou;
|
||||
|
||||
XlnxZynqMPRTC rtc;
|
||||
XlnxVersalTRng trng;
|
||||
XlnxBBRam bbram;
|
||||
XlnxEFuse efuse;
|
||||
XlnxVersalEFuseCtrl efuse_ctrl;
|
||||
XlnxVersalEFuseCache efuse_cache;
|
||||
XlnxVersalCFUAPB cfu_apb;
|
||||
XlnxVersalCFUFDRO cfu_fdro;
|
||||
XlnxVersalCFUSFR cfu_sfr;
|
||||
XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME];
|
||||
XlnxVersalCFrameBcastReg cframe_bcast;
|
||||
|
||||
OrIRQState apb_irq_orgate;
|
||||
} pmc;
|
||||
uint32_t clk_25mhz;
|
||||
uint32_t clk_125mhz;
|
||||
uint32_t gic;
|
||||
} phandle;
|
||||
|
||||
struct {
|
||||
MemoryRegion *mr_ddr;
|
||||
CanBusState **canbus;
|
||||
void *fdt;
|
||||
} cfg;
|
||||
};
|
||||
|
||||
/* Memory-map and IRQ definitions. Copied a subset from
|
||||
* auto-generated files. */
|
||||
struct VersalClass {
|
||||
SysBusDeviceClass parent;
|
||||
|
||||
#define VERSAL_GIC_MAINT_IRQ 9
|
||||
#define VERSAL_TIMER_VIRT_IRQ 11
|
||||
#define VERSAL_TIMER_S_EL1_IRQ 13
|
||||
#define VERSAL_TIMER_NS_EL1_IRQ 14
|
||||
#define VERSAL_TIMER_NS_EL2_IRQ 10
|
||||
VersalVersion version;
|
||||
};
|
||||
|
||||
#define VERSAL_CRL_IRQ 10
|
||||
#define VERSAL_UART0_IRQ_0 18
|
||||
#define VERSAL_UART1_IRQ_0 19
|
||||
#define VERSAL_CANFD0_IRQ_0 20
|
||||
#define VERSAL_CANFD1_IRQ_0 21
|
||||
#define VERSAL_USB0_IRQ_0 22
|
||||
#define VERSAL_GEM0_IRQ_0 56
|
||||
#define VERSAL_GEM0_WAKE_IRQ_0 57
|
||||
#define VERSAL_GEM1_IRQ_0 58
|
||||
#define VERSAL_GEM1_WAKE_IRQ_0 59
|
||||
#define VERSAL_ADMA_IRQ_0 60
|
||||
#define VERSAL_XRAM_IRQ_0 79
|
||||
#define VERSAL_CFU_IRQ_0 120
|
||||
#define VERSAL_PMC_APB_IRQ 121
|
||||
#define VERSAL_OSPI_IRQ 124
|
||||
#define VERSAL_SD0_IRQ_0 126
|
||||
#define VERSAL_EFUSE_IRQ 139
|
||||
#define VERSAL_TRNG_IRQ 141
|
||||
#define VERSAL_RTC_ALARM_IRQ 142
|
||||
#define VERSAL_RTC_SECONDS_IRQ 143
|
||||
static inline void versal_set_fdt(Versal *s, void *fdt)
|
||||
{
|
||||
g_assert(!qdev_is_realized(DEVICE(s)));
|
||||
s->cfg.fdt = fdt;
|
||||
}
|
||||
|
||||
/* Architecturally reserved IRQs suitable for virtualization. */
|
||||
#define VERSAL_RSVD_IRQ_FIRST 111
|
||||
#define VERSAL_RSVD_IRQ_LAST 118
|
||||
void versal_fdt_add_memory_nodes(Versal *s, uint64_t ram_size);
|
||||
|
||||
#define MM_TOP_RSVD 0xa0000000U
|
||||
#define MM_TOP_RSVD_SIZE 0x4000000
|
||||
#define MM_GIC_APU_DIST_MAIN 0xf9000000U
|
||||
#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
|
||||
#define MM_GIC_APU_REDIST_0 0xf9080000U
|
||||
#define MM_GIC_APU_REDIST_0_SIZE 0x80000
|
||||
DeviceState *versal_get_boot_cpu(Versal *s);
|
||||
void versal_sdhci_plug_card(Versal *s, int sd_idx, BlockBackend *blk);
|
||||
void versal_efuse_attach_drive(Versal *s, BlockBackend *blk);
|
||||
void versal_bbram_attach_drive(Versal *s, BlockBackend *blk);
|
||||
void versal_ospi_create_flash(Versal *s, int flash_idx, const char *flash_mdl,
|
||||
BlockBackend *blk);
|
||||
|
||||
#define MM_UART0 0xff000000U
|
||||
#define MM_UART0_SIZE 0x10000
|
||||
#define MM_UART1 0xff010000U
|
||||
#define MM_UART1_SIZE 0x10000
|
||||
qemu_irq versal_get_reserved_irq(Versal *s, int idx, int *dtb_idx);
|
||||
hwaddr versal_get_reserved_mmio_addr(Versal *s);
|
||||
|
||||
#define MM_CANFD0 0xff060000U
|
||||
#define MM_CANFD0_SIZE 0x10000
|
||||
#define MM_CANFD1 0xff070000U
|
||||
#define MM_CANFD1_SIZE 0x10000
|
||||
int versal_get_num_cpu(VersalVersion version);
|
||||
int versal_get_num_can(VersalVersion version);
|
||||
int versal_get_num_sdhci(VersalVersion version);
|
||||
|
||||
#define MM_GEM0 0xff0c0000U
|
||||
#define MM_GEM0_SIZE 0x10000
|
||||
#define MM_GEM1 0xff0d0000U
|
||||
#define MM_GEM1_SIZE 0x10000
|
||||
static inline const char *versal_get_class(VersalVersion version)
|
||||
{
|
||||
switch (version) {
|
||||
case VERSAL_VER_VERSAL:
|
||||
return TYPE_XLNX_VERSAL;
|
||||
|
||||
#define MM_ADMA_CH0 0xffa80000U
|
||||
#define MM_ADMA_CH0_SIZE 0x10000
|
||||
case VERSAL_VER_VERSAL2:
|
||||
return TYPE_XLNX_VERSAL2;
|
||||
|
||||
#define MM_OCM 0xfffc0000U
|
||||
#define MM_OCM_SIZE 0x40000
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
}
|
||||
|
||||
#define MM_XRAM 0xfe800000
|
||||
#define MM_XRAMC 0xff8e0000
|
||||
#define MM_XRAMC_SIZE 0x10000
|
||||
|
||||
#define MM_USB2_CTRL_REGS 0xFF9D0000
|
||||
#define MM_USB2_CTRL_REGS_SIZE 0x10000
|
||||
|
||||
#define MM_USB_0 0xFE200000
|
||||
#define MM_USB_0_SIZE 0x10000
|
||||
|
||||
#define MM_TOP_DDR 0x0
|
||||
#define MM_TOP_DDR_SIZE 0x80000000U
|
||||
#define MM_TOP_DDR_2 0x800000000ULL
|
||||
#define MM_TOP_DDR_2_SIZE 0x800000000ULL
|
||||
#define MM_TOP_DDR_3 0xc000000000ULL
|
||||
#define MM_TOP_DDR_3_SIZE 0x4000000000ULL
|
||||
#define MM_TOP_DDR_4 0x10000000000ULL
|
||||
#define MM_TOP_DDR_4_SIZE 0xb780000000ULL
|
||||
|
||||
#define MM_PSM_START 0xffc80000U
|
||||
#define MM_PSM_END 0xffcf0000U
|
||||
|
||||
#define MM_CRL 0xff5e0000U
|
||||
#define MM_CRL_SIZE 0x300000
|
||||
#define MM_IOU_SCNTR 0xff130000U
|
||||
#define MM_IOU_SCNTR_SIZE 0x10000
|
||||
#define MM_IOU_SCNTRS 0xff140000U
|
||||
#define MM_IOU_SCNTRS_SIZE 0x10000
|
||||
#define MM_FPD_CRF 0xfd1a0000U
|
||||
#define MM_FPD_CRF_SIZE 0x140000
|
||||
#define MM_FPD_FPD_APU 0xfd5c0000
|
||||
#define MM_FPD_FPD_APU_SIZE 0x100
|
||||
|
||||
#define MM_PMC_PMC_IOU_SLCR 0xf1060000
|
||||
#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000
|
||||
|
||||
#define MM_PMC_OSPI 0xf1010000
|
||||
#define MM_PMC_OSPI_SIZE 0x10000
|
||||
|
||||
#define MM_PMC_OSPI_DAC 0xc0000000
|
||||
#define MM_PMC_OSPI_DAC_SIZE 0x20000000
|
||||
|
||||
#define MM_PMC_OSPI_DMA_DST 0xf1011800
|
||||
#define MM_PMC_OSPI_DMA_SRC 0xf1011000
|
||||
|
||||
#define MM_PMC_SD0 0xf1040000U
|
||||
#define MM_PMC_SD0_SIZE 0x10000
|
||||
#define MM_PMC_BBRAM_CTRL 0xf11f0000
|
||||
#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
|
||||
#define MM_PMC_EFUSE_CTRL 0xf1240000
|
||||
#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
|
||||
#define MM_PMC_EFUSE_CACHE 0xf1250000
|
||||
#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
|
||||
|
||||
#define MM_PMC_CFU_APB 0xf12b0000
|
||||
#define MM_PMC_CFU_APB_SIZE 0x10000
|
||||
#define MM_PMC_CFU_STREAM 0xf12c0000
|
||||
#define MM_PMC_CFU_STREAM_SIZE 0x1000
|
||||
#define MM_PMC_CFU_SFR 0xf12c1000
|
||||
#define MM_PMC_CFU_SFR_SIZE 0x1000
|
||||
#define MM_PMC_CFU_FDRO 0xf12c2000
|
||||
#define MM_PMC_CFU_FDRO_SIZE 0x1000
|
||||
#define MM_PMC_CFU_STREAM_2 0xf1f80000
|
||||
#define MM_PMC_CFU_STREAM_2_SIZE 0x40000
|
||||
|
||||
#define MM_PMC_CFRAME0_REG 0xf12d0000
|
||||
#define MM_PMC_CFRAME0_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME0_FDRI 0xf12d1000
|
||||
#define MM_PMC_CFRAME0_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME1_REG 0xf12d2000
|
||||
#define MM_PMC_CFRAME1_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME1_FDRI 0xf12d3000
|
||||
#define MM_PMC_CFRAME1_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME2_REG 0xf12d4000
|
||||
#define MM_PMC_CFRAME2_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME2_FDRI 0xf12d5000
|
||||
#define MM_PMC_CFRAME2_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME3_REG 0xf12d6000
|
||||
#define MM_PMC_CFRAME3_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME3_FDRI 0xf12d7000
|
||||
#define MM_PMC_CFRAME3_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME4_REG 0xf12d8000
|
||||
#define MM_PMC_CFRAME4_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME4_FDRI 0xf12d9000
|
||||
#define MM_PMC_CFRAME4_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME5_REG 0xf12da000
|
||||
#define MM_PMC_CFRAME5_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME5_FDRI 0xf12db000
|
||||
#define MM_PMC_CFRAME5_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME6_REG 0xf12dc000
|
||||
#define MM_PMC_CFRAME6_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME6_FDRI 0xf12dd000
|
||||
#define MM_PMC_CFRAME6_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME7_REG 0xf12de000
|
||||
#define MM_PMC_CFRAME7_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME7_FDRI 0xf12df000
|
||||
#define MM_PMC_CFRAME7_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME8_REG 0xf12e0000
|
||||
#define MM_PMC_CFRAME8_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME8_FDRI 0xf12e1000
|
||||
#define MM_PMC_CFRAME8_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME9_REG 0xf12e2000
|
||||
#define MM_PMC_CFRAME9_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME9_FDRI 0xf12e3000
|
||||
#define MM_PMC_CFRAME9_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME10_REG 0xf12e4000
|
||||
#define MM_PMC_CFRAME10_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME10_FDRI 0xf12e5000
|
||||
#define MM_PMC_CFRAME10_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME11_REG 0xf12e6000
|
||||
#define MM_PMC_CFRAME11_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME11_FDRI 0xf12e7000
|
||||
#define MM_PMC_CFRAME11_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME12_REG 0xf12e8000
|
||||
#define MM_PMC_CFRAME12_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME12_FDRI 0xf12e9000
|
||||
#define MM_PMC_CFRAME12_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME13_REG 0xf12ea000
|
||||
#define MM_PMC_CFRAME13_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME13_FDRI 0xf12eb000
|
||||
#define MM_PMC_CFRAME13_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME14_REG 0xf12ec000
|
||||
#define MM_PMC_CFRAME14_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME14_FDRI 0xf12ed000
|
||||
#define MM_PMC_CFRAME14_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME_BCAST_REG 0xf12ee000
|
||||
#define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000
|
||||
#define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000
|
||||
|
||||
#define MM_PMC_CRP 0xf1260000U
|
||||
#define MM_PMC_CRP_SIZE 0x10000
|
||||
#define MM_PMC_RTC 0xf12a0000
|
||||
#define MM_PMC_RTC_SIZE 0x10000
|
||||
#define MM_PMC_TRNG 0xf1230000
|
||||
#define MM_PMC_TRNG_SIZE 0x10000
|
||||
#endif
|
||||
|
||||
@@ -42,6 +42,7 @@
|
||||
#include "hw/misc/xlnx-zynqmp-crf.h"
|
||||
#include "hw/timer/cadence_ttc.h"
|
||||
#include "hw/usb/hcd-dwc3.h"
|
||||
#include "hw/core/split-irq.h"
|
||||
|
||||
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
|
||||
@@ -67,6 +68,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
|
||||
#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
|
||||
|
||||
#define XLNX_ZYNQMP_GIC_REGIONS 6
|
||||
#define XLNX_ZYNQMP_GIC_NUM_SPI_INTR 160
|
||||
|
||||
/*
|
||||
* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
|
||||
@@ -105,6 +107,9 @@ struct XlnxZynqMPState {
|
||||
GICState gic;
|
||||
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
|
||||
|
||||
GICState rpu_gic;
|
||||
SplitIRQ splitter[XLNX_ZYNQMP_GIC_NUM_SPI_INTR];
|
||||
|
||||
MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
|
||||
|
||||
MemoryRegion *ddr_ram;
|
||||
|
||||
@@ -229,6 +229,7 @@ struct GICv3State {
|
||||
uint32_t *redist_region_count; /* redistributor count within each region */
|
||||
uint32_t nb_redist_regions; /* number of redist regions */
|
||||
|
||||
uint32_t first_cpu_idx;
|
||||
uint32_t num_cpu;
|
||||
uint32_t num_irq;
|
||||
uint32_t revision;
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
* QEMU model of the Clock-Reset-LPD (CRL).
|
||||
*
|
||||
* Copyright (c) 2022 Xilinx Inc.
|
||||
* Copyright (c) 2025 Advanced Micro Devices, Inc.
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
|
||||
@@ -12,9 +13,16 @@
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/register.h"
|
||||
#include "target/arm/cpu-qom.h"
|
||||
#include "hw/arm/xlnx-versal-version.h"
|
||||
|
||||
#define TYPE_XLNX_VERSAL_CRL_BASE "xlnx-versal-crl-base"
|
||||
#define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
|
||||
#define TYPE_XLNX_VERSAL2_CRL "xlnx-versal2-crl"
|
||||
|
||||
OBJECT_DECLARE_TYPE(XlnxVersalCRLBase, XlnxVersalCRLBaseClass,
|
||||
XLNX_VERSAL_CRL_BASE)
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersal2CRL, XLNX_VERSAL2_CRL)
|
||||
|
||||
REG32(ERR_CTRL, 0x0)
|
||||
FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
|
||||
@@ -214,22 +222,370 @@ REG32(PSM_RST_MODE, 0x370)
|
||||
|
||||
#define CRL_R_MAX (R_PSM_RST_MODE + 1)
|
||||
|
||||
#define RPU_MAX_CPU 2
|
||||
REG32(VERSAL2_ERR_CTRL, 0x0)
|
||||
REG32(VERSAL2_WPROT, 0x1c)
|
||||
FIELD(VERSAL2_WPROT, ACTIVE, 0, 1)
|
||||
REG32(VERSAL2_RPLL_CTRL, 0x40)
|
||||
FIELD(VERSAL2_RPLL_CTRL, POST_SRC, 24, 3)
|
||||
FIELD(VERSAL2_RPLL_CTRL, PRE_SRC, 20, 3)
|
||||
FIELD(VERSAL2_RPLL_CTRL, CLKOUTDIV, 16, 2)
|
||||
FIELD(VERSAL2_RPLL_CTRL, FBDIV, 8, 8)
|
||||
FIELD(VERSAL2_RPLL_CTRL, BYPASS, 3, 1)
|
||||
FIELD(VERSAL2_RPLL_CTRL, RESET, 0, 1)
|
||||
REG32(VERSAL2_RPLL_CFG, 0x44)
|
||||
FIELD(VERSAL2_RPLL_CFG, LOCK_DLY, 25, 7)
|
||||
FIELD(VERSAL2_RPLL_CFG, LOCK_CNT, 13, 10)
|
||||
FIELD(VERSAL2_RPLL_CFG, LFHF, 10, 2)
|
||||
FIELD(VERSAL2_RPLL_CFG, CP, 5, 4)
|
||||
FIELD(VERSAL2_RPLL_CFG, RES, 0, 4)
|
||||
REG32(VERSAL2_FLXPLL_CTRL, 0x50)
|
||||
FIELD(VERSAL2_FLXPLL_CTRL, POST_SRC, 24, 3)
|
||||
FIELD(VERSAL2_FLXPLL_CTRL, PRE_SRC, 20, 3)
|
||||
FIELD(VERSAL2_FLXPLL_CTRL, CLKOUTDIV, 16, 2)
|
||||
FIELD(VERSAL2_FLXPLL_CTRL, FBDIV, 8, 8)
|
||||
FIELD(VERSAL2_FLXPLL_CTRL, BYPASS, 3, 1)
|
||||
FIELD(VERSAL2_FLXPLL_CTRL, RESET, 0, 1)
|
||||
REG32(VERSAL2_FLXPLL_CFG, 0x54)
|
||||
FIELD(VERSAL2_FLXPLL_CFG, LOCK_DLY, 25, 7)
|
||||
FIELD(VERSAL2_FLXPLL_CFG, LOCK_CNT, 13, 10)
|
||||
FIELD(VERSAL2_FLXPLL_CFG, LFHF, 10, 2)
|
||||
FIELD(VERSAL2_FLXPLL_CFG, CP, 5, 4)
|
||||
FIELD(VERSAL2_FLXPLL_CFG, RES, 0, 4)
|
||||
REG32(VERSAL2_PLL_STATUS, 0x60)
|
||||
FIELD(VERSAL2_PLL_STATUS, FLXPLL_STABLE, 3, 1)
|
||||
FIELD(VERSAL2_PLL_STATUS, RPLL_STABLE, 2, 1)
|
||||
FIELD(VERSAL2_PLL_STATUS, FLXPLL_LOCK, 1, 1)
|
||||
FIELD(VERSAL2_PLL_STATUS, RPLL_LOCK, 0, 1)
|
||||
REG32(VERSAL2_RPLL_TO_XPD_CTRL, 0x100)
|
||||
FIELD(VERSAL2_RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
|
||||
REG32(VERSAL2_LPX_TOP_SWITCH_CTRL, 0x104)
|
||||
FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
|
||||
FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_LPX_LSBUS_CLK_CTRL, 0x108)
|
||||
FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_RPU_CLK_CTRL, 0x10c)
|
||||
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERE, 24, 1)
|
||||
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERD, 23, 1)
|
||||
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERC, 22, 1)
|
||||
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERB, 21, 1)
|
||||
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERA, 20, 1)
|
||||
FIELD(VERSAL2_RPU_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_RPU_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_OCM_CLK_CTRL, 0x120)
|
||||
FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM3, 24, 1)
|
||||
FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM2, 23, 1)
|
||||
FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM1, 22, 1)
|
||||
FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM0, 21, 1)
|
||||
REG32(VERSAL2_IOU_SWITCH_CLK_CTRL, 0x124)
|
||||
FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_GEM0_REF_CTRL, 0x128)
|
||||
FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_RX, 27, 1)
|
||||
FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_TX, 26, 1)
|
||||
FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_GEM0_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_GEM0_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_GEM1_REF_CTRL, 0x12c)
|
||||
FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_RX, 27, 1)
|
||||
FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_TX, 26, 1)
|
||||
FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_GEM1_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_GEM1_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_GEM_TSU_REF_CLK_CTRL, 0x130)
|
||||
FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_USB0_BUS_REF_CLK_CTRL, 0x134)
|
||||
FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_USB1_BUS_REF_CLK_CTRL, 0x138)
|
||||
FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_UART0_REF_CLK_CTRL, 0x13c)
|
||||
FIELD(VERSAL2_UART0_REF_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_UART0_REF_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_UART0_REF_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_UART1_REF_CLK_CTRL, 0x140)
|
||||
FIELD(VERSAL2_UART1_REF_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_UART1_REF_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_UART1_REF_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_SPI0_REF_CLK_CTRL, 0x144)
|
||||
FIELD(VERSAL2_SPI0_REF_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_SPI0_REF_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_SPI0_REF_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_SPI1_REF_CLK_CTRL, 0x148)
|
||||
FIELD(VERSAL2_SPI1_REF_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_SPI1_REF_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_SPI1_REF_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_CAN0_REF_2X_CTRL, 0x14c)
|
||||
FIELD(VERSAL2_CAN0_REF_2X_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_CAN0_REF_2X_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_CAN0_REF_2X_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_CAN1_REF_2X_CTRL, 0x150)
|
||||
FIELD(VERSAL2_CAN1_REF_2X_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_CAN1_REF_2X_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_CAN1_REF_2X_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_CAN2_REF_2X_CTRL, 0x154)
|
||||
FIELD(VERSAL2_CAN2_REF_2X_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_CAN2_REF_2X_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_CAN2_REF_2X_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_CAN3_REF_2X_CTRL, 0x158)
|
||||
FIELD(VERSAL2_CAN3_REF_2X_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_CAN3_REF_2X_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_CAN3_REF_2X_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_I3C0_REF_CTRL, 0x15c)
|
||||
FIELD(VERSAL2_I3C0_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_I3C0_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_I3C0_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_I3C1_REF_CTRL, 0x160)
|
||||
FIELD(VERSAL2_I3C1_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_I3C1_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_I3C1_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_I3C2_REF_CTRL, 0x164)
|
||||
FIELD(VERSAL2_I3C2_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_I3C2_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_I3C2_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_I3C3_REF_CTRL, 0x168)
|
||||
FIELD(VERSAL2_I3C3_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_I3C3_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_I3C3_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_I3C4_REF_CTRL, 0x16c)
|
||||
FIELD(VERSAL2_I3C4_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_I3C4_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_I3C4_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_I3C5_REF_CTRL, 0x170)
|
||||
FIELD(VERSAL2_I3C5_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_I3C5_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_I3C5_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_I3C6_REF_CTRL, 0x174)
|
||||
FIELD(VERSAL2_I3C6_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_I3C6_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_I3C6_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_I3C7_REF_CTRL, 0x178)
|
||||
FIELD(VERSAL2_I3C7_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_I3C7_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_I3C7_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_DBG_LPX_CTRL, 0x17c)
|
||||
FIELD(VERSAL2_DBG_LPX_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_DBG_LPX_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_DBG_LPX_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_TIMESTAMP_REF_CTRL, 0x180)
|
||||
FIELD(VERSAL2_TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_SAFETY_CHK, 0x184)
|
||||
REG32(VERSAL2_ASU_CLK_CTRL, 0x188)
|
||||
FIELD(VERSAL2_ASU_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_ASU_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_DBG_TSTMP_CLK_CTRL, 0x18c)
|
||||
FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_MMI_TOPSW_CLK_CTRL, 0x190)
|
||||
FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, CLKACT, 25, 1)
|
||||
FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_WWDT_PLL_CLK_CTRL, 0x194)
|
||||
FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, SRCSEL, 0, 3)
|
||||
REG32(VERSAL2_RCLK_CTRL, 0x1a0)
|
||||
FIELD(VERSAL2_RCLK_CTRL, CLKACT, 8, 6)
|
||||
FIELD(VERSAL2_RCLK_CTRL, SELECT, 0, 6)
|
||||
REG32(VERSAL2_RST_RPU_A, 0x310)
|
||||
FIELD(VERSAL2_RST_RPU_A, TOPRESET, 16, 1)
|
||||
FIELD(VERSAL2_RST_RPU_A, CORE1_POR, 9, 1)
|
||||
FIELD(VERSAL2_RST_RPU_A, CORE0_POR, 8, 1)
|
||||
FIELD(VERSAL2_RST_RPU_A, CORE1_RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_RPU_A, CORE0_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_RPU_B, 0x314)
|
||||
FIELD(VERSAL2_RST_RPU_B, TOPRESET, 16, 1)
|
||||
FIELD(VERSAL2_RST_RPU_B, CORE1_POR, 9, 1)
|
||||
FIELD(VERSAL2_RST_RPU_B, CORE0_POR, 8, 1)
|
||||
FIELD(VERSAL2_RST_RPU_B, CORE1_RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_RPU_B, CORE0_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_RPU_C, 0x318)
|
||||
FIELD(VERSAL2_RST_RPU_C, TOPRESET, 16, 1)
|
||||
FIELD(VERSAL2_RST_RPU_C, CORE1_POR, 9, 1)
|
||||
FIELD(VERSAL2_RST_RPU_C, CORE0_POR, 8, 1)
|
||||
FIELD(VERSAL2_RST_RPU_C, CORE1_RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_RPU_C, CORE0_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_RPU_D, 0x31c)
|
||||
FIELD(VERSAL2_RST_RPU_D, TOPRESET, 16, 1)
|
||||
FIELD(VERSAL2_RST_RPU_D, CORE1_POR, 9, 1)
|
||||
FIELD(VERSAL2_RST_RPU_D, CORE0_POR, 8, 1)
|
||||
FIELD(VERSAL2_RST_RPU_D, CORE1_RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_RPU_D, CORE0_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_RPU_E, 0x320)
|
||||
FIELD(VERSAL2_RST_RPU_E, TOPRESET, 16, 1)
|
||||
FIELD(VERSAL2_RST_RPU_E, CORE1_POR, 9, 1)
|
||||
FIELD(VERSAL2_RST_RPU_E, CORE0_POR, 8, 1)
|
||||
FIELD(VERSAL2_RST_RPU_E, CORE1_RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_RPU_E, CORE0_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_RPU_GD_0, 0x324)
|
||||
FIELD(VERSAL2_RST_RPU_GD_0, RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_RPU_GD_0, TOP_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_RPU_GD_1, 0x328)
|
||||
FIELD(VERSAL2_RST_RPU_GD_1, RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_RPU_GD_1, TOP_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_ASU_GD, 0x32c)
|
||||
FIELD(VERSAL2_RST_ASU_GD, RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_ASU_GD, TOP_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_ADMA, 0x334)
|
||||
FIELD(VERSAL2_RST_ADMA, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SDMA, 0x338)
|
||||
FIELD(VERSAL2_RST_SDMA, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_GEM0, 0x33c)
|
||||
FIELD(VERSAL2_RST_GEM0, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_GEM1, 0x340)
|
||||
FIELD(VERSAL2_RST_GEM1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_USB0, 0x348)
|
||||
FIELD(VERSAL2_RST_USB0, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_USB1, 0x34c)
|
||||
FIELD(VERSAL2_RST_USB1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_UART0, 0x350)
|
||||
FIELD(VERSAL2_RST_UART0, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_UART1, 0x354)
|
||||
FIELD(VERSAL2_RST_UART1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SPI0, 0x358)
|
||||
FIELD(VERSAL2_RST_SPI0, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SPI1, 0x35c)
|
||||
FIELD(VERSAL2_RST_SPI1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_CAN0, 0x360)
|
||||
FIELD(VERSAL2_RST_CAN0, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_CAN1, 0x364)
|
||||
FIELD(VERSAL2_RST_CAN1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_CAN2, 0x368)
|
||||
FIELD(VERSAL2_RST_CAN2, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_CAN3, 0x36c)
|
||||
FIELD(VERSAL2_RST_CAN3, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C0, 0x374)
|
||||
FIELD(VERSAL2_RST_I3C0, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C1, 0x378)
|
||||
FIELD(VERSAL2_RST_I3C1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C2, 0x37c)
|
||||
FIELD(VERSAL2_RST_I3C2, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C3, 0x380)
|
||||
FIELD(VERSAL2_RST_I3C3, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C4, 0x384)
|
||||
FIELD(VERSAL2_RST_I3C4, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C5, 0x388)
|
||||
FIELD(VERSAL2_RST_I3C5, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C6, 0x38c)
|
||||
FIELD(VERSAL2_RST_I3C6, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C7, 0x390)
|
||||
FIELD(VERSAL2_RST_I3C7, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_DBG_LPX, 0x398)
|
||||
FIELD(VERSAL2_RST_DBG_LPX, RESET_HSDP, 1, 1)
|
||||
FIELD(VERSAL2_RST_DBG_LPX, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_GPIO, 0x39c)
|
||||
FIELD(VERSAL2_RST_GPIO, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_TTC, 0x3a0)
|
||||
FIELD(VERSAL2_RST_TTC, TTC7_RESET, 7, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC6_RESET, 6, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC5_RESET, 5, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC4_RESET, 4, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC3_RESET, 3, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC2_RESET, 2, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC1_RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC0_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_TIMESTAMP, 0x3a4)
|
||||
FIELD(VERSAL2_RST_TIMESTAMP, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT0, 0x3a8)
|
||||
FIELD(VERSAL2_RST_SWDT0, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT1, 0x3ac)
|
||||
FIELD(VERSAL2_RST_SWDT1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT2, 0x3b0)
|
||||
FIELD(VERSAL2_RST_SWDT2, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT3, 0x3b4)
|
||||
FIELD(VERSAL2_RST_SWDT3, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT4, 0x3b8)
|
||||
FIELD(VERSAL2_RST_SWDT4, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_IPI, 0x3bc)
|
||||
FIELD(VERSAL2_RST_IPI, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SYSMON, 0x3c0)
|
||||
FIELD(VERSAL2_RST_SYSMON, CFG_RST, 0, 1)
|
||||
REG32(VERSAL2_ASU_MB_RST_MODE, 0x3c4)
|
||||
FIELD(VERSAL2_ASU_MB_RST_MODE, WAKEUP, 2, 1)
|
||||
FIELD(VERSAL2_ASU_MB_RST_MODE, RST_MODE, 0, 2)
|
||||
REG32(VERSAL2_FPX_TOPSW_MUX_CTRL, 0x3c8)
|
||||
FIELD(VERSAL2_FPX_TOPSW_MUX_CTRL, SELECT, 0, 1)
|
||||
REG32(VERSAL2_RST_FPX, 0x3d0)
|
||||
FIELD(VERSAL2_RST_FPX, SRST, 1, 1)
|
||||
FIELD(VERSAL2_RST_FPX, POR, 0, 1)
|
||||
REG32(VERSAL2_RST_MMI, 0x3d4)
|
||||
FIELD(VERSAL2_RST_MMI, POR, 0, 1)
|
||||
REG32(VERSAL2_RST_OCM, 0x3d8)
|
||||
FIELD(VERSAL2_RST_OCM, RESET_OCM3, 3, 1)
|
||||
FIELD(VERSAL2_RST_OCM, RESET_OCM2, 2, 1)
|
||||
FIELD(VERSAL2_RST_OCM, RESET_OCM1, 1, 1)
|
||||
FIELD(VERSAL2_RST_OCM, RESET_OCM0, 0, 1)
|
||||
|
||||
#define VERSAL2_CRL_R_MAX (R_VERSAL2_RST_OCM + 1)
|
||||
|
||||
struct XlnxVersalCRLBase {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
RegisterInfoArray *reg_array;
|
||||
uint32_t *regs;
|
||||
};
|
||||
|
||||
struct XlnxVersalCRLBaseClass {
|
||||
SysBusDeviceClass parent_class;
|
||||
|
||||
DeviceState ** (*decode_periph_rst)(XlnxVersalCRLBase *s, hwaddr, size_t *);
|
||||
};
|
||||
|
||||
struct XlnxVersalCRL {
|
||||
SysBusDevice parent_obj;
|
||||
XlnxVersalCRLBase parent_obj;
|
||||
qemu_irq irq;
|
||||
|
||||
struct {
|
||||
ARMCPU *cpu_r5[RPU_MAX_CPU];
|
||||
DeviceState *rpu[2];
|
||||
DeviceState *adma[8];
|
||||
DeviceState *uart[2];
|
||||
DeviceState *gem[2];
|
||||
DeviceState *usb;
|
||||
DeviceState *usb[1];
|
||||
} cfg;
|
||||
|
||||
RegisterInfoArray *reg_array;
|
||||
uint32_t regs[CRL_R_MAX];
|
||||
RegisterInfo regs_info[CRL_R_MAX];
|
||||
};
|
||||
|
||||
struct XlnxVersal2CRL {
|
||||
XlnxVersalCRLBase parent_obj;
|
||||
|
||||
struct {
|
||||
DeviceState *rpu[10];
|
||||
DeviceState *adma[8];
|
||||
DeviceState *sdma[8];
|
||||
DeviceState *uart[2];
|
||||
DeviceState *gem[2];
|
||||
DeviceState *usb[2];
|
||||
DeviceState *can[4];
|
||||
} cfg;
|
||||
|
||||
RegisterInfo regs_info[VERSAL2_CRL_R_MAX];
|
||||
uint32_t regs[VERSAL2_CRL_R_MAX];
|
||||
};
|
||||
|
||||
static inline const char *xlnx_versal_crl_class_name(VersalVersion ver)
|
||||
{
|
||||
switch (ver) {
|
||||
case VERSAL_VER_VERSAL:
|
||||
return TYPE_XLNX_VERSAL_CRL;
|
||||
case VERSAL_VER_VERSAL2:
|
||||
return TYPE_XLNX_VERSAL2_CRL;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1091,6 +1091,11 @@ static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
|
||||
return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) != 0;
|
||||
}
|
||||
|
||||
static inline bool isar_feature_aa64_rme_gpc2(const ARMISARegisters *id)
|
||||
{
|
||||
return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) >= 2;
|
||||
}
|
||||
|
||||
static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
|
||||
{
|
||||
return FIELD_EX64_IDREG(id, ID_AA64PFR0, DIT) != 0;
|
||||
|
||||
@@ -1995,13 +1995,19 @@ FIELD(V7M_VPR, MASK01, 16, 4)
|
||||
FIELD(V7M_VPR, MASK23, 20, 4)
|
||||
|
||||
FIELD(GPCCR, PPS, 0, 3)
|
||||
FIELD(GPCCR, RLPAD, 5, 1)
|
||||
FIELD(GPCCR, NSPAD, 6, 1)
|
||||
FIELD(GPCCR, SPAD, 7, 1)
|
||||
FIELD(GPCCR, IRGN, 8, 2)
|
||||
FIELD(GPCCR, ORGN, 10, 2)
|
||||
FIELD(GPCCR, SH, 12, 2)
|
||||
FIELD(GPCCR, PGS, 14, 2)
|
||||
FIELD(GPCCR, GPC, 16, 1)
|
||||
FIELD(GPCCR, GPCP, 17, 1)
|
||||
FIELD(GPCCR, TBGPCD, 18, 1)
|
||||
FIELD(GPCCR, NSO, 19, 1)
|
||||
FIELD(GPCCR, L0GPTSZ, 20, 4)
|
||||
FIELD(GPCCR, APPSAA, 24, 1)
|
||||
|
||||
FIELD(MFAR, FPA, 12, 40)
|
||||
FIELD(MFAR, NSE, 62, 1)
|
||||
|
||||
+7
-1
@@ -3742,7 +3742,8 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
|
||||
value &= valid_mask;
|
||||
|
||||
/* RW is RAO/WI if EL1 is AArch64 only */
|
||||
if (!cpu_isar_feature(aa64_aa32_el1, cpu)) {
|
||||
if (arm_feature(env, ARM_FEATURE_AARCH64) &&
|
||||
!cpu_isar_feature(aa64_aa32_el1, cpu)) {
|
||||
value |= HCR_RW;
|
||||
}
|
||||
|
||||
@@ -4932,6 +4933,11 @@ static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK |
|
||||
R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK;
|
||||
|
||||
if (cpu_isar_feature(aa64_rme_gpc2, env_archcpu(env))) {
|
||||
rw_mask |= R_GPCCR_APPSAA_MASK | R_GPCCR_NSO_MASK |
|
||||
R_GPCCR_SPAD_MASK | R_GPCCR_NSPAD_MASK | R_GPCCR_RLPAD_MASK;
|
||||
}
|
||||
|
||||
env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask);
|
||||
}
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user