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https://github.com/izzy2lost/xemu.git
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Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210317' into staging
TCI argument extraction helpers and disassembler TCG build fix for gcc 11 # gpg: Signature made Wed 17 Mar 2021 15:29:47 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210317: (38 commits) tcg: Fix prototypes for tcg_out_vec_op and tcg_out_op tcg/tci: Split out tcg_out_op_r[iI] tcg/tci: Split out tcg_out_op_v tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} tcg/tci: Split out tcg_out_op_rrrrcl tcg/tci: Split out tcg_out_op_rrrr tcg/tci: Split out tcg_out_op_rrrrrr tcg/tci: Split out tcg_out_op_rrcl tcg/tci: Split out tcg_out_op_rrrbb tcg/tci: Split out tcg_out_op_rrrrrc tcg/tci: Split out tcg_out_op_rrrc tcg/tci: Split out tcg_out_op_rrr tcg/tci: Split out tcg_out_op_rr tcg/tci: Split out tcg_out_op_p tcg/tci: Split out tcg_out_op_l tcg/tci: Split out tcg_out_op_rrs tcg/tci: Push opcode emit into each case tcg/tci: Implement the disassembler properly tcg/tci: Remove tci_disas tcg/tci: Hoist op_size checking into tci_args_* ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
-61
@@ -1,61 +0,0 @@
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/*
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* Tiny Code Interpreter for QEMU - disassembler
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*
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* Copyright (c) 2011 Stefan Weil
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "disas/dis-asm.h"
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#include "tcg/tcg.h"
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/* Disassemble TCI bytecode. */
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int print_insn_tci(bfd_vma addr, disassemble_info *info)
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{
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int length;
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uint8_t byte;
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int status;
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TCGOpcode op;
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status = info->read_memory_func(addr, &byte, 1, info);
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if (status != 0) {
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info->memory_error_func(status, addr, info);
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return -1;
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}
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op = byte;
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addr++;
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status = info->read_memory_func(addr, &byte, 1, info);
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if (status != 0) {
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info->memory_error_func(status, addr, info);
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return -1;
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}
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length = byte;
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if (op >= tcg_op_defs_max) {
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info->fprintf_func(info->stream, "illegal opcode %d", op);
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} else {
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const TCGOpDef *def = &tcg_op_defs[op];
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int nb_oargs = def->nb_oargs;
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int nb_iargs = def->nb_iargs;
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int nb_cargs = def->nb_cargs;
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/* TODO: Improve disassembler output. */
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info->fprintf_func(info->stream, "%s\to=%d i=%d c=%d",
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def->name, nb_oargs, nb_iargs, nb_cargs);
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}
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return length;
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}
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@@ -278,10 +278,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
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#ifdef TCG_TARGET_INTERPRETER
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/* These opcodes are only for use between the tci generator and interpreter. */
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DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
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#if TCG_TARGET_REG_BITS == 64
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DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
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#endif
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#endif
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#undef TLADDR_ARGS
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#undef DATA64_ARGS
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+1
-1
@@ -1943,7 +1943,7 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files(
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'tcg/tcg-op.c',
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'tcg/tcg.c',
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))
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specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('disas/tci.c', 'tcg/tci.c'))
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specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'))
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subdir('backends')
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subdir('disas')
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@@ -2286,7 +2286,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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unsigned vecl, unsigned vece,
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const TCGArg *args, const int *const_args)
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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static const AArch64Insn cmp_vec_insn[16] = {
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[TCG_COND_EQ] = I3616_CMEQ,
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@@ -2177,7 +2177,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
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}
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static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg *args, const int *const_args)
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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TCGArg a0, a1, a2;
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int c, const_a2, vexop, rexw = 0;
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@@ -2613,7 +2614,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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unsigned vecl, unsigned vece,
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const TCGArg *args, const int *const_args)
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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static int const add_insn[4] = {
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OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ
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@@ -1651,7 +1651,8 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
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}
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static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg *args, const int *const_args)
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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MIPSInsn i1, i2;
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TCGArg a0, a1, a2;
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@@ -2319,8 +2319,9 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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tcg_out32(s, BCLR | BO_ALWAYS);
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}
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static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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const int *const_args)
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static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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TCGArg a0, a1, a2;
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int c;
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@@ -3115,7 +3116,8 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
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static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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unsigned vecl, unsigned vece,
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const TCGArg *args, const int *const_args)
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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static const uint32_t
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add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
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@@ -1212,7 +1212,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
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static const tcg_insn_unit *tb_ret_addr;
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static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg *args, const int *const_args)
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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TCGArg a0 = args[0];
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TCGArg a1 = args[1];
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@@ -1705,7 +1705,8 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
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case glue(glue(INDEX_op_,x),_i64)
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static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg *args, const int *const_args)
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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S390Opcode op, op2;
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TCGArg a0, a1, a2;
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@@ -107,8 +107,9 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
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static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
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static void tcg_out_movi(TCGContext *s, TCGType type,
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TCGReg ret, tcg_target_long arg);
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static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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const int *const_args);
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static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS]);
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#if TCG_TARGET_MAYBE_vec
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static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg dst, TCGReg src);
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@@ -116,9 +117,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg dst, TCGReg base, intptr_t offset);
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static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg dst, int64_t arg);
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static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
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unsigned vece, const TCGArg *args,
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const int *const_args);
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static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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unsigned vecl, unsigned vece,
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS]);
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#else
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static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg dst, TCGReg src)
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@@ -135,9 +137,10 @@ static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
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{
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g_assert_not_reached();
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}
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static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
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unsigned vece, const TCGArg *args,
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const int *const_args)
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static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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unsigned vecl, unsigned vece,
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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g_assert_not_reached();
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}
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@@ -13,7 +13,6 @@ C_O0_I2(r, r)
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C_O0_I3(r, r, r)
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C_O0_I4(r, r, r, r)
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C_O1_I1(r, r)
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C_O1_I2(r, 0, r)
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C_O1_I2(r, r, r)
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C_O1_I4(r, r, r, r, r)
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C_O2_I1(r, r, r)
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+331
-155
File diff suppressed because it is too large
Load Diff
+3
-10
@@ -87,7 +87,7 @@
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_goto_ptr 0
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#define TCG_TARGET_HAS_direct_jump 1
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#define TCG_TARGET_HAS_direct_jump 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#if TCG_TARGET_REG_BITS == 64
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@@ -163,8 +163,6 @@ typedef enum {
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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#define TCG_TARGET_STACK_ALIGN 16
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void tci_disas(uint8_t opc);
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#define HAVE_TCG_QEMU_TB_EXEC
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/* We could notice __i386__ or __s390x__ and reduce the barriers depending
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@@ -174,12 +172,7 @@ void tci_disas(uint8_t opc);
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#define TCG_TARGET_HAS_MEMORY_BSWAP 1
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static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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uintptr_t jmp_rw, uintptr_t addr)
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{
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/* patch the branch destination */
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qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4));
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/* no need to flush icache explicitly */
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}
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/* not defined -- call should be eliminated at compile time */
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#endif /* TCG_TARGET_H */
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