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qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device

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For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes,
one of which has bypass_iommu enabled. The generated IORT table contains
a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node.
RC node features 4 ID mappings, of which 2 points to SMMU node and the
remaining ones points to ITS.

       pcie.0 -> {SMMU0} -> {ITS}
{RC}   pcie.1 -> {SMMU0} -> {ITS}
       pcie.2            -> {ITS}
       [all other ids]   -> {ITS}

For the -device arm-smmuv3,... test, the configuration also includes three
Root Complexes, with two connected to separate SMMUv3 devices.
The resulting IORT table contains 1 RC node, 2 SMMU nodes and 1 ITS node.
RC node features 4 ID mappings. 2 of them target the 2 SMMU nodes while
the others targets the ITS.

        pcie.0 -> {SMMU0} -> {ITS}
{RC}    pcie.1 -> {SMMU1} -> {ITS}
        pcie.2            -> {ITS}
        [all other ids]   -> {ITS}

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Reviewed-by: Donald Dutile <ddutile@redhat.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Message-id: 20250829082543.7680-11-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Shameer Kolothum
2025-09-16 17:31:54 +01:00
committed by Peter Maydell
parent c69520c13d
commit 3f8cd046c1
1 changed files with 86 additions and 0 deletions
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tests/qtest/bios-tables-test.c
+86
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@@ -2337,6 +2337,86 @@ static void test_acpi_aarch64_virt_viot(void)
free_test_data(&data);
}
static void test_acpi_aarch64_virt_smmuv3_legacy(void)
{
test_data data = {
.machine = "virt",
.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
.ram_start = 0x40000000ULL,
.scan_len = 128ULL * MiB,
};
/*
* cdrom is plugged into scsi controller to avoid conflict
* with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb() for
* details.
*
* The setup includes three PCIe root complexes, one of which has
* bypass_iommu enabled. The generated IORT table contains a single
* SMMUv3 node and a Root Complex node with three ID mappings. Two
* of the ID mappings have output references pointing to the SMMUv3
* node and the remaining one points to ITS.
*/
data.variant = ".smmuv3-legacy";
test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1"
" -device virtio-scsi-pci,id=scsi0,bus=pci.1"
" -drive file="
"tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2,"
"if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
" -device scsi-cd,bus=scsi0.0,scsi-id=0,"
"drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
" -cpu cortex-a57"
" -M iommu=smmuv3"
" -device pxb-pcie,id=pcie.1,bus=pcie.0,bus_nr=0x10"
" -device pxb-pcie,id=pcie.2,bus=pcie.0,bus_nr=0x20,bypass_iommu=on",
&data);
free_test_data(&data);
}
static void test_acpi_aarch64_virt_smmuv3_dev(void)
{
test_data data = {
.machine = "virt",
.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
.ram_start = 0x40000000ULL,
.scan_len = 128ULL * MiB,
};
/*
* cdrom is plugged into scsi controller to avoid conflict
* with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb()
* for details.
*
* The setup includes three PCie root complexes, two of which are
* connected to separate SMMUv3 devices. The resulting IORT table
* contains two SMMUv3 nodes and a Root Complex node with ID mappings
* of which two of the ID mappings have output references pointing
* to two different SMMUv3 nodes and the remaining ones pointing to
* ITS.
*/
data.variant = ".smmuv3-dev";
test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1"
" -device virtio-scsi-pci,id=scsi0,bus=pci.1"
" -drive file="
"tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2,"
"if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
" -device scsi-cd,bus=scsi0.0,scsi-id=0,"
"drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
" -cpu cortex-a57"
" -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0"
" -device pxb-pcie,id=pcie.1,bus=pcie.0,bus_nr=0x10"
" -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1"
" -device pxb-pcie,id=pcie.2,bus=pcie.0,bus_nr=0x20",
&data);
free_test_data(&data);
}
#ifndef _WIN32
# define DEV_NULL "/dev/null"
#else
@@ -2768,6 +2848,12 @@ int main(int argc, char *argv[])
if (qtest_has_device("virtio-iommu-pci")) {
qtest_add_func("acpi/virt/viot", test_acpi_aarch64_virt_viot);
}
qtest_add_func("acpi/virt/smmuv3-legacy",
test_acpi_aarch64_virt_smmuv3_legacy);
if (qtest_has_device("arm-smmuv3")) {
qtest_add_func("acpi/virt/smmuv3-dev",
test_acpi_aarch64_virt_smmuv3_dev);
}
}
} else if (strcmp(arch, "riscv64") == 0) {
if (has_tcg && qtest_has_device("virtio-blk-pci")) {