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Merge tag 'single-binary-20251016' of https://github.com/philmd/qemu into staging

Browse Source 
Various patches related to single binary work:

- Remove some VMSTATE_UINTTL() uses
- Replace target_ulong by vaddr / hwaddr / uint[32,64]_t
- Expand TCGv to TCGv_i32 for 32-bit targets
- Remove some unnecessary checks on TARGET_LONG_BITS
- Replace few HOST_BIG_ENDIAN preprocessor #ifdef by compile-time if() check
- Expand MO_TE to either MO_BE or MO_LE

Also:

- Remove legacy cpu_physical_memory_*() calls
- Fix HPPA FMPYADD opcode
- Unify Clément Mathieu--Drif email addresses

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#
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# mRgeCHD1E0WBDsVV9yi9TnbzDF6SfNZP9XYcSHomrNt9qY0xcQ==
# =M9X9
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 16 Oct 2025 08:09:22 AM PDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'single-binary-20251016' of https://github.com/philmd/qemu: (79 commits)
  mailmap: Unify Clément Mathieu--Drif emails
  linux-user/microblaze: Fix little-endianness binary
  target/xtensa: Remove target_ulong use in xtensa_get_tb_cpu_state()
  target/xtensa: Remove target_ulong use in xtensa_tr_translate_insn()
  target/xtensa: Replace legacy cpu_physical_memory_[un]map() calls
  target/tricore: Expand TCGv type for 32-bit target
  target/tricore: Un-inline various helpers
  target/tricore: Pass DisasContext as first argument
  target/tricore: Expand TCG helpers for 32-bit target
  target/tricore: Inline tcg_gen_ld32u_tl()
  target/tricore: Declare registers as TCGv_i32
  target/tricore: Replace target_ulong -> uint32_t in op_helper.c
  target/tricore: Remove unnecessary cast to target_ulong
  target/tricore: Remove target_ulong use in gen_addi_d()
  target/tricore: Remove target_ulong use in translate_insn() handler
  target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees
  target/tricore: Remove target_ulong use in gen_goto_tb()
  target/sparc: Reduce inclusions of 'exec/cpu-common.h'
  target/sh4: Remove target_ulong use in gen_goto_tb()
  target/sh4: Use vaddr type for TLB virtual addresses
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2025-10-16 12:26:51 -07:00
parent 8109ebdb95 8dd133fa85
commit 3ad3326bd6
66 changed files with 2925 additions and 2888 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.mailmap
+1
View File
@@ -136,6 +136,7 @@ Chen Gang <gang.chen.5i5j@gmail.com>
Chen Gang <gang.chen@sunrus.com.cn>
Chen Wei-Ren <chenwj@iis.sinica.edu.tw>
Christophe Lyon <christophe.lyon@st.com>
Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Collin L. Walling <walling@linux.ibm.com>
Daniel P. Berrangé <berrange@redhat.com>
Eduardo Otubo <otubo@redhat.com>
linux-user/microblaze/elfload.c
+2 -1
View File
@@ -8,7 +8,8 @@
const char *get_elf_cpu_model(uint32_t eflags)
{
return "any";
return TARGET_BIG_ENDIAN ? "any,little-endian=off"
: "any,little-endian=on";
}
void elf_core_copy_regs(target_elf_gregset_t *r, const CPUMBState *env)
target/alpha/helper.h
+1
View File
@@ -92,6 +92,7 @@ DEF_HELPER_FLAGS_1(tbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(tbis, TCG_CALL_NO_RWG, void, env, i64)
DEF_HELPER_1(halt, void, i64)
DEF_HELPER_1(whami, i64, env)
DEF_HELPER_FLAGS_0(get_vmtime, TCG_CALL_NO_RWG, i64)
DEF_HELPER_FLAGS_0(get_walltime, TCG_CALL_NO_RWG, i64)
target/alpha/machine.c
+17 -17
View File
@@ -25,8 +25,8 @@ static const VMStateInfo vmstate_fpcr = {
};
static const VMStateField vmstate_env_fields[] = {
VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31),
VMSTATE_UINTTL_ARRAY(fir, CPUAlphaState, 31),
VMSTATE_UINT64_ARRAY(ir, CPUAlphaState, 31),
VMSTATE_UINT64_ARRAY(fir, CPUAlphaState, 31),
/* Save the architecture value of the fpcr, not the internally
expanded version. Since this architecture value does not
exist in memory to be stored, this requires a but of hoop
@@ -41,27 +41,27 @@ static const VMStateField vmstate_env_fields[] = {
.flags = VMS_SINGLE,
.offset = 0
},
VMSTATE_UINTTL(pc, CPUAlphaState),
VMSTATE_UINTTL(unique, CPUAlphaState),
VMSTATE_UINTTL(lock_addr, CPUAlphaState),
VMSTATE_UINTTL(lock_value, CPUAlphaState),
VMSTATE_UINT64(pc, CPUAlphaState),
VMSTATE_UINT64(unique, CPUAlphaState),
VMSTATE_UINT64(lock_addr, CPUAlphaState),
VMSTATE_UINT64(lock_value, CPUAlphaState),
VMSTATE_UINT32(flags, CPUAlphaState),
VMSTATE_UINT32(pcc_ofs, CPUAlphaState),
VMSTATE_UINTTL(trap_arg0, CPUAlphaState),
VMSTATE_UINTTL(trap_arg1, CPUAlphaState),
VMSTATE_UINTTL(trap_arg2, CPUAlphaState),
VMSTATE_UINT64(trap_arg0, CPUAlphaState),
VMSTATE_UINT64(trap_arg1, CPUAlphaState),
VMSTATE_UINT64(trap_arg2, CPUAlphaState),
VMSTATE_UINTTL(exc_addr, CPUAlphaState),
VMSTATE_UINTTL(palbr, CPUAlphaState),
VMSTATE_UINTTL(ptbr, CPUAlphaState),
VMSTATE_UINTTL(vptptr, CPUAlphaState),
VMSTATE_UINTTL(sysval, CPUAlphaState),
VMSTATE_UINTTL(usp, CPUAlphaState),
VMSTATE_UINT64(exc_addr, CPUAlphaState),
VMSTATE_UINT64(palbr, CPUAlphaState),
VMSTATE_UINT64(ptbr, CPUAlphaState),
VMSTATE_UINT64(vptptr, CPUAlphaState),
VMSTATE_UINT64(sysval, CPUAlphaState),
VMSTATE_UINT64(usp, CPUAlphaState),
VMSTATE_UINTTL_ARRAY(shadow, CPUAlphaState, 8),
VMSTATE_UINTTL_ARRAY(scratch, CPUAlphaState, 24),
VMSTATE_UINT64_ARRAY(shadow, CPUAlphaState, 8),
VMSTATE_UINT64_ARRAY(scratch, CPUAlphaState, 24),
VMSTATE_END_OF_LIST()
};
target/alpha/sys_helper.c
+5
View File
@@ -67,3 +67,8 @@ void helper_set_alarm(CPUAlphaState *env, uint64_t expire)
timer_del(cpu->alarm_timer);
}
}
uint64_t HELPER(whami)(CPUAlphaState *env)
{
return env_cpu(env)->cpu_index;
}
target/alpha/translate.c
+5 -6
View File
@@ -436,18 +436,18 @@ static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
return DISAS_NEXT;
}
static void gen_goto_tb(DisasContext *ctx, int idx, int32_t disp)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx, int32_t disp)
{
if (translator_use_goto_tb(&ctx->base, ctx->base.pc_next + disp)) {
/* With PCREL, PC must always be up-to-date. */
if (ctx->pcrel) {
gen_pc_disp(ctx, cpu_pc, disp);
tcg_gen_goto_tb(idx);
tcg_gen_goto_tb(tb_slot_idx);
} else {
tcg_gen_goto_tb(idx);
tcg_gen_goto_tb(tb_slot_idx);
gen_pc_disp(ctx, cpu_pc, disp);
}
tcg_gen_exit_tb(ctx->base.tb, idx);
tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
gen_pc_disp(ctx, cpu_pc, disp);
tcg_gen_lookup_and_goto_ptr();
@@ -1126,8 +1126,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
break;
case 0x3C:
/* WHAMI */
tcg_gen_ld32s_i64(ctx->ir[IR_V0], tcg_env,
-offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index));
gen_helper_whami(ctx->ir[IR_V0], tcg_env);
break;
case 0x3E:
target/arm/tcg/translate-a64.c
+4 -4
View File
@@ -528,7 +528,7 @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest)
return translator_use_goto_tb(&s->base, dest);
}
static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, int64_t diff)
{
if (use_goto_tb(s, s->pc_curr + diff)) {
/*
@@ -541,12 +541,12 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
*/
if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_a64_update_pc(s, diff);
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
} else {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
gen_a64_update_pc(s, diff);
}
tcg_gen_exit_tb(s->base.tb, n);
tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
s->base.is_jmp = DISAS_NORETURN;
} else {
gen_a64_update_pc(s, diff);
target/arm/tcg/translate.c
+4 -4
View File
@@ -1310,7 +1310,7 @@ static void gen_goto_ptr(void)
* cpu_loop_exec. Any live exit_requests will be processed as we
* enter the next TB.
*/
static void gen_goto_tb(DisasContext *s, int n, target_long diff)
static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, target_long diff)
{
if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) {
/*
@@ -1323,12 +1323,12 @@ static void gen_goto_tb(DisasContext *s, int n, target_long diff)
*/
if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_update_pc(s, diff);
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
} else {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
gen_update_pc(s, diff);
}
tcg_gen_exit_tb(s->base.tb, n);
tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
} else {
gen_update_pc(s, diff);
gen_goto_ptr();
target/avr/translate.c
+4 -3
View File
@@ -981,14 +981,15 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret)
}
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
target_ulong dest)
{
const TranslationBlock *tb = ctx->base.tb;
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_exit_tb(tb, n);
tcg_gen_exit_tb(tb, tb_slot_idx);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_lookup_and_goto_ptr();
target/hexagon/translate.c
+4 -4
View File
@@ -133,15 +133,15 @@ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
return translator_use_goto_tb(&ctx->base, dest);
}
static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest, bool
move_to_pc)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
target_ulong dest, bool move_to_pc)
{
if (use_goto_tb(ctx, dest)) {
tcg_gen_goto_tb(idx);
tcg_gen_goto_tb(tb_slot_idx);
if (move_to_pc) {
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
}
tcg_gen_exit_tb(ctx->base.tb, idx);
tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
if (move_to_pc) {
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
target/hppa/cpu.h
+5 -5
View File
@@ -187,7 +187,7 @@ typedef struct HPPATLBEntry {
struct HPPATLBEntry *unused_next;
};
target_ulong pa;
hwaddr pa;
unsigned entry_valid : 1;
@@ -320,8 +320,8 @@ void hppa_translate_code(CPUState *cs, TranslationBlock *tb,
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
static inline target_ulong hppa_form_gva_mask(uint64_t gva_offset_mask,
uint64_t spc, target_ulong off)
static inline vaddr hppa_form_gva_mask(uint64_t gva_offset_mask,
uint64_t spc, target_ulong off)
{
#ifdef CONFIG_USER_ONLY
return off & gva_offset_mask;
@@ -330,8 +330,8 @@ static inline target_ulong hppa_form_gva_mask(uint64_t gva_offset_mask,
#endif
}
static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
target_ulong off)
static inline vaddr hppa_form_gva(CPUHPPAState *env, uint64_t spc,
target_ulong off)
{
return hppa_form_gva_mask(env->gva_offset_mask, spc, off);
}
target/hppa/helper.c
+2 -2
View File
@@ -148,8 +148,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
m = UINT32_MAX;
}
qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n"
"IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n",
qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (0x%" VADDR_PRIx ")\n"
"IA_B %08" PRIx64 ":%0*" PRIx64 " (0x%" VADDR_PRIx ")\n",
env->iasq_f >> 32, w, m & env->iaoq_f,
hppa_form_gva_mask(env->gva_offset_mask, env->iasq_f,
env->iaoq_f),
target/hppa/insns.decode
+4 -4
View File
@@ -365,10 +365,10 @@ fstd 011100 ..... ..... .. ............1. @ldstim11
&mpyadd rm1 rm2 ta ra tm
@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd
fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd
fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd
fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd
fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
fmpyadd_f 000110 ..... ..... ..... ..... 1 ..... @mpyadd
fmpyadd_d 000110 ..... ..... ..... ..... 0 ..... @mpyadd
fmpysub_f 100110 ..... ..... ..... ..... 1 ..... @mpyadd
fmpysub_d 100110 ..... ..... ..... ..... 0 ..... @mpyadd
####
# Conditional Branches
target/hppa/mem_helper.c
+1 -1
View File
@@ -803,7 +803,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
uint64_t HELPER(b_gate_priv)(CPUHPPAState *env, uint64_t iaoq_f)
{
uint64_t gva = hppa_form_gva(env, env->iasq_f, iaoq_f);
vaddr gva = hppa_form_gva(env, env->iasq_f, iaoq_f);
HPPATLBEntry *ent = hppa_find_tlb(env, gva);
if (ent == NULL) {
target/hppa/trace-events
+3 -3
View File
@@ -1,13 +1,13 @@
# See docs/devel/tracing.rst for syntax documentation.
# mem_helper.c
disable hppa_tlb_flush_ent(void *env, void *ent, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p va_b=0x%lx va_e=0x%lx pa=0x%lx"
disable hppa_tlb_find_entry(void *env, void *ent, int valid, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p valid=%d va_b=0x%lx va_e=0x%lx pa=0x%lx"
disable hppa_tlb_flush_ent(void *env, void *ent, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p va_b=0x%lx va_e=0x%lx pa=0x%" PRIx64
disable hppa_tlb_find_entry(void *env, void *ent, int valid, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p valid=%d va_b=0x%lx va_e=0x%lx pa=0x%" PRIx64
disable hppa_tlb_find_entry_not_found(void *env, uint64_t addr) "env=%p addr=%08lx"
disable hppa_tlb_get_physical_address(void *env, int ret, int prot, uint64_t addr, uint64_t phys) "env=%p ret=%d prot=%d addr=0x%lx phys=0x%lx"
disable hppa_tlb_fill_excp(void *env, uint64_t addr, int size, int type, int mmu_idx) "env=%p addr=0x%lx size=%d type=%d mmu_idx=%d"
disable hppa_tlb_fill_success(void *env, uint64_t addr, uint64_t phys, int size, int type, int mmu_idx) "env=%p addr=0x%lx phys=0x%lx size=%d type=%d mmu_idx=%d"
disable hppa_tlb_itlba(void *env, void *ent, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p va_b=0x%lx va_e=0x%lx pa=0x%lx"
disable hppa_tlb_itlba(void *env, void *ent, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p va_b=0x%lx va_e=0x%lx pa=0x%" PRIx64
disable hppa_tlb_itlbp(void *env, void *ent, int access_id, int u, int pl2, int pl1, int type, int b, int d, int t) "env=%p ent=%p access_id=%x u=%d pl2=%d pl1=%d type=%d b=%d d=%d t=%d"
disable hppa_tlb_ptlb(void *env) "env=%p"
disable hppa_tlb_ptlb_local(void *env) "env=%p"
target/hppa/translate.c
+17 -7
View File
@@ -104,6 +104,12 @@ typedef struct DisasContext {
#define MMU_DISABLED(C) MMU_IDX_MMU_DISABLED((C)->mmu_idx)
#endif
static inline MemOp mo_endian(DisasContext *ctx)
{
/* The PSW_E bit sets the (little) endianness, but we don't implement it. */
return MO_BE;
}
/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
static int expand_sm_imm(DisasContext *ctx, int val)
{
@@ -1599,6 +1605,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
mop |= mo_endian(ctx);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
MMU_DISABLED(ctx));
tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
@@ -1617,6 +1624,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
mop |= mo_endian(ctx);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
MMU_DISABLED(ctx));
tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
@@ -1635,6 +1643,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
mop |= mo_endian(ctx);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
MMU_DISABLED(ctx));
tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
@@ -1653,6 +1662,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
mop |= mo_endian(ctx);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
MMU_DISABLED(ctx));
tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
@@ -1691,7 +1701,7 @@ static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb,
nullify_over(ctx);
tmp = tcg_temp_new_i32();
do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL);
do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_UL);
save_frw_i32(rt, tmp);
if (rt == 0) {
@@ -1716,7 +1726,7 @@ static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb,
nullify_over(ctx);
tmp = tcg_temp_new_i64();
do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ);
do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_UQ);
save_frd(rt, tmp);
if (rt == 0) {
@@ -1750,7 +1760,7 @@ static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
nullify_over(ctx);
tmp = load_frw_i32(rt);
do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL);
do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_UL);
return nullify_end(ctx);
}
@@ -1770,7 +1780,7 @@ static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb,
nullify_over(ctx);
tmp = load_frd(rt);
do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ);
do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_UQ);
return nullify_end(ctx);
}
@@ -3302,7 +3312,7 @@ static bool trans_ld(DisasContext *ctx, arg_ldst *a)
return gen_illegal(ctx);
}
return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
a->disp, a->sp, a->m, a->size | MO_TE);
a->disp, a->sp, a->m, a->size);
}
static bool trans_st(DisasContext *ctx, arg_ldst *a)
@@ -3311,12 +3321,12 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a)
if (!ctx->is_pa20 && a->size > MO_32) {
return gen_illegal(ctx);
}
return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size);
}
static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
{
MemOp mop = MO_TE | MO_ALIGN | a->size;
MemOp mop = mo_endian(ctx) | MO_ALIGN | a->size;
TCGv_i64 dest, ofs;
TCGv_i64 addr;
target/i386/monitor.c
+65 -69
View File
@@ -30,6 +30,7 @@
#include "qobject/qdict.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc.h"
#include "system/memory.h"
/* Perform linear address sign extension */
static hwaddr addr_canonical(CPUArchState *env, hwaddr addr)
@@ -68,23 +69,23 @@ static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
pte & PG_RW_MASK ? 'W' : '-');
}
static void tlb_info_32(Monitor *mon, CPUArchState *env)
static void tlb_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2;
uint32_t pgd, pde, pte;
pgd = env->cr[3] & ~0xfff;
for(l1 = 0; l1 < 1024; l1++) {
cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
pde = le32_to_cpu(pde);
pde = address_space_ldl_le(as, pgd + l1 * 4, attrs, NULL);
if (pde & PG_PRESENT_MASK) {
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
/* 4M pages */
print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1));
} else {
for(l2 = 0; l2 < 1024; l2++) {
cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
pte = le32_to_cpu(pte);
pte = address_space_ldl_le(as, (pde & ~0xfff) + l2 * 4,
attrs, NULL);
if (pte & PG_PRESENT_MASK) {
print_pte(mon, env, (l1 << 22) + (l2 << 12),
pte & ~PG_PSE_MASK,
@@ -96,21 +97,20 @@ static void tlb_info_32(Monitor *mon, CPUArchState *env)
}
}
static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
static void tlb_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2, l3;
uint64_t pdpe, pde, pte;
uint64_t pdp_addr, pd_addr, pt_addr;
pdp_addr = env->cr[3] & ~0x1f;
for (l1 = 0; l1 < 4; l1++) {
cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l1 * 8, attrs, NULL);
if (pdpe & PG_PRESENT_MASK) {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l2 * 8, attrs, NULL);
if (pde & PG_PRESENT_MASK) {
if (pde & PG_PSE_MASK) {
/* 2M pages with PAE, CR4.PSE is ignored */
@@ -119,8 +119,8 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as, pt_addr + l3 * 8,
attrs, NULL);
if (pte & PG_PRESENT_MASK) {
print_pte(mon, env, (l1 << 30) + (l2 << 21)
+ (l3 << 12),
@@ -136,24 +136,23 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
}
#ifdef TARGET_X86_64
static void tlb_info_la48(Monitor *mon, CPUArchState *env,
static void tlb_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as,
uint64_t l0, uint64_t pml4_addr)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
uint64_t l1, l2, l3, l4;
uint64_t pml4e, pdpe, pde, pte;
uint64_t pdp_addr, pd_addr, pt_addr;
for (l1 = 0; l1 < 512; l1++) {
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
pml4e = le64_to_cpu(pml4e);
pml4e = address_space_ldq_le(as, pml4_addr + l1 * 8, attrs, NULL);
if (!(pml4e & PG_PRESENT_MASK)) {
continue;
}
pdp_addr = pml4e & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l2 * 8, attrs, NULL);
if (!(pdpe & PG_PRESENT_MASK)) {
continue;
}
@@ -167,8 +166,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env,
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l3 * 8, attrs, NULL);
if (!(pde & PG_PRESENT_MASK)) {
continue;
}
@@ -182,10 +180,8 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env,
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
cpu_physical_memory_read(pt_addr
+ l4 * 8,
&pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as, pt_addr + l4 * 8,
attrs, NULL);
if (pte & PG_PRESENT_MASK) {
print_pte(mon, env, (l0 << 48) + (l1 << 39) +
(l2 << 30) + (l3 << 21) + (l4 << 12),
@@ -197,18 +193,18 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env,
}
}
static void tlb_info_la57(Monitor *mon, CPUArchState *env)
static void tlb_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
uint64_t l0;
uint64_t pml5e;
uint64_t pml5_addr;
pml5_addr = env->cr[3] & 0x3fffffffff000ULL;
for (l0 = 0; l0 < 512; l0++) {
cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
pml5e = le64_to_cpu(pml5e);
pml5e = address_space_ldq_le(as, pml5_addr + l0 * 8, attrs, NULL);
if (pml5e & PG_PRESENT_MASK) {
tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL);
tlb_info_la48(mon, env, as, l0, pml5e & 0x3fffffffff000ULL);
}
}
}
@@ -217,6 +213,7 @@ static void tlb_info_la57(Monitor *mon, CPUArchState *env)
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
{
CPUArchState *env;
AddressSpace *as;
env = mon_get_cpu_env(mon);
if (!env) {
@@ -228,21 +225,22 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "PG disabled\n");
return;
}
as = cpu_get_address_space(env_cpu(env), X86ASIdx_MEM);
if (env->cr[4] & CR4_PAE_MASK) {
#ifdef TARGET_X86_64
if (env->hflags & HF_LMA_MASK) {
if (env->cr[4] & CR4_LA57_MASK) {
tlb_info_la57(mon, env);
tlb_info_la57(mon, env, as);
} else {
tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL);
tlb_info_la48(mon, env, as, 0, env->cr[3] & 0x3fffffffff000ULL);
}
} else
#endif
{
tlb_info_pae32(mon, env);
tlb_info_pae32(mon, env, as);
}
} else {
tlb_info_32(mon, env);
tlb_info_32(mon, env, as);
}
}
@@ -271,8 +269,9 @@ static void mem_print(Monitor *mon, CPUArchState *env,
}
}
static void mem_info_32(Monitor *mon, CPUArchState *env)
static void mem_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2;
int prot, last_prot;
uint32_t pgd, pde, pte;
@@ -282,8 +281,7 @@ static void mem_info_32(Monitor *mon, CPUArchState *env)
last_prot = 0;
start = -1;
for(l1 = 0; l1 < 1024; l1++) {
cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
pde = le32_to_cpu(pde);
pde = address_space_ldl_le(as, pgd + l1 * 4, attrs, NULL);
end = l1 << 22;
if (pde & PG_PRESENT_MASK) {
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
@@ -291,8 +289,8 @@ static void mem_info_32(Monitor *mon, CPUArchState *env)
mem_print(mon, env, &start, &last_prot, end, prot);
} else {
for(l2 = 0; l2 < 1024; l2++) {
cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
pte = le32_to_cpu(pte);
pte = address_space_ldl_le(as, (pde & ~0xfff) + l2 * 4,
attrs, NULL);
end = (l1 << 22) + (l2 << 12);
if (pte & PG_PRESENT_MASK) {
prot = pte & pde &
@@ -312,8 +310,9 @@ static void mem_info_32(Monitor *mon, CPUArchState *env)
mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 32, 0);
}
static void mem_info_pae32(Monitor *mon, CPUArchState *env)
static void mem_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2, l3;
int prot, last_prot;
uint64_t pdpe, pde, pte;
@@ -324,14 +323,12 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
last_prot = 0;
start = -1;
for (l1 = 0; l1 < 4; l1++) {
cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l1 * 8, attrs, NULL);
end = l1 << 30;
if (pdpe & PG_PRESENT_MASK) {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l2 * 8, attrs, NULL);
end = (l1 << 30) + (l2 << 21);
if (pde & PG_PRESENT_MASK) {
if (pde & PG_PSE_MASK) {
@@ -341,8 +338,8 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as, pt_addr + l3 * 8,
attrs, NULL);
end = (l1 << 30) + (l2 << 21) + (l3 << 12);
if (pte & PG_PRESENT_MASK) {
prot = pte & pde & (PG_USER_MASK | PG_RW_MASK |
@@ -369,8 +366,9 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
#ifdef TARGET_X86_64
static void mem_info_la48(Monitor *mon, CPUArchState *env)
static void mem_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int prot, last_prot;
uint64_t l1, l2, l3, l4;
uint64_t pml4e, pdpe, pde, pte;
@@ -380,14 +378,12 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
last_prot = 0;
start = -1;
for (l1 = 0; l1 < 512; l1++) {
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
pml4e = le64_to_cpu(pml4e);
pml4e = address_space_ldq_le(as, pml4_addr + l1 * 8, attrs, NULL);
end = l1 << 39;
if (pml4e & PG_PRESENT_MASK) {
pdp_addr = pml4e & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l2 * 8, attrs, NULL);
end = (l1 << 39) + (l2 << 30);
if (pdpe & PG_PRESENT_MASK) {
if (pdpe & PG_PSE_MASK) {
@@ -398,8 +394,8 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
} else {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l3 * 8,
attrs, NULL);
end = (l1 << 39) + (l2 << 30) + (l3 << 21);
if (pde & PG_PRESENT_MASK) {
if (pde & PG_PSE_MASK) {
@@ -411,10 +407,10 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
cpu_physical_memory_read(pt_addr
+ l4 * 8,
&pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as,
pt_addr
+ l4 * 8,
attrs, NULL);
end = (l1 << 39) + (l2 << 30) +
(l3 << 21) + (l4 << 12);
if (pte & PG_PRESENT_MASK) {
@@ -449,8 +445,9 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 48, 0);
}
static void mem_info_la57(Monitor *mon, CPUArchState *env)
static void mem_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int prot, last_prot;
uint64_t l0, l1, l2, l3, l4;
uint64_t pml5e, pml4e, pdpe, pde, pte;
@@ -460,8 +457,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
last_prot = 0;
start = -1;
for (l0 = 0; l0 < 512; l0++) {
cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
pml5e = le64_to_cpu(pml5e);
pml5e = address_space_ldq_le(as, pml5_addr + l0 * 8, attrs, NULL);
end = l0 << 48;
if (!(pml5e & PG_PRESENT_MASK)) {
prot = 0;
@@ -471,8 +467,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
pml4_addr = pml5e & 0x3fffffffff000ULL;
for (l1 = 0; l1 < 512; l1++) {
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
pml4e = le64_to_cpu(pml4e);
pml4e = address_space_ldq_le(as, pml4_addr + l1 * 8, attrs, NULL);
end = (l0 << 48) + (l1 << 39);
if (!(pml4e & PG_PRESENT_MASK)) {
prot = 0;
@@ -482,8 +477,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
pdp_addr = pml4e & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l2 * 8, attrs, NULL);
end = (l0 << 48) + (l1 << 39) + (l2 << 30);
if (pdpe & PG_PRESENT_MASK) {
prot = 0;
@@ -501,8 +495,8 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l3 * 8,
attrs, NULL);
end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21);
if (pde & PG_PRESENT_MASK) {
prot = 0;
@@ -520,8 +514,8 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
cpu_physical_memory_read(pt_addr + l4 * 8, &pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as, pt_addr + l4 * 8,
attrs, NULL);
end = (l0 << 48) + (l1 << 39) + (l2 << 30) +
(l3 << 21) + (l4 << 12);
if (pte & PG_PRESENT_MASK) {
@@ -545,6 +539,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
void hmp_info_mem(Monitor *mon, const QDict *qdict)
{
CPUArchState *env;
AddressSpace *as;
env = mon_get_cpu_env(mon);
if (!env) {
@@ -556,21 +551,22 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "PG disabled\n");
return;
}
as = cpu_get_address_space(env_cpu(env), X86ASIdx_MEM);
if (env->cr[4] & CR4_PAE_MASK) {
#ifdef TARGET_X86_64
if (env->hflags & HF_LMA_MASK) {
if (env->cr[4] & CR4_LA57_MASK) {
mem_info_la57(mon, env);
mem_info_la57(mon, env, as);
} else {
mem_info_la48(mon, env);
mem_info_la48(mon, env, as);
}
} else
#endif
{
mem_info_pae32(mon, env);
mem_info_pae32(mon, env, as);
}
} else {
mem_info_32(mon, env);
mem_info_32(mon, env, as);
}
}
target/loongarch/cpu-mmu.h
+1 -1
View File
@@ -34,7 +34,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug);
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, target_ulong level);
uint64_t *dir_width, unsigned int level);
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif /* LOONGARCH_CPU_MMU_H */
target/loongarch/cpu_helper.c
+1 -1
View File
@@ -17,7 +17,7 @@
#include "tcg/tcg_loongarch.h"
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, target_ulong level)
uint64_t *dir_width, unsigned int level)
{
switch (level) {
case 1:
target/loongarch/gdbstub.c
+1 -1
View File
@@ -62,7 +62,7 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
CPULoongArchState *env = cpu_env(cs);
target_ulong tmp;
uint64_t tmp;
int length = 0;
if (n < 0 || n > 34) {

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