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https://github.com/izzy2lost/xemu.git
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disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently. This patch adds support for these instructions to the RISC-V disassembler. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner
committed by
Alistair Francis
Alistair Francis
parent
f6f72338d8
commit
318df7238b
@@ -8,6 +8,7 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))
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common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c'))
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common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(
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'riscv.c',
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'riscv-xthead.c',
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'riscv-xventana.c'
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))
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common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,28 @@
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/*
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* QEMU disassembler -- RISC-V specific header (xthead*).
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*
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* Copyright (c) 2023 VRULL GmbH
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef DISAS_RISCV_XTHEAD_H
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#define DISAS_RISCV_XTHEAD_H
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#include "disas/riscv.h"
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extern const rv_opcode_data xthead_opcode_data[];
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void decode_xtheadba(rv_decode *, rv_isa);
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void decode_xtheadbb(rv_decode *, rv_isa);
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void decode_xtheadbs(rv_decode *, rv_isa);
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void decode_xtheadcmo(rv_decode *, rv_isa);
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void decode_xtheadcondmov(rv_decode *, rv_isa);
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void decode_xtheadfmemidx(rv_decode *, rv_isa);
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void decode_xtheadfmv(rv_decode *, rv_isa);
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void decode_xtheadmac(rv_decode *, rv_isa);
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void decode_xtheadmemidx(rv_decode *, rv_isa);
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void decode_xtheadmempair(rv_decode *, rv_isa);
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void decode_xtheadsync(rv_decode *, rv_isa);
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#endif /* DISAS_RISCV_XTHEAD_H */
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@@ -18,11 +18,13 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "disas/dis-asm.h"
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#include "target/riscv/cpu_cfg.h"
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#include "disas/riscv.h"
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/* Vendor extensions */
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#include "disas/riscv-xthead.h"
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#include "disas/riscv-xventana.h"
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typedef enum {
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@@ -3869,6 +3871,26 @@ static uint32_t operand_zcmp_rlist(rv_inst inst)
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return ((inst << 56) >> 60);
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}
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static uint32_t operand_imm6(rv_inst inst)
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{
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return (inst << 38) >> 60;
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}
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static uint32_t operand_imm2(rv_inst inst)
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{
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return (inst << 37) >> 62;
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}
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static uint32_t operand_immh(rv_inst inst)
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{
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return (inst << 32) >> 58;
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}
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static uint32_t operand_imml(rv_inst inst)
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{
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return (inst << 38) >> 58;
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}
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static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
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{
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int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
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@@ -4233,6 +4255,38 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
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case rv_codec_zcmt_jt:
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dec->imm = operand_tbl_index(inst);
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break;
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case rv_codec_r2_imm5:
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dec->rd = operand_rd(inst);
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dec->rs1 = operand_rs1(inst);
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dec->imm = operand_rs2(inst);
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break;
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case rv_codec_r2:
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dec->rd = operand_rd(inst);
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dec->rs1 = operand_rs1(inst);
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break;
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case rv_codec_r2_imm6:
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dec->rd = operand_rd(inst);
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dec->rs1 = operand_rs1(inst);
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dec->imm = operand_imm6(inst);
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break;
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case rv_codec_r_imm2:
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dec->rd = operand_rd(inst);
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dec->rs1 = operand_rs1(inst);
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dec->rs2 = operand_rs2(inst);
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dec->imm = operand_imm2(inst);
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break;
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case rv_codec_r2_immhl:
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dec->rd = operand_rd(inst);
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dec->rs1 = operand_rs1(inst);
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dec->imm = operand_immh(inst);
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dec->imm1 = operand_imml(inst);
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break;
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case rv_codec_r2_imm2_imm5:
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dec->rd = operand_rd(inst);
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dec->rs1 = operand_rs1(inst);
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dec->imm = sextract32(operand_rs2(inst), 0, 5);
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dec->imm1 = operand_imm2(inst);
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break;
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};
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}
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@@ -4446,6 +4500,10 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
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snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
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append(buf, tmp, buflen);
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break;
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case 'j':
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snprintf(tmp, sizeof(tmp), "%d", dec->imm1);
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append(buf, tmp, buflen);
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break;
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case 'o':
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snprintf(tmp, sizeof(tmp), "%d", dec->imm);
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append(buf, tmp, buflen);
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@@ -4711,6 +4769,17 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
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void (*decode_func)(rv_decode *, rv_isa);
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} decoders[] = {
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{ always_true_p, rvi_opcode_data, decode_inst_opcode },
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{ has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
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{ has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
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{ has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
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{ has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
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{ has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov },
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{ has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx },
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{ has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
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{ has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
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{ has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx },
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{ has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
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{ has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
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{ has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
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};
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@@ -159,6 +159,12 @@ typedef enum {
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rv_codec_zcmp_cm_pushpop,
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rv_codec_zcmp_cm_mv,
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rv_codec_zcmt_jt,
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rv_codec_r2_imm5,
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rv_codec_r2,
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rv_codec_r2_imm6,
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rv_codec_r_imm2,
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rv_codec_r2_immhl,
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rv_codec_r2_imm2_imm5,
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} rv_codec;
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/* structures */
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@@ -185,6 +191,7 @@ typedef struct {
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uint64_t inst;
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const rv_opcode_data *opcode_data;
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int32_t imm;
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int32_t imm1;
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uint16_t op;
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uint8_t codec;
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uint8_t rd;
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@@ -283,5 +290,10 @@ enum {
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#define rv_fmt_push_rlist "O\tx,-i"
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#define rv_fmt_pop_rlist "O\tx,i"
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#define rv_fmt_zcmt_index "O\ti"
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#define rv_fmt_rd_rs1_rs2_imm "O\t0,1,2,i"
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#define rv_fmt_frd_rs1_rs2_imm "O\t3,1,2,i"
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#define rv_fmt_rd_rs1_immh_imml "O\t0,1,i,j"
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#define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j"
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#define rv_fmt_rd2_imm "O\t0,2,(1),i"
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#endif /* DISAS_RISCV_H */
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@@ -157,6 +157,17 @@ static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
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return cfg->ext_ ## ext ; \
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}
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MATERIALISE_EXT_PREDICATE(xtheadba)
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MATERIALISE_EXT_PREDICATE(xtheadbb)
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MATERIALISE_EXT_PREDICATE(xtheadbs)
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MATERIALISE_EXT_PREDICATE(xtheadcmo)
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MATERIALISE_EXT_PREDICATE(xtheadcondmov)
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MATERIALISE_EXT_PREDICATE(xtheadfmemidx)
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MATERIALISE_EXT_PREDICATE(xtheadfmv)
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MATERIALISE_EXT_PREDICATE(xtheadmac)
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MATERIALISE_EXT_PREDICATE(xtheadmemidx)
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MATERIALISE_EXT_PREDICATE(xtheadmempair)
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MATERIALISE_EXT_PREDICATE(xtheadsync)
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MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
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#endif
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