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target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6

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Implement the relationship between CP0.Status.KX, SX and UX. It should not
be possible to set UX bit if SX is 0, the same applies for setting SX if
KX is 0.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Leon Alrae
2015-10-29 16:16:44 +00:00
parent 7540a43a1d
commit 2dcf7908d9
1 changed files with 6 additions and 1 deletions
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target-mips/cpu.h
+6 -1
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@@ -1001,7 +1001,12 @@ static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
if (env->insn_flags & ISA_MIPS32R6) {
bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
#if defined(TARGET_MIPS64)
uint32_t ksux = (1 << CP0St_KX) & val;
ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
val = (val & ~(7 << CP0St_UX)) | ksux;
#endif
if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
mask &= ~(3 << CP0St_KSU);
}