mirror of
https://github.com/izzy2lost/xemu.git
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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-january-25-2019' into staging
MIPS queue for January 25, 2019 # gpg: Signature made Fri 25 Jan 2019 13:25:57 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-january-25-2019: docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models qemu-doc: Add nanoMIPS ISA information tests: tcg: mips: Remove old directories tests: tcg: mips: Add two new Makefiles tests: tcg: mips: Move source files to new locations MAINTAINERS: Update MIPS sections target/mips: Add I6500 core configuration target/mips: nanoMIPS: Fix branch handling disas: nanoMIPS: Amend DSP instructions related comments target/mips: Extend gen_scwp() functionality to support EVA target/mips: Correct the second argument type of cpu_supports_isa() target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers target/mips: nanoMIPS: Remove an unused macro target/mips: nanoMIPS: Remove duplicate macro definitions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
@@ -206,7 +206,6 @@ MIPS
|
||||
M: Aurelien Jarno <aurelien@aurel32.net>
|
||||
M: Aleksandar Markovic <amarkovic@wavecomp.com>
|
||||
R: Aleksandar Rikalo <arikalo@wavecomp.com>
|
||||
R: Stefan Markovic <smarkovic@wavecomp.com>
|
||||
S: Maintained
|
||||
F: target/mips/
|
||||
F: default-configs/*mips*
|
||||
@@ -365,7 +364,6 @@ F: target/arm/kvm.c
|
||||
MIPS
|
||||
M: James Hogan <jhogan@kernel.org>
|
||||
R: Aleksandar Rikalo <arikalo@wavecomp.com>
|
||||
R: Stefan Markovic <smarkovic@wavecomp.com>
|
||||
S: Maintained
|
||||
F: target/mips/kvm.c
|
||||
|
||||
@@ -890,7 +888,6 @@ MIPS Machines
|
||||
Jazz
|
||||
M: Hervé Poussineau <hpoussin@reactos.org>
|
||||
R: Aleksandar Rikalo <arikalo@wavecomp.com>
|
||||
R: Stefan Markovic <smarkovic@wavecomp.com>
|
||||
S: Maintained
|
||||
F: hw/mips/mips_jazz.c
|
||||
F: hw/display/jazz_led.c
|
||||
@@ -899,14 +896,12 @@ F: hw/dma/rc4030.c
|
||||
Malta
|
||||
M: Aurelien Jarno <aurelien@aurel32.net>
|
||||
R: Aleksandar Rikalo <arikalo@wavecomp.com>
|
||||
R: Stefan Markovic <smarkovic@wavecomp.com>
|
||||
S: Maintained
|
||||
F: hw/mips/mips_malta.c
|
||||
|
||||
Mipssim
|
||||
M: Aleksandar Markovic <amarkovic@wavecomp.com>
|
||||
R: Aleksandar Rikalo <arikalo@wavecomp.com>
|
||||
R: Stefan Markovic <smarkovic@wavecomp.com>
|
||||
S: Odd Fixes
|
||||
F: hw/mips/mips_mipssim.c
|
||||
F: hw/net/mipsnet.c
|
||||
@@ -914,14 +909,12 @@ F: hw/net/mipsnet.c
|
||||
R4000
|
||||
M: Aurelien Jarno <aurelien@aurel32.net>
|
||||
R: Aleksandar Rikalo <arikalo@wavecomp.com>
|
||||
R: Stefan Markovic <smarkovic@wavecomp.com>
|
||||
S: Maintained
|
||||
F: hw/mips/mips_r4k.c
|
||||
|
||||
Fulong 2E
|
||||
M: Aleksandar Markovic <amarkovic@wavecomp.com>
|
||||
R: Aleksandar Rikalo <arikalo@wavecomp.com>
|
||||
R: Stefan Markovic <smarkovic@wavecomp.com>
|
||||
S: Odd Fixes
|
||||
F: hw/mips/mips_fulong2e.c
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||||
F: hw/isa/vt82c686.c
|
||||
@@ -931,7 +924,6 @@ F: include/hw/isa/vt82c686.h
|
||||
Boston
|
||||
M: Paul Burton <pburton@wavecomp.com>
|
||||
R: Aleksandar Rikalo <arikalo@wavecomp.com>
|
||||
R: Stefan Markovic <smarkovic@wavecomp.com>
|
||||
S: Maintained
|
||||
F: hw/core/loader-fit.c
|
||||
F: hw/mips/boston.c
|
||||
@@ -2203,7 +2195,6 @@ F: disas/i386.c
|
||||
MIPS target
|
||||
M: Aurelien Jarno <aurelien@aurel32.net>
|
||||
R: Aleksandar Rikalo <arikalo@wavecomp.com>
|
||||
R: Stefan Markovic <smarkovic@wavecomp.com>
|
||||
S: Maintained
|
||||
F: tcg/mips/
|
||||
F: disas/mips.c
|
||||
|
||||
+75
-44
@@ -1836,7 +1836,8 @@ std::string NMD::ABS_S(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ABSQ_S.PH rt, rs - Find Absolute Value of Two Fractional Halfwords
|
||||
* [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords
|
||||
* with 16-bit saturation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -1857,7 +1858,8 @@ std::string NMD::ABSQ_S_PH(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ABSQ_S.QB rt, rs - Find Absolute Value of Four Fractional Byte Values
|
||||
* [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values
|
||||
* with 8-bit saturation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -1878,7 +1880,8 @@ std::string NMD::ABSQ_S_QB(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit
|
||||
* saturation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2233,7 +2236,7 @@ std::string NMD::ADDIUPC_48_(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQ.PH rd, rt, rs - Add Fractional Halfword Vectors
|
||||
* [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2257,7 +2260,8 @@ std::string NMD::ADDQ_PH(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQ_S.PH rd, rt, rs - Add Fractional Halfword Vectors
|
||||
* [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit
|
||||
* saturation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2281,7 +2285,7 @@ std::string NMD::ADDQ_S_PH(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQ_S.W rd, rt, rs - Add Fractional Words
|
||||
* [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2305,8 +2309,8 @@ std::string NMD::ADDQ_S_W(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
|
||||
* to Halve Results
|
||||
* [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift
|
||||
* right to halve results
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2330,8 +2334,8 @@ std::string NMD::ADDQH_PH(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
|
||||
* to Halve Results
|
||||
* [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift
|
||||
* right to halve results with rounding
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2355,7 +2359,8 @@ std::string NMD::ADDQH_R_PH(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve
|
||||
* results with rounding
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2379,7 +2384,8 @@ std::string NMD::ADDQH_R_W(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve
|
||||
* results
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2403,7 +2409,7 @@ std::string NMD::ADDQH_W(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDSC rd, rt, rs - Add Signed Word and Set Carry Bit
|
||||
* [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2496,7 +2502,7 @@ std::string NMD::ADDU_4X4_(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDU.PH rd, rt, rs - Unsigned Add Integer Halfwords
|
||||
* [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -2544,7 +2550,8 @@ std::string NMD::ADDU_QB(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDU_S.PH rd, rt, rs - Unsigned Add Integer Halfwords
|
||||
* [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit
|
||||
* saturation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -7848,7 +7855,7 @@ std::string NMD::INS(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* [DSP] INSV - Insert bit field variable
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -9698,7 +9705,8 @@ std::string NMD::LWXS_32_(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* [DSP] MADD ac, rs, rt - Multiply two words and add to the specified
|
||||
* accumulator
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -9770,7 +9778,8 @@ std::string NMD::MADDF_S(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the
|
||||
* specified accumulator
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -9794,7 +9803,8 @@ std::string NMD::MADDU_DSP_(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector
|
||||
* fractional halfword elements with accumulation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -9818,7 +9828,8 @@ std::string NMD::MAQ_S_W_PHL(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector
|
||||
* fractional halfword elements with accumulation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -9842,7 +9853,8 @@ std::string NMD::MAQ_S_W_PHR(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector
|
||||
* fractional halfword elements with saturating accumulation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -9866,7 +9878,8 @@ std::string NMD::MAQ_SA_W_PHL(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector
|
||||
* fractional halfword elements with saturating accumulation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11722,7 +11735,8 @@ std::string NMD::ORI(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one
|
||||
* source register and left halfword from another source register
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11764,7 +11778,8 @@ std::string NMD::PAUSE(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition
|
||||
* code bits
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11788,7 +11803,8 @@ std::string NMD::PICK_PH(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition
|
||||
* code bits
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11812,7 +11828,8 @@ std::string NMD::PICK_QB(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element
|
||||
* of a paired halfword
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11834,7 +11851,8 @@ std::string NMD::PRECEQ_W_PHL(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element
|
||||
* of a paired halfword
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11856,7 +11874,8 @@ std::string NMD::PRECEQ_W_PHR(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two
|
||||
* left-alternate elements of a quad byte vector
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11878,7 +11897,8 @@ std::string NMD::PRECEQU_PH_QBLA(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most
|
||||
* elements of a quad byte vector
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11900,7 +11920,8 @@ std::string NMD::PRECEQU_PH_QBL(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two
|
||||
* right-alternate elements of a quad byte vector
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11922,7 +11943,8 @@ std::string NMD::PRECEQU_PH_QBRA(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most
|
||||
* elements of a quad byte vector
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11944,7 +11966,9 @@ std::string NMD::PRECEQU_PH_QBR(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two
|
||||
* left-alternate elements of a quad byte vector to four unsigned
|
||||
* halfwords
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11966,7 +11990,8 @@ std::string NMD::PRECEU_PH_QBLA(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most
|
||||
* elements of a quad byte vector to form unsigned halfwords
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -11988,7 +12013,9 @@ std::string NMD::PRECEU_PH_QBL(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two
|
||||
* right-alternate elements of a quad byte vector to form four
|
||||
* unsigned halfwords
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -12010,7 +12037,8 @@ std::string NMD::PRECEU_PH_QBRA(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
|
||||
* [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most
|
||||
* elements of a quad byte vector to form unsigned halfwords
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -15202,7 +15230,7 @@ std::string NMD::SUBU_32_(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* SUBU.PH rd, rs, rt - Subtract Unsigned Integer Halfwords
|
||||
* [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -15226,7 +15254,7 @@ std::string NMD::SUBU_PH(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* SUBU.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector
|
||||
* [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -15250,7 +15278,8 @@ std::string NMD::SUBU_QB(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* SUBU_S.PH rd, rs, rt - Subtract Unsigned Integer Halfwords (saturating)
|
||||
* [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with
|
||||
* 8-bit saturation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -15274,7 +15303,8 @@ std::string NMD::SUBU_S_PH(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* SUBU_S.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector (saturating)
|
||||
* [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with
|
||||
* 8-bit saturation
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -15298,8 +15328,8 @@ std::string NMD::SUBU_S_QB(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* SUBUH.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
|
||||
* Results
|
||||
* [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift
|
||||
* to halve results
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -15323,8 +15353,8 @@ std::string NMD::SUBUH_QB(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* SUBUH_R.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
|
||||
* Results (rounding)
|
||||
* [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift
|
||||
* to halve results with rounding
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
@@ -16412,7 +16442,8 @@ std::string NMD::WAIT(uint64 instruction)
|
||||
|
||||
|
||||
/*
|
||||
* WRDSP rt, mask - Write Fields to DSPControl Register from a GPR
|
||||
* [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl
|
||||
* register
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
|
||||
+161
-2
@@ -5,8 +5,9 @@ QEMU / KVM CPU model configuration
|
||||
@c man begin DESCRIPTION
|
||||
|
||||
@menu
|
||||
* recommendations_cpu_models_x86:: Recommendations for KVM CPU model configuration on x86 hosts
|
||||
* cpu_model_syntax_apps:: Syntax for configuring CPU models
|
||||
* recommendations_cpu_models_x86:: Recommendations for KVM CPU model configuration on x86 hosts
|
||||
* recommendations_cpu_models_MIPS:: Supported CPU model configurations on MIPS hosts
|
||||
* cpu_model_syntax_apps:: Syntax for configuring CPU models
|
||||
@end menu
|
||||
|
||||
QEMU / KVM virtualization supports two ways to configure CPU models
|
||||
@@ -368,6 +369,164 @@ hardware assisted virtualization, that should thus not be required for
|
||||
running virtual machines.
|
||||
@end table
|
||||
|
||||
@node recommendations_cpu_models_MIPS
|
||||
@subsection Supported CPU model configurations on MIPS hosts
|
||||
|
||||
QEMU supports variety of MIPS CPU models:
|
||||
|
||||
@menu
|
||||
* cpu_models_MIPS32:: Supported CPU models for MIPS32 hosts
|
||||
* cpu_models_MIPS64:: Supported CPU models for MIPS64 hosts
|
||||
* cpu_models_nanoMIPS:: Supported CPU models for nanoMIPS hosts
|
||||
* preferred_cpu_models_MIPS:: Preferred CPU models for MIPS hosts
|
||||
@end menu
|
||||
|
||||
@node cpu_models_MIPS32
|
||||
@subsubsection Supported CPU models for MIPS32 hosts
|
||||
|
||||
The following CPU models are supported for use on MIPS32 hosts. Administrators /
|
||||
applications are recommended to use the CPU model that matches the generation
|
||||
of the host CPUs in use. In a deployment with a mixture of host CPU models
|
||||
between machines, if live migration compatibility is required, use the newest
|
||||
CPU model that is compatible across all desired hosts.
|
||||
|
||||
@table @option
|
||||
@item @code{mips32r6-generic}
|
||||
|
||||
MIPS32 Processor (Release 6, 2015)
|
||||
|
||||
|
||||
@item @code{P5600}
|
||||
|
||||
MIPS32 Processor (P5600, 2014)
|
||||
|
||||
|
||||
@item @code{M14K}
|
||||
@item @code{M14Kc}
|
||||
|
||||
MIPS32 Processor (M14K, 2009)
|
||||
|
||||
|
||||
@item @code{74Kf}
|
||||
|
||||
MIPS32 Processor (74K, 2007)
|
||||
|
||||
|
||||
@item @code{34Kf}
|
||||
|
||||
MIPS32 Processor (34K, 2006)
|
||||
|
||||
|
||||
@item @code{24Kc}
|
||||
@item @code{24KEc}
|
||||
@item @code{24Kf}
|
||||
|
||||
MIPS32 Processor (24K, 2003)
|
||||
|
||||
|
||||
@item @code{4Kc}
|
||||
@item @code{4Km}
|
||||
@item @code{4KEcR1}
|
||||
@item @code{4KEmR1}
|
||||
@item @code{4KEc}
|
||||
@item @code{4KEm}
|
||||
|
||||
MIPS32 Processor (4K, 1999)
|
||||
@end table
|
||||
|
||||
@node cpu_models_MIPS64
|
||||
@subsubsection Supported CPU models for MIPS64 hosts
|
||||
|
||||
The following CPU models are supported for use on MIPS64 hosts. Administrators /
|
||||
applications are recommended to use the CPU model that matches the generation
|
||||
of the host CPUs in use. In a deployment with a mixture of host CPU models
|
||||
between machines, if live migration compatibility is required, use the newest
|
||||
CPU model that is compatible across all desired hosts.
|
||||
|
||||
@table @option
|
||||
@item @code{I6400}
|
||||
|
||||
MIPS64 Processor (Release 6, 2014)
|
||||
|
||||
|
||||
@item @code{Loongson-2F}
|
||||
|
||||
MIPS64 Processor (Longsoon 2, 2008)
|
||||
|
||||
|
||||
@item @code{Loongson-2E}
|
||||
|
||||
MIPS64 Processor (Loongson 2, 2006)
|
||||
|
||||
|
||||
@item @code{mips64dspr2}
|
||||
|
||||
MIPS64 Processor (Release 2, 2006)
|
||||
|
||||
|
||||
@item @code{MIPS64R2-generic}
|
||||
@item @code{5KEc}
|
||||
@item @code{5KEf}
|
||||
|
||||
MIPS64 Processor (Release 2, 2002)
|
||||
|
||||
|
||||
@item @code{20Kc}
|
||||
|
||||
MIPS64 Processor (20K, 2000)
|
||||
|
||||
|
||||
@item @code{5Kc}
|
||||
@item @code{5Kf}
|
||||
|
||||
MIPS64 Processor (5K, 1999)
|
||||
|
||||
|
||||
@item @code{VR5432}
|
||||
|
||||
MIPS64 Processor (VR, 1998)
|
||||
|
||||
|
||||
@item @code{R4000}
|
||||
|
||||
MIPS64 Processor (MIPS III, 1991)
|
||||
@end table
|
||||
|
||||
@node cpu_models_nanoMIPS
|
||||
@subsubsection Supported CPU models for nanoMIPS hosts
|
||||
|
||||
The following CPU models are supported for use on nanoMIPS hosts. Administrators /
|
||||
applications are recommended to use the CPU model that matches the generation
|
||||
of the host CPUs in use. In a deployment with a mixture of host CPU models
|
||||
between machines, if live migration compatibility is required, use the newest
|
||||
CPU model that is compatible across all desired hosts.
|
||||
|
||||
@table @option
|
||||
@item @code{I7200}
|
||||
|
||||
MIPS I7200 (nanoMIPS, 2018)
|
||||
|
||||
@end table
|
||||
|
||||
@node preferred_cpu_models_MIPS
|
||||
@subsubsection Preferred CPU models for MIPS hosts
|
||||
|
||||
The following CPU models are preferred for use on different MIPS hosts:
|
||||
|
||||
@table @option
|
||||
@item @code{MIPS III}
|
||||
R4000
|
||||
|
||||
@item @code{MIPS32R2}
|
||||
34Kf
|
||||
|
||||
@item @code{MIPS64R6}
|
||||
I6400
|
||||
|
||||
@item @code{nanoMIPS}
|
||||
I7200
|
||||
@end table
|
||||
|
||||
@node cpu_model_syntax_apps
|
||||
@subsection Syntax for configuring CPU models
|
||||
|
||||
|
||||
@@ -1995,6 +1995,10 @@ Set the emulated machine type. The default is sun4u.
|
||||
@section MIPS System emulator
|
||||
@cindex system emulation (MIPS)
|
||||
|
||||
@menu
|
||||
* nanoMIPS System emulator ::
|
||||
@end menu
|
||||
|
||||
Four executables cover simulation of 32 and 64-bit MIPS systems in
|
||||
both endian options, @file{qemu-system-mips}, @file{qemu-system-mipsel}
|
||||
@file{qemu-system-mips64} and @file{qemu-system-mips64el}.
|
||||
@@ -2086,6 +2090,31 @@ SCSI controller
|
||||
G364 framebuffer
|
||||
@end itemize
|
||||
|
||||
@node nanoMIPS System emulator
|
||||
@subsection nanoMIPS System emulator
|
||||
@cindex system emulation (nanoMIPS)
|
||||
|
||||
Executable @file{qemu-system-mipsel} also covers simulation of
|
||||
32-bit nanoMIPS system in little endian mode:
|
||||
|
||||
@itemize @minus
|
||||
@item
|
||||
nanoMIPS I7200 CPU
|
||||
@end itemize
|
||||
|
||||
Example of @file{qemu-system-mipsel} usage for nanoMIPS is shown below:
|
||||
|
||||
Download @code{<disk_image_file>} from @url{https://mipsdistros.mips.com/LinuxDistro/nanomips/buildroot/index.html}.
|
||||
|
||||
Download @code{<kernel_image_file>} from @url{https://mipsdistros.mips.com/LinuxDistro/nanomips/kernels/v4.15.18-432-gb2eb9a8b07a1-20180627102142/index.html}.
|
||||
|
||||
Start system emulation of Malta board with nanoMIPS I7200 CPU:
|
||||
@example
|
||||
qemu-system-mipsel -cpu I7200 -kernel @code{<kernel_image_file>} \
|
||||
-M malta -serial stdio -m @code{<memory_size>} -hda @code{<disk_image_file>} \
|
||||
-append "mem=256m@@0x0 rw console=ttyS0 vga=cirrus vesa=0x111 root=/dev/sda"
|
||||
@end example
|
||||
|
||||
|
||||
@node ARM System emulator
|
||||
@section ARM System emulator
|
||||
|
||||
+1
-1
@@ -1173,7 +1173,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
|
||||
#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
|
||||
|
||||
bool cpu_supports_cps_smp(const char *cpu_type);
|
||||
bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
|
||||
bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
|
||||
void cpu_set_exception_base(int vp_index, target_ulong address);
|
||||
|
||||
/* mips_int.c */
|
||||
|
||||
+32
-29
@@ -3714,7 +3714,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
|
||||
}
|
||||
|
||||
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
|
||||
uint32_t reg1, uint32_t reg2)
|
||||
uint32_t reg1, uint32_t reg2, bool eva)
|
||||
{
|
||||
TCGv taddr = tcg_temp_local_new();
|
||||
TCGv lladdr = tcg_temp_local_new();
|
||||
@@ -3742,7 +3742,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
|
||||
|
||||
tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
|
||||
tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
|
||||
ctx->mem_idx, MO_64);
|
||||
eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);
|
||||
if (reg1 != 0) {
|
||||
tcg_gen_movi_tl(cpu_gpr[reg1], 1);
|
||||
}
|
||||
@@ -18460,10 +18460,9 @@ enum {
|
||||
|
||||
/* extraction utilities */
|
||||
|
||||
#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
|
||||
#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
|
||||
#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
|
||||
#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
|
||||
#define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7)
|
||||
#define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7)
|
||||
#define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7)
|
||||
#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
|
||||
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
|
||||
|
||||
@@ -18502,16 +18501,6 @@ static inline int decode_gpr_gpr4_zero(int r)
|
||||
}
|
||||
|
||||
|
||||
/* extraction utilities */
|
||||
|
||||
#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
|
||||
#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
|
||||
#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
|
||||
#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
|
||||
#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
|
||||
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
|
||||
|
||||
|
||||
static void gen_adjust_sp(DisasContext *ctx, int u)
|
||||
{
|
||||
gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u);
|
||||
@@ -18570,8 +18559,8 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
|
||||
|
||||
static void gen_pool16c_nanomips_insn(DisasContext *ctx)
|
||||
{
|
||||
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
|
||||
int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
|
||||
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
|
||||
int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
|
||||
|
||||
switch (extract32(ctx->opcode, 2, 2)) {
|
||||
case NM_NOT16:
|
||||
@@ -19769,6 +19758,10 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* branch completion */
|
||||
clear_branch_hflags(ctx);
|
||||
ctx->base.is_jmp = DISAS_NORETURN;
|
||||
|
||||
if (bcond_compute == 0) {
|
||||
/* Uncoditional compact branch */
|
||||
gen_goto_tb(ctx, 0, ctx->btarget);
|
||||
@@ -19809,6 +19802,10 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
|
||||
tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);
|
||||
gen_op_addr_add(ctx, btarget, t1, t0);
|
||||
|
||||
/* branch completion */
|
||||
clear_branch_hflags(ctx);
|
||||
ctx->base.is_jmp = DISAS_NORETURN;
|
||||
|
||||
/* unconditional branch to register */
|
||||
tcg_gen_mov_tl(cpu_PC, btarget);
|
||||
tcg_gen_lookup_and_goto_ptr();
|
||||
@@ -19947,6 +19944,10 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* branch completion */
|
||||
clear_branch_hflags(ctx);
|
||||
ctx->base.is_jmp = DISAS_NORETURN;
|
||||
|
||||
/* Generating branch here as compact branches don't have delay slot */
|
||||
gen_goto_tb(ctx, 1, ctx->btarget);
|
||||
gen_set_label(fs);
|
||||
@@ -21561,7 +21562,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||
break;
|
||||
case NM_SCWP:
|
||||
check_xnp(ctx);
|
||||
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
|
||||
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
|
||||
false);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@@ -21665,7 +21667,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||
check_xnp(ctx);
|
||||
check_eva(ctx);
|
||||
check_cp0_enabled(ctx);
|
||||
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
|
||||
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
|
||||
true);
|
||||
break;
|
||||
default:
|
||||
generate_exception_end(ctx, EXCP_RI);
|
||||
@@ -21872,9 +21875,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||
{
|
||||
uint32_t op;
|
||||
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
|
||||
int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
|
||||
int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
|
||||
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
|
||||
int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
|
||||
int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
|
||||
int offset;
|
||||
int imm;
|
||||
|
||||
@@ -22037,7 +22040,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||
break;
|
||||
case NM_SB16:
|
||||
rt = decode_gpr_gpr3_src_store(
|
||||
NANOMIPS_EXTRACT_RD(ctx->opcode));
|
||||
NANOMIPS_EXTRACT_RT3(ctx->opcode));
|
||||
gen_st(ctx, OPC_SB, rt, rs, offset);
|
||||
break;
|
||||
case NM_LBU16:
|
||||
@@ -22056,7 +22059,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||
break;
|
||||
case NM_SH16:
|
||||
rt = decode_gpr_gpr3_src_store(
|
||||
NANOMIPS_EXTRACT_RD(ctx->opcode));
|
||||
NANOMIPS_EXTRACT_RT3(ctx->opcode));
|
||||
gen_st(ctx, OPC_SH, rt, rs, offset);
|
||||
break;
|
||||
case NM_LHU16:
|
||||
@@ -22111,14 +22114,14 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||
break;
|
||||
case NM_SW16:
|
||||
rt = decode_gpr_gpr3_src_store(
|
||||
NANOMIPS_EXTRACT_RD(ctx->opcode));
|
||||
rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
|
||||
NANOMIPS_EXTRACT_RT3(ctx->opcode));
|
||||
rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
|
||||
offset = extract32(ctx->opcode, 0, 4) << 2;
|
||||
gen_st(ctx, OPC_SW, rt, rs, offset);
|
||||
break;
|
||||
case NM_SWGP16:
|
||||
rt = decode_gpr_gpr3_src_store(
|
||||
NANOMIPS_EXTRACT_RD(ctx->opcode));
|
||||
NANOMIPS_EXTRACT_RT3(ctx->opcode));
|
||||
offset = extract32(ctx->opcode, 0, 7) << 2;
|
||||
gen_st(ctx, OPC_SW, rt, 28, offset);
|
||||
break;
|
||||
@@ -29894,7 +29897,7 @@ bool cpu_supports_cps_smp(const char *cpu_type)
|
||||
return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
|
||||
}
|
||||
|
||||
bool cpu_supports_isa(const char *cpu_type, unsigned int isa)
|
||||
bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
|
||||
{
|
||||
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
|
||||
return (mcc->cpu_def->insn_flags & isa) != 0;
|
||||
|
||||
@@ -721,6 +721,46 @@ const mips_def_t mips_defs[] =
|
||||
.insn_flags = CPU_MIPS64R6 | ASE_MSA,
|
||||
.mmu_type = MMU_TYPE_R4000,
|
||||
},
|
||||
{
|
||||
.name = "I6500",
|
||||
.CP0_PRid = 0x1B000,
|
||||
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
|
||||
(MMU_TYPE_R4000 << CP0C0_MT),
|
||||
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
|
||||
(2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
|
||||
(2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
|
||||
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
||||
.CP0_Config2 = MIPS_CONFIG2,
|
||||
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
|
||||
(1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
|
||||
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
|
||||
(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
|
||||
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
|
||||
(1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
|
||||
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
|
||||
(1 << CP0C5_LLB) | (1 << CP0C5_MRP),
|
||||
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
|
||||
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
|
||||
.CP0_LLAddr_rw_bitmask = 0,
|
||||
.CP0_LLAddr_shift = 0,
|
||||
.SYNCI_Step = 64,
|
||||
.CCRes = 2,
|
||||
.CP0_Status_rw_bitmask = 0x30D8FFFF,
|
||||
.CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
|
||||
(1U << CP0PG_RIE),
|
||||
.CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
|
||||
.CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
|
||||
.CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
|
||||
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
||||
(1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
|
||||
.CP1_fcr31_rw_bitmask = 0x0103FFFF,
|
||||
.MSAIR = 0x03 << MSAIR_ProcID,
|
||||
.SEGBITS = 48,
|
||||
.PABITS = 48,
|
||||
.insn_flags = CPU_MIPS64R6 | ASE_MSA,
|
||||
.mmu_type = MMU_TYPE_R4000,
|
||||
},
|
||||
{
|
||||
.name = "Loongson-2E",
|
||||
.CP0_PRid = 0x6302,
|
||||
|
||||
@@ -1,136 +0,0 @@
|
||||
-include ../../config-host.mak
|
||||
|
||||
CROSS=mips64el-unknown-linux-gnu-
|
||||
|
||||
SIM=qemu-mipsel
|
||||
SIM_FLAGS=-cpu 74Kf
|
||||
|
||||
CC = $(CROSS)gcc
|
||||
CFLAGS = -mabi=32 -march=mips32r2 -mgp32 -mdsp -static
|
||||
|
||||
TESTCASES = absq_s_ph.tst
|
||||
TESTCASES += absq_s_w.tst
|
||||
TESTCASES += addq_ph.tst
|
||||
TESTCASES += addq_s_ph.tst
|
||||
TESTCASES += addq_s_w.tst
|
||||
TESTCASES += addsc.tst
|
||||
TESTCASES += addu_qb.tst
|
||||
TESTCASES += addu_s_qb.tst
|
||||
TESTCASES += addwc.tst
|
||||
TESTCASES += bitrev.tst
|
||||
TESTCASES += bposge32.tst
|
||||
TESTCASES += cmp_eq_ph.tst
|
||||
TESTCASES += cmpgu_eq_qb.tst
|
||||
TESTCASES += cmpgu_le_qb.tst
|
||||
TESTCASES += cmpgu_lt_qb.tst
|
||||
TESTCASES += cmp_le_ph.tst
|
||||
TESTCASES += cmp_lt_ph.tst
|
||||
TESTCASES += cmpu_eq_qb.tst
|
||||
TESTCASES += cmpu_le_qb.tst
|
||||
TESTCASES += cmpu_lt_qb.tst
|
||||
TESTCASES += dpaq_sa_l_w.tst
|
||||
TESTCASES += dpaq_s_w_ph.tst
|
||||
TESTCASES += dpau_h_qbl.tst
|
||||
TESTCASES += dpau_h_qbr.tst
|
||||
TESTCASES += dpsq_sa_l_w.tst
|
||||
TESTCASES += dpsq_s_w_ph.tst
|
||||
TESTCASES += dpsu_h_qbl.tst
|
||||
TESTCASES += dpsu_h_qbr.tst
|
||||
TESTCASES += extp.tst
|
||||
TESTCASES += extpdp.tst
|
||||
TESTCASES += extpdpv.tst
|
||||
TESTCASES += extpv.tst
|
||||
TESTCASES += extr_rs_w.tst
|
||||
TESTCASES += extr_r_w.tst
|
||||
TESTCASES += extr_s_h.tst
|
||||
TESTCASES += extrv_rs_w.tst
|
||||
TESTCASES += extrv_r_w.tst
|
||||
TESTCASES += extrv_s_h.tst
|
||||
TESTCASES += extrv_w.tst
|
||||
TESTCASES += extr_w.tst
|
||||
TESTCASES += insv.tst
|
||||
TESTCASES += lbux.tst
|
||||
TESTCASES += lhx.tst
|
||||
TESTCASES += lwx.tst
|
||||
TESTCASES += madd.tst
|
||||
TESTCASES += maddu.tst
|
||||
TESTCASES += maq_sa_w_phl.tst
|
||||
TESTCASES += maq_sa_w_phr.tst
|
||||
TESTCASES += maq_s_w_phl.tst
|
||||
TESTCASES += maq_s_w_phr.tst
|
||||
TESTCASES += mfhi.tst
|
||||
TESTCASES += mflo.tst
|
||||
TESTCASES += modsub.tst
|
||||
TESTCASES += msub.tst
|
||||
TESTCASES += msubu.tst
|
||||
TESTCASES += mthi.tst
|
||||
TESTCASES += mthlip.tst
|
||||
TESTCASES += mtlo.tst
|
||||
TESTCASES += muleq_s_w_phl.tst
|
||||
TESTCASES += muleq_s_w_phr.tst
|
||||
TESTCASES += muleu_s_ph_qbl.tst
|
||||
TESTCASES += muleu_s_ph_qbr.tst
|
||||
TESTCASES += mulq_rs_ph.tst
|
||||
TESTCASES += mult.tst
|
||||
TESTCASES += multu.tst
|
||||
TESTCASES += packrl_ph.tst
|
||||
TESTCASES += pick_ph.tst
|
||||
TESTCASES += pick_qb.tst
|
||||
TESTCASES += precequ_ph_qbla.tst
|
||||
TESTCASES += precequ_ph_qbl.tst
|
||||
TESTCASES += precequ_ph_qbra.tst
|
||||
TESTCASES += precequ_ph_qbr.tst
|
||||
TESTCASES += preceq_w_phl.tst
|
||||
TESTCASES += preceq_w_phr.tst
|
||||
TESTCASES += preceu_ph_qbla.tst
|
||||
TESTCASES += preceu_ph_qbl.tst
|
||||
TESTCASES += preceu_ph_qbra.tst
|
||||
TESTCASES += preceu_ph_qbr.tst
|
||||
TESTCASES += precrq_ph_w.tst
|
||||
TESTCASES += precrq_qb_ph.tst
|
||||
TESTCASES += precrq_rs_ph_w.tst
|
||||
TESTCASES += precrqu_s_qb_ph.tst
|
||||
TESTCASES += raddu_w_qb.tst
|
||||
TESTCASES += rddsp.tst
|
||||
TESTCASES += repl_ph.tst
|
||||
TESTCASES += repl_qb.tst
|
||||
TESTCASES += replv_ph.tst
|
||||
TESTCASES += replv_qb.tst
|
||||
TESTCASES += shilo.tst
|
||||
TESTCASES += shilov.tst
|
||||
TESTCASES += shll_ph.tst
|
||||
TESTCASES += shll_qb.tst
|
||||
TESTCASES += shll_s_ph.tst
|
||||
TESTCASES += shll_s_w.tst
|
||||
TESTCASES += shllv_ph.tst
|
||||
TESTCASES += shllv_qb.tst
|
||||
TESTCASES += shllv_s_ph.tst
|
||||
TESTCASES += shllv_s_w.tst
|
||||
TESTCASES += shra_ph.tst
|
||||
TESTCASES += shra_r_ph.tst
|
||||
TESTCASES += shra_r_w.tst
|
||||
TESTCASES += shrav_ph.tst
|
||||
TESTCASES += shrav_r_ph.tst
|
||||
TESTCASES += shrav_r_w.tst
|
||||
TESTCASES += shrl_qb.tst
|
||||
TESTCASES += shrlv_qb.tst
|
||||
TESTCASES += subq_ph.tst
|
||||
TESTCASES += subq_s_ph.tst
|
||||
TESTCASES += subq_s_w.tst
|
||||
TESTCASES += subu_qb.tst
|
||||
TESTCASES += subu_s_qb.tst
|
||||
TESTCASES += wrdsp.tst
|
||||
|
||||
all: $(TESTCASES)
|
||||
|
||||
%.tst: %.c
|
||||
$(CC) $(CFLAGS) $< -o $@
|
||||
|
||||
check: $(TESTCASES)
|
||||
@for case in $(TESTCASES); do \
|
||||
echo $(SIM) $(SIM_FLAGS) ./$$case;\
|
||||
$(SIM) $(SIM_FLAGS) ./$$case; \
|
||||
done
|
||||
|
||||
clean:
|
||||
$(RM) -rf $(TESTCASES)
|
||||
@@ -1,71 +0,0 @@
|
||||
-include ../../config-host.mak
|
||||
|
||||
CROSS=mips64el-unknown-linux-gnu-
|
||||
|
||||
SIM=qemu-mipsel
|
||||
SIM_FLAGS=-cpu 74Kf
|
||||
|
||||
CC = $(CROSS)gcc
|
||||
CFLAGS = -mabi=32 -march=mips32r2 -mgp32 -mdspr2 -static
|
||||
|
||||
TESTCASES = absq_s_qb.tst
|
||||
TESTCASES += addqh_ph.tst
|
||||
TESTCASES += addqh_r_ph.tst
|
||||
TESTCASES += addqh_r_w.tst
|
||||
TESTCASES += addqh_w.tst
|
||||
TESTCASES += adduh_qb.tst
|
||||
TESTCASES += adduh_r_qb.tst
|
||||
TESTCASES += addu_ph.tst
|
||||
TESTCASES += addu_s_ph.tst
|
||||
TESTCASES += append.tst
|
||||
TESTCASES += balign.tst
|
||||
TESTCASES += cmpgdu_eq_qb.tst
|
||||
TESTCASES += cmpgdu_le_qb.tst
|
||||
TESTCASES += cmpgdu_lt_qb.tst
|
||||
TESTCASES += dpaqx_sa_w_ph.tst
|
||||
TESTCASES += dpa_w_ph.tst
|
||||
TESTCASES += dpax_w_ph.tst
|
||||
TESTCASES += dpaqx_s_w_ph.tst
|
||||
TESTCASES += dpsqx_sa_w_ph.tst
|
||||
TESTCASES += dpsqx_s_w_ph.tst
|
||||
TESTCASES += dps_w_ph.tst
|
||||
TESTCASES += dpsx_w_ph.tst
|
||||
TESTCASES += mul_ph.tst
|
||||
TESTCASES += mulq_rs_w.tst
|
||||
TESTCASES += mulq_s_ph.tst
|
||||
TESTCASES += mulq_s_w.tst
|
||||
TESTCASES += mulsaq_s_w_ph.tst
|
||||
TESTCASES += mulsa_w_ph.tst
|
||||
TESTCASES += mul_s_ph.tst
|
||||
TESTCASES += precr_qb_ph.tst
|
||||
TESTCASES += precr_sra_ph_w.tst
|
||||
TESTCASES += precr_sra_r_ph_w.tst
|
||||
TESTCASES += prepend.tst
|
||||
TESTCASES += shra_qb.tst
|
||||
TESTCASES += shra_r_qb.tst
|
||||
TESTCASES += shrav_qb.tst
|
||||
TESTCASES += shrav_r_qb.tst
|
||||
TESTCASES += shrl_ph.tst
|
||||
TESTCASES += shrlv_ph.tst
|
||||
TESTCASES += subqh_ph.tst
|
||||
TESTCASES += subqh_r_ph.tst
|
||||
TESTCASES += subqh_r_w.tst
|
||||
TESTCASES += subqh_w.tst
|
||||
TESTCASES += subuh_qb.tst
|
||||
TESTCASES += subuh_r_qb.tst
|
||||
TESTCASES += subu_ph.tst
|
||||
TESTCASES += subu_s_ph.tst
|
||||
|
||||
all: $(TESTCASES)
|
||||
|
||||
%.tst: %.c
|
||||
$(CC) $(CFLAGS) $< -o $@
|
||||
|
||||
check: $(TESTCASES)
|
||||
@for case in $(TESTCASES); do \
|
||||
echo $(SIM) $(SIM_FLAGS) ./$$case;\
|
||||
$(SIM) $(SIM_FLAGS) ./$$case; \
|
||||
done
|
||||
|
||||
clean:
|
||||
$(RM) -rf $(TESTCASES)
|
||||
@@ -1,306 +0,0 @@
|
||||
|
||||
CROSS_COMPILE ?= mips64el-unknown-linux-gnu-
|
||||
|
||||
SIM = qemu-system-mips64el
|
||||
SIMFLAGS = -nographic -cpu mips64dspr2 -kernel
|
||||
|
||||
AS = $(CROSS_COMPILE)as
|
||||
LD = $(CROSS_COMPILE)ld
|
||||
CC = $(CROSS_COMPILE)gcc
|
||||
AR = $(CROSS_COMPILE)ar
|
||||
NM = $(CROSS_COMPILE)nm
|
||||
STRIP = $(CROSS_COMPILE)strip
|
||||
RANLIB = $(CROSS_COMPILE)ranlib
|
||||
OBJCOPY = $(CROSS_COMPILE)objcopy
|
||||
OBJDUMP = $(CROSS_COMPILE)objdump
|
||||
|
||||
VECTORS_OBJ ?= ./head.o ./printf.o
|
||||
|
||||
HEAD_FLAGS ?= -nostdinc -mabi=64 -G 0 -mno-abicalls -fno-pic -pipe \
|
||||
-msoft-float -march=mips64 -Wa,-mips64 -Wa,--trap \
|
||||
-msym32 -DKBUILD_64BIT_SYM32 -I./
|
||||
|
||||
CFLAGS ?= -nostdinc -mabi=64 -G 0 -mno-abicalls -fno-pic -fno-builtin \
|
||||
-pipe -march=mips64r2 -mgp64 -mdsp -static -Wa,--trap -msym32 \
|
||||
-DKBUILD_64BIT_SYM32 -I./
|
||||
|
||||
LDFLAGS = -T./mips_boot.lds -L./
|
||||
FLAGS = -nostdlib -mabi=64 -march=mips64r2 -mgp64 -mdsp
|
||||
|
||||
|
||||
#TESTCASES = absq_s_ob.tst
|
||||
TESTCASES = absq_s_ph.tst
|
||||
TESTCASES += absq_s_pw.tst
|
||||
TESTCASES += absq_s_qh.tst
|
||||
TESTCASES += absq_s_w.tst
|
||||
TESTCASES += addq_ph.tst
|
||||
TESTCASES += addq_pw.tst
|
||||
TESTCASES += addq_qh.tst
|
||||
TESTCASES += addq_s_ph.tst
|
||||
TESTCASES += addq_s_pw.tst
|
||||
TESTCASES += addq_s_qh.tst
|
||||
TESTCASES += addq_s_w.tst
|
||||
TESTCASES += addsc.tst
|
||||
TESTCASES += addu_ob.tst
|
||||
TESTCASES += addu_qb.tst
|
||||
TESTCASES += addu_s_ob.tst
|
||||
TESTCASES += addu_s_qb.tst
|
||||
TESTCASES += addwc.tst
|
||||
TESTCASES += bitrev.tst
|
||||
TESTCASES += bposge32.tst
|
||||
TESTCASES += bposge64.tst
|
||||
TESTCASES += cmp_eq_ph.tst
|
||||
TESTCASES += cmp_eq_pw.tst
|
||||
TESTCASES += cmp_eq_qh.tst
|
||||
TESTCASES += cmpgu_eq_ob.tst
|
||||
TESTCASES += cmpgu_eq_qb.tst
|
||||
TESTCASES += cmpgu_le_ob.tst
|
||||
TESTCASES += cmpgu_le_qb.tst
|
||||
TESTCASES += cmpgu_lt_ob.tst
|
||||
TESTCASES += cmpgu_lt_qb.tst
|
||||
TESTCASES += cmp_le_ph.tst
|
||||
TESTCASES += cmp_le_pw.tst
|
||||
TESTCASES += cmp_le_qh.tst
|
||||
TESTCASES += cmp_lt_ph.tst
|
||||
TESTCASES += cmp_lt_pw.tst
|
||||
TESTCASES += cmp_lt_qh.tst
|
||||
TESTCASES += cmpu_eq_ob.tst
|
||||
TESTCASES += cmpu_eq_qb.tst
|
||||
TESTCASES += cmpu_le_ob.tst
|
||||
TESTCASES += cmpu_le_qb.tst
|
||||
TESTCASES += cmpu_lt_ob.tst
|
||||
TESTCASES += cmpu_lt_qb.tst
|
||||
#TESTCASES += dappend.tst
|
||||
TESTCASES += dextp.tst
|
||||
TESTCASES += dextpdp.tst
|
||||
TESTCASES += dextpdpv.tst
|
||||
TESTCASES += dextpv.tst
|
||||
TESTCASES += dextr_l.tst
|
||||
TESTCASES += dextr_r_l.tst
|
||||
TESTCASES += dextr_rs_l.tst
|
||||
TESTCASES += dextr_rs_w.tst
|
||||
TESTCASES += dextr_r_w.tst
|
||||
TESTCASES += dextr_s_h.tst
|
||||
TESTCASES += dextrv_l.tst
|
||||
TESTCASES += dextrv_r_l.tst
|
||||
TESTCASES += dextrv_rs_l.tst
|
||||
TESTCASES += dextrv_rs_w.tst
|
||||
TESTCASES += dextrv_r_w.tst
|
||||
TESTCASES += dextrv_s_h.tst
|
||||
TESTCASES += dextrv_w.tst
|
||||
TESTCASES += dextr_w.tst
|
||||
TESTCASES += dinsv.tst
|
||||
TESTCASES += dmadd.tst
|
||||
TESTCASES += dmaddu.tst
|
||||
TESTCASES += dmsub.tst
|
||||
TESTCASES += dmsubu.tst
|
||||
TESTCASES += dmthlip.tst
|
||||
TESTCASES += dpaq_sa_l_pw.tst
|
||||
TESTCASES += dpaq_sa_l_w.tst
|
||||
TESTCASES += dpaq_s_w_ph.tst
|
||||
TESTCASES += dpaq_s_w_qh.tst
|
||||
TESTCASES += dpau_h_obl.tst
|
||||
TESTCASES += dpau_h_obr.tst
|
||||
TESTCASES += dpau_h_qbl.tst
|
||||
TESTCASES += dpau_h_qbr.tst
|
||||
TESTCASES += dpsq_sa_l_pw.tst
|
||||
TESTCASES += dpsq_sa_l_w.tst
|
||||
TESTCASES += dpsq_s_w_ph.tst
|
||||
TESTCASES += dpsq_s_w_qh.tst
|
||||
TESTCASES += dpsu_h_obl.tst
|
||||
TESTCASES += dpsu_h_obr.tst
|
||||
TESTCASES += dpsu_h_qbl.tst
|
||||
TESTCASES += dpsu_h_qbr.tst
|
||||
TESTCASES += dshilo.tst
|
||||
TESTCASES += dshilov.tst
|
||||
TESTCASES += extp.tst
|
||||
TESTCASES += extpdp.tst
|
||||
TESTCASES += extpdpv.tst
|
||||
TESTCASES += extpv.tst
|
||||
TESTCASES += extr_rs_w.tst
|
||||
TESTCASES += extr_r_w.tst
|
||||
TESTCASES += extr_s_h.tst
|
||||
TESTCASES += extrv_rs_w.tst
|
||||
TESTCASES += extrv_r_w.tst
|
||||
TESTCASES += extrv_s_h.tst
|
||||
TESTCASES += extrv_w.tst
|
||||
TESTCASES += extr_w.tst
|
||||
TESTCASES += insv.tst
|
||||
TESTCASES += lbux.tst
|
||||
TESTCASES += lhx.tst
|
||||
TESTCASES += lwx.tst
|
||||
TESTCASES += ldx.tst
|
||||
TESTCASES += madd.tst
|
||||
TESTCASES += maddu.tst
|
||||
TESTCASES += maq_sa_w_phl.tst
|
||||
TESTCASES += maq_sa_w_phr.tst
|
||||
TESTCASES += maq_sa_w_qhll.tst
|
||||
TESTCASES += maq_sa_w_qhlr.tst
|
||||
TESTCASES += maq_sa_w_qhrl.tst
|
||||
TESTCASES += maq_sa_w_qhrr.tst
|
||||
TESTCASES += maq_s_l_pwl.tst
|
||||
TESTCASES += maq_s_l_pwr.tst
|
||||
TESTCASES += maq_s_w_phl.tst
|
||||
TESTCASES += maq_s_w_phr.tst
|
||||
TESTCASES += maq_s_w_qhll.tst
|
||||
TESTCASES += maq_s_w_qhlr.tst
|
||||
TESTCASES += maq_s_w_qhrl.tst
|
||||
TESTCASES += maq_s_w_qhrr.tst
|
||||
TESTCASES += mfhi.tst
|
||||
TESTCASES += mflo.tst
|
||||
TESTCASES += modsub.tst
|
||||
TESTCASES += msub.tst
|
||||
TESTCASES += msubu.tst
|
||||
TESTCASES += mthi.tst
|
||||
TESTCASES += mthlip.tst
|
||||
TESTCASES += mtlo.tst
|
||||
TESTCASES += muleq_s_pw_qhl.tst
|
||||
TESTCASES += muleq_s_pw_qhr.tst
|
||||
TESTCASES += muleq_s_w_phl.tst
|
||||
TESTCASES += muleq_s_w_phr.tst
|
||||
TESTCASES += muleu_s_ph_qbl.tst
|
||||
TESTCASES += muleu_s_ph_qbr.tst
|
||||
TESTCASES += muleu_s_qh_obl.tst
|
||||
TESTCASES += muleu_s_qh_obr.tst
|
||||
TESTCASES += mulq_rs_ph.tst
|
||||
TESTCASES += mulq_rs_qh.tst
|
||||
TESTCASES += mulsaq_s_l_pw.tst
|
||||
TESTCASES += mulsaq_s_w_qh.tst
|
||||
TESTCASES += mult.tst
|
||||
TESTCASES += multu.tst
|
||||
TESTCASES += packrl_ph.tst
|
||||
TESTCASES += packrl_pw.tst
|
||||
TESTCASES += pick_ob.tst
|
||||
TESTCASES += pick_ph.tst
|
||||
TESTCASES += pick_pw.tst
|
||||
TESTCASES += pick_qb.tst
|
||||
TESTCASES += pick_qh.tst
|
||||
#TESTCASES += preceq_l_pwl.tst
|
||||
#TESTCASES += preceq_l_pwr.tst
|
||||
TESTCASES += preceq_pw_qhla.tst
|
||||
TESTCASES += preceq_pw_qhl.tst
|
||||
TESTCASES += preceq_pw_qhra.tst
|
||||
TESTCASES += preceq_pw_qhr.tst
|
||||
TESTCASES += precequ_ph_qbla.tst
|
||||
TESTCASES += precequ_ph_qbl.tst
|
||||
TESTCASES += precequ_ph_qbra.tst
|
||||
TESTCASES += precequ_ph_qbr.tst
|
||||
#TESTCASES += precequ_qh_obla.tst
|
||||
#TESTCASES += precequ_qh_obl.tst
|
||||
#TESTCASES += precequ_qh_obra.tst
|
||||
#TESTCASES += precequ_qh_obr.tst
|
||||
TESTCASES += preceq_w_phl.tst
|
||||
TESTCASES += preceq_w_phr.tst
|
||||
TESTCASES += preceu_ph_qbla.tst
|
||||
TESTCASES += preceu_ph_qbl.tst
|
||||
TESTCASES += preceu_ph_qbra.tst
|
||||
TESTCASES += preceu_ph_qbr.tst
|
||||
TESTCASES += preceu_qh_obla.tst
|
||||
TESTCASES += preceu_qh_obl.tst
|
||||
TESTCASES += preceu_qh_obra.tst
|
||||
TESTCASES += preceu_qh_obr.tst
|
||||
#TESTCASES += precr_ob_qh.tst
|
||||
TESTCASES += precrq_ob_qh.tst
|
||||
TESTCASES += precrq_ph_w.tst
|
||||
TESTCASES += precrq_pw_l.tst
|
||||
TESTCASES += precrq_qb_ph.tst
|
||||
TESTCASES += precrq_qh_pw.tst
|
||||
TESTCASES += precrq_rs_ph_w.tst
|
||||
TESTCASES += precrq_rs_qh_pw.tst
|
||||
TESTCASES += precrqu_s_ob_qh.tst
|
||||
TESTCASES += precrqu_s_qb_ph.tst
|
||||
#TESTCASES += precr_sra_qh_pw.tst
|
||||
#TESTCASES += precr_sra_r_qh_pw.tst
|
||||
#TESTCASES += prependd.tst
|
||||
#TESTCASES += prependw.tst
|
||||
#TESTCASES += raddu_l_ob.tst
|
||||
TESTCASES += raddu_w_qb.tst
|
||||
TESTCASES += rddsp.tst
|
||||
TESTCASES += repl_ob.tst
|
||||
TESTCASES += repl_ph.tst
|
||||
TESTCASES += repl_pw.tst
|
||||
TESTCASES += repl_qb.tst
|
||||
TESTCASES += repl_qh.tst
|
||||
TESTCASES += replv_ob.tst
|
||||
TESTCASES += replv_ph.tst
|
||||
TESTCASES += replv_pw.tst
|
||||
TESTCASES += replv_qb.tst
|
||||
TESTCASES += shilo.tst
|
||||
TESTCASES += shilov.tst
|
||||
TESTCASES += shll_ob.tst
|
||||
TESTCASES += shll_ph.tst
|
||||
TESTCASES += shll_pw.tst
|
||||
TESTCASES += shll_qb.tst
|
||||
TESTCASES += shll_qh.tst
|
||||
TESTCASES += shll_s_ph.tst
|
||||
TESTCASES += shll_s_pw.tst
|
||||
TESTCASES += shll_s_qh.tst
|
||||
TESTCASES += shll_s_w.tst
|
||||
TESTCASES += shllv_ob.tst
|
||||
TESTCASES += shllv_ph.tst
|
||||
TESTCASES += shllv_pw.tst
|
||||
TESTCASES += shllv_qb.tst
|
||||
TESTCASES += shllv_qh.tst
|
||||
TESTCASES += shllv_s_ph.tst
|
||||
TESTCASES += shllv_s_pw.tst
|
||||
TESTCASES += shllv_s_qh.tst
|
||||
TESTCASES += shllv_s_w.tst
|
||||
#TESTCASES += shra_ob.tst
|
||||
TESTCASES += shra_ph.tst
|
||||
TESTCASES += shra_pw.tst
|
||||
TESTCASES += shra_qh.tst
|
||||
#TESTCASES += shra_r_ob.tst
|
||||
TESTCASES += shra_r_ph.tst
|
||||
TESTCASES += shra_r_pw.tst
|
||||
TESTCASES += shra_r_qh.tst
|
||||
TESTCASES += shra_r_w.tst
|
||||
TESTCASES += shrav_ph.tst
|
||||
TESTCASES += shrav_pw.tst
|
||||
TESTCASES += shrav_qh.tst
|
||||
TESTCASES += shrav_r_ph.tst
|
||||
TESTCASES += shrav_r_pw.tst
|
||||
TESTCASES += shrav_r_qh.tst
|
||||
TESTCASES += shrav_r_w.tst
|
||||
TESTCASES += shrl_ob.tst
|
||||
TESTCASES += shrl_qb.tst
|
||||
#TESTCASES += shrl_qh.tst
|
||||
TESTCASES += shrlv_ob.tst
|
||||
TESTCASES += shrlv_qb.tst
|
||||
#TESTCASES += shrlv_qh.tst
|
||||
TESTCASES += subq_ph.tst
|
||||
TESTCASES += subq_pw.tst
|
||||
TESTCASES += subq_qh.tst
|
||||
TESTCASES += subq_s_ph.tst
|
||||
TESTCASES += subq_s_pw.tst
|
||||
TESTCASES += subq_s_qh.tst
|
||||
TESTCASES += subq_s_w.tst
|
||||
TESTCASES += subu_ob.tst
|
||||
TESTCASES += subu_qb.tst
|
||||
TESTCASES += subu_s_ob.tst
|
||||
TESTCASES += subu_s_qb.tst
|
||||
TESTCASES += wrdsp.tst
|
||||
|
||||
all: build
|
||||
|
||||
head.o : head.S
|
||||
$(Q)$(CC) $(HEAD_FLAGS) -D"STACK_TOP=0xffffffff80200000" -c $< -o $@
|
||||
|
||||
%.o : %.S
|
||||
$(CC) $(CFLAGS) -c $< -o $@
|
||||
|
||||
%.o : %.c
|
||||
$(CC) $(CFLAGS) -c $< -o $@
|
||||
|
||||
%.tst: %.o $(VECTORS_OBJ)
|
||||
$(CC) $(VECTORS_OBJ) $(FLAGS) $(LDFLAGS) $< -o $@
|
||||
|
||||
build: $(VECTORS_OBJ) $(MIPSSOC_LIB) $(TESTCASES)
|
||||
|
||||
check: $(VECTORS_OBJ) $(MIPSSOC_LIB) $(TESTCASES)
|
||||
@for case in $(TESTCASES); do \
|
||||
echo $(SIM) $(SIMFLAGS) ./$$case; \
|
||||
$(SIM) $(SIMFLAGS) ./$$case & (sleep 1; killall $(SIM)); \
|
||||
done
|
||||
|
||||
clean:
|
||||
$(Q)rm -f *.o *.tst *.a
|
||||
@@ -1,63 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rt, result, dspcontrol;
|
||||
rt = 0x7F7F7F7F7F7F7F7F;
|
||||
result = 0x7F7F7F7F7F7F7F7F;
|
||||
|
||||
|
||||
__asm
|
||||
(".set mips64\n\t"
|
||||
"absq_s.ob %0 %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
|
||||
if (result != rd) {
|
||||
printf("absq_s.ob test 1 error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
__asm
|
||||
("rddsp %0\n\t"
|
||||
: "=r"(rd)
|
||||
);
|
||||
rd >> 20;
|
||||
rd = rd & 0x1;
|
||||
if (rd != 0) {
|
||||
printf("absq_s.ob test 1 dspcontrol overflow flag error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rt = 0x80FFFFFFFFFFFFFF;
|
||||
result = 0x7F01010101010101;
|
||||
|
||||
__asm
|
||||
("absq_s.ob %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
if (result != rd) {
|
||||
printf("absq_s.ob test 2 error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
__asm
|
||||
("rddsp %0\n\t"
|
||||
: "=r"(rd)
|
||||
);
|
||||
rd = rd >> 20;
|
||||
rd = rd & 0x1;
|
||||
if (rd != 1) {
|
||||
printf("absq_s.ob test 2 dspcontrol overflow flag error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,37 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rt;
|
||||
long long result;
|
||||
|
||||
rt = 0x10017EFD;
|
||||
result = 0x10017EFD;
|
||||
|
||||
__asm
|
||||
("absq_s.ph %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
if (rd != result) {
|
||||
printf("absq_s.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rt = 0x8000A536;
|
||||
result = 0x7FFF5ACA;
|
||||
|
||||
__asm
|
||||
("absq_s.ph %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
if (rd != result) {
|
||||
printf("absq_s.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,66 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rt, result, dspcontrol;
|
||||
rd = 0;
|
||||
rt = 0x7F7F7F7F7F7F7F7F;
|
||||
result = 0x7F7F7F7F7F7F7F7F;
|
||||
|
||||
|
||||
__asm
|
||||
("absq_s.pw %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
|
||||
if (result != rd) {
|
||||
printf("absq_s.pw test 1 error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rd = 0;
|
||||
__asm
|
||||
("rddsp %0\n\t"
|
||||
: "=r"(rd)
|
||||
);
|
||||
rd >> 20;
|
||||
rd = rd & 0x1;
|
||||
if (rd != 0) {
|
||||
printf("absq_s.pw test 1 dspcontrol overflow flag error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rd = 0;
|
||||
rt = 0x80000000FFFFFFFF;
|
||||
result = 0x7FFFFFFF00000001;
|
||||
|
||||
__asm
|
||||
("absq_s.pw %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
if (result != rd) {
|
||||
printf("absq_s.pw test 2 error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rd = 0;
|
||||
__asm
|
||||
("rddsp %0\n\t"
|
||||
: "=r"(rd)
|
||||
);
|
||||
rd = rd >> 20;
|
||||
rd = rd & 0x1;
|
||||
if (rd != 1) {
|
||||
printf("absq_s.pw test 2 dspcontrol overflow flag error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,40 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rt, result, dspcontrol;
|
||||
rd = 0;
|
||||
rt = 0x7F7F7F7F7F7F7F7F;
|
||||
result = 0x7F7F7F7F7F7F7F7F;
|
||||
|
||||
|
||||
__asm
|
||||
("absq_s.qh %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
|
||||
if (result != rd) {
|
||||
printf("absq_s.qh test 1 error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rd = 0;
|
||||
rt = 0x8000FFFFFFFFFFFF;
|
||||
result = 0x7FFF000100000001;
|
||||
|
||||
__asm
|
||||
("absq_s.pw %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
if (result != rd) {
|
||||
printf("absq_s.rw test 2 error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,48 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rt;
|
||||
long long result;
|
||||
|
||||
rt = 0x80000000;
|
||||
result = 0x7FFFFFFF;
|
||||
__asm
|
||||
("absq_s.w %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
if (rd != result) {
|
||||
printf("absq_s_w.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rt = 0x80030000;
|
||||
result = 0x7FFD0000;
|
||||
__asm
|
||||
("absq_s.w %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
if (rd != result) {
|
||||
printf("absq_s_w.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rt = 0x31036080;
|
||||
result = 0x31036080;
|
||||
__asm
|
||||
("absq_s.w %0, %1\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rt)
|
||||
);
|
||||
if (rd != result) {
|
||||
printf("absq_s_w.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,57 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rs, rt;
|
||||
long long dsp;
|
||||
long long result;
|
||||
|
||||
rs = 0xFFFFFFFF;
|
||||
rt = 0x10101010;
|
||||
result = 0x100F100F;
|
||||
__asm
|
||||
("addq.ph %0, %1, %2\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
if (rd != result) {
|
||||
printf("1 addq.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rs = 0x3712847D;
|
||||
rt = 0x0031AF2D;
|
||||
result = 0x374333AA;
|
||||
__asm
|
||||
("addq.ph %0, %1, %2\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
if (rd != result) {
|
||||
printf("2 addq.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rs = 0x7fff847D;
|
||||
rt = 0x0031AF2D;
|
||||
result = 0xffffffff803033AA;
|
||||
__asm
|
||||
("addq.ph %0, %1, %2\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
|
||||
__asm("rddsp %0\n\t"
|
||||
: "=r"(dsp)
|
||||
);
|
||||
|
||||
if (rd != result || (((dsp >> 20) & 0x01) != 1)) {
|
||||
printf("3 addq.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,46 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rs, rt, result, dspreg, dspresult;
|
||||
|
||||
rs = 0x123456787FFFFFFF;
|
||||
rt = 0x1111111100000101;
|
||||
result = 0x2345678980000100;
|
||||
dspresult = 0x1;
|
||||
|
||||
__asm
|
||||
("addq.pw %0, %2, %3\n\t"
|
||||
"rddsp %1\n\t"
|
||||
: "=r"(rd), "=r"(dspreg)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
|
||||
dspreg = ((dspreg >> 20) & 0x01);
|
||||
if ((rd != result) || (dspreg != dspresult)) {
|
||||
printf("addq.pw error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rs = 0x1234567880FFFFFF;
|
||||
rt = 0x1111111180000001;
|
||||
result = 0x2345678901000000;
|
||||
dspresult = 0x1;
|
||||
|
||||
__asm
|
||||
("addq.pw %0, %2, %3\n\t"
|
||||
"rddsp %1\n\t"
|
||||
: "=r"(rd), "=r"(dspreg)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
|
||||
dspreg = ((dspreg >> 20) & 0x01);
|
||||
if ((rd != result) || (dspreg != dspresult)) {
|
||||
printf("addq.pw error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,28 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rs, rt, result, dspreg, dspresult;
|
||||
|
||||
rs = 0x123456787FFF8010;
|
||||
rt = 0x1111111100018000;
|
||||
result = 0x2345678980000010;
|
||||
dspresult = 0x1;
|
||||
|
||||
__asm
|
||||
("addq.qh %0, %2, %3\n\t"
|
||||
"rddsp %1\n\t"
|
||||
: "=r"(rd), "=r"(dspreg)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
|
||||
dspreg = ((dspreg >> 20) & 0x01);
|
||||
|
||||
if ((rd != result) || (dspreg != dspresult)) {
|
||||
printf("addq.qh error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,84 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rs, rt;
|
||||
long long dsp;
|
||||
long long result;
|
||||
|
||||
rs = 0xFFFFFFFF;
|
||||
rt = 0x10101010;
|
||||
result = 0x100F100F;
|
||||
__asm
|
||||
("addq_s.ph %0, %1, %2\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
if (rd != result) {
|
||||
printf("1 addq_s.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rs = 0x3712847D;
|
||||
rt = 0x0031AF2D;
|
||||
result = 0x37438000;
|
||||
__asm
|
||||
("addq_s.ph %0, %1, %2\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
|
||||
__asm
|
||||
("rddsp %0\n\t"
|
||||
: "=r"(dsp)
|
||||
);
|
||||
|
||||
if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) {
|
||||
printf("2 addq_s.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rs = 0x7fff847D;
|
||||
rt = 0x0031AF2D;
|
||||
result = 0x7fff8000;
|
||||
__asm
|
||||
("addq_s.ph %0, %1, %2\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
|
||||
__asm
|
||||
("rddsp %0\n\t"
|
||||
: "=r"(dsp)
|
||||
);
|
||||
|
||||
if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) {
|
||||
printf("3 addq_s.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rs = 0x8030847D;
|
||||
rt = 0x8a00AF2D;
|
||||
result = 0xffffffff80008000;
|
||||
__asm
|
||||
("addq_s.ph %0, %1, %2\n\t"
|
||||
: "=r"(rd)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
|
||||
__asm
|
||||
("rddsp %0\n\t"
|
||||
: "=r"(dsp)
|
||||
);
|
||||
|
||||
if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) {
|
||||
printf("4 addq_s.ph wrong\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,45 +0,0 @@
|
||||
#include "io.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
long long rd, rs, rt, result, dspreg, dspresult;
|
||||
rs = 0x123456787FFFFFFF;
|
||||
rt = 0x1111111100000001;
|
||||
result = 0x234567897FFFFFFF;
|
||||
dspresult = 0x1;
|
||||
|
||||
__asm
|
||||
("addq_s.pw %0, %2, %3\n\t"
|
||||
"rddsp %1\n\t"
|
||||
: "=r"(rd), "=r"(dspreg)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
|
||||
dspreg = ((dspreg >> 20) & 0x01);
|
||||
if ((rd != result) || (dspreg != dspresult)) {
|
||||
printf("addq_s.pw error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
rs = 0x80FFFFFFE00000FF;
|
||||
rt = 0x80000001200000DD;
|
||||
result = 0x80000000000001DC;
|
||||
dspresult = 0x01;
|
||||
|
||||
__asm
|
||||
("addq_s.pw %0, %2, %3\n\t"
|
||||
"rddsp %1\n\t"
|
||||
: "=r"(rd), "=r"(dspreg)
|
||||
: "r"(rs), "r"(rt)
|
||||
);
|
||||
|
||||
dspreg = ((dspreg >> 20) & 0x01);
|
||||
if ((rd != result) || (dspreg != dspresult)) {
|
||||
printf("addq_s.pw error\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user