Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-05-12' into staging

Miscellaneous patches for 2021-05-12

# gpg: Signature made Wed 12 May 2021 17:22:15 BST
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-misc-2021-05-12:
  Drop the deprecated unicore32 target
  Drop the deprecated lm32 target
  block: Drop the sheepdog block driver
  Remove the deprecated moxie target
  monitor/qmp: fix race on CHR_EVENT_CLOSED without OOB

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2021-05-13 20:13:24 +01:00
208 changed files with 78 additions and 22410 deletions
+4 -5
View File
@@ -89,7 +89,7 @@ build-system-alpine:
variables:
IMAGE: alpine
TARGETS: aarch64-softmmu alpha-softmmu cris-softmmu hppa-softmmu
moxie-softmmu microblazeel-softmmu mips64el-softmmu
microblazeel-softmmu mips64el-softmmu
MAKE_CHECK_ARGS: check-build
CONFIGURE_ARGS: --enable-docs --enable-trace-backends=log,simple,syslog
artifacts:
@@ -125,7 +125,7 @@ build-system-ubuntu:
IMAGE: ubuntu2004
CONFIGURE_ARGS: --enable-docs --enable-fdt=system --enable-slirp=system
TARGETS: aarch64-softmmu alpha-softmmu cris-softmmu hppa-softmmu
moxie-softmmu microblazeel-softmmu mips64el-softmmu
microblazeel-softmmu mips64el-softmmu
MAKE_CHECK_ARGS: check-build
artifacts:
expire_in: 2 days
@@ -342,7 +342,6 @@ build-disabled:
--disable-replication
--disable-sdl
--disable-seccomp
--disable-sheepdog
--disable-slirp
--disable-smartcard
--disable-snappy
@@ -625,7 +624,7 @@ build-deprecated:
IMAGE: debian-all-test-cross
CONFIGURE_ARGS: --disable-tools
MAKE_CHECK_ARGS: build-tcg
TARGETS: ppc64abi32-linux-user lm32-softmmu unicore32-softmmu
TARGETS: ppc64abi32-linux-user
artifacts:
expire_in: 2 days
paths:
@@ -684,7 +683,7 @@ build-tci:
variables:
IMAGE: debian-all-test-cross
script:
- TARGETS="aarch64 alpha arm hppa m68k microblaze moxie ppc64 s390x x86_64"
- TARGETS="aarch64 alpha arm hppa m68k microblaze ppc64 s390x x86_64"
- mkdir build
- cd build
- ../configure --enable-tcg-interpreter
-54
View File
@@ -207,19 +207,6 @@ F: disas/hppa.c
F: hw/net/*i82596*
F: include/hw/net/lasi_82596.h
LM32 TCG CPUs
R: Michael Walle <michael@walle.cc>
S: Orphan
F: target/lm32/
F: disas/lm32.c
F: hw/lm32/
F: hw/*/lm32_*
F: hw/*/milkymist-*
F: include/hw/display/milkymist_tmu2.h
F: include/hw/char/lm32_juart.h
F: include/hw/lm32/
F: tests/tcg/lm32/
M68K TCG CPUs
M: Laurent Vivier <laurent@vivier.eu>
S: Maintained
@@ -258,14 +245,6 @@ MIPS TCG CPUs (nanoMIPS ISA)
S: Orphan
F: disas/nanomips.*
Moxie TCG CPUs
M: Anthony Green <green@moxielogic.com>
S: Maintained
F: target/moxie/
F: disas/moxie.c
F: hw/moxie/
F: default-configs/*/moxie-softmmu.mak
NiosII TCG CPUs
M: Chris Wulff <crwulff@gmail.com>
M: Marek Vasut <marex@denx.de>
@@ -338,13 +317,6 @@ F: hw/sparc64/
F: include/hw/sparc/sparc64.h
F: disas/sparc.c
UniCore32 TCG CPUs
M: Guan Xuetao <gxt@mprc.pku.edu.cn>
S: Maintained
F: target/unicore32/
F: hw/unicore32/
F: include/hw/unicore32/
X86 TCG CPUs
M: Paolo Bonzini <pbonzini@redhat.com>
M: Richard Henderson <richard.henderson@linaro.org>
@@ -1088,18 +1060,6 @@ F: default-configs/*/hppa-softmmu.mak
F: hw/hppa/
F: pc-bios/hppa-firmware.img
LM32 Machines
-------------
EVR32 and uclinux BSP
R: Michael Walle <michael@walle.cc>
S: Orphan
F: hw/lm32/lm32_boards.c
milkymist
R: Michael Walle <michael@walle.cc>
S: Orphan
F: hw/lm32/milkymist.c
M68K Machines
-------------
an5206
@@ -1549,14 +1509,6 @@ F: hw/s390x/s390-pci*
F: include/hw/s390x/s390-pci*
L: qemu-s390x@nongnu.org
UniCore32 Machines
------------------
PKUnity-3 SoC initramfs-with-busybox
M: Guan Xuetao <gxt@mprc.pku.edu.cn>
S: Maintained
F: hw/*/puv3*
F: hw/unicore32/
X86 Machines
------------
PC
@@ -3088,12 +3040,6 @@ L: qemu-block@nongnu.org
S: Supported
F: block/rbd.c
Sheepdog
M: Liu Yuan <namei.unix@gmail.com>
L: qemu-block@nongnu.org
S: Odd Fixes
F: block/sheepdog.c
VHDX
M: Jeff Cody <codyprime@gmail.com>
L: qemu-block@nongnu.org
-1
View File
@@ -64,7 +64,6 @@ block_ss.add(when: 'CONFIG_POSIX', if_true: [files('file-posix.c'), coref, iokit
block_ss.add(when: libiscsi, if_true: files('iscsi-opts.c'))
block_ss.add(when: 'CONFIG_LINUX', if_true: files('nvme.c'))
block_ss.add(when: 'CONFIG_REPLICATION', if_true: files('replication.c'))
block_ss.add(when: 'CONFIG_SHEEPDOG', if_true: files('sheepdog.c'))
block_ss.add(when: ['CONFIG_LINUX_AIO', libaio], if_true: files('linux-aio.c'))
block_ss.add(when: ['CONFIG_LINUX_IO_URING', linux_io_uring], if_true: files('io_uring.c'))
-3356
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File diff suppressed because it is too large Load Diff
-14
View File
@@ -207,19 +207,5 @@ file_FindEjectableOpticalMedia(const char *media) "Matching using %s"
file_setup_cdrom(const char *partition) "Using %s as optical disc"
file_hdev_is_sg(int type, int version) "SG device found: type=%d, version=%d"
# sheepdog.c
sheepdog_reconnect_to_sdog(void) "Wait for connection to be established"
sheepdog_aio_read_response(void) "disable cache since the server doesn't support it"
sheepdog_open(uint32_t vid) "0x%" PRIx32 " snapshot inode was open"
sheepdog_close(const char *name) "%s"
sheepdog_create_branch_snapshot(uint32_t vdi) "0x%" PRIx32 " is snapshot"
sheepdog_create_branch_created(uint32_t vdi) "0x%" PRIx32 " is created"
sheepdog_create_branch_new(uint32_t vdi) "0x%" PRIx32 " was newly created"
sheepdog_co_rw_vector_update(uint32_t vdi, uint64_t oid, uint64_t data, long idx) "update ino (%" PRIu32 ") %" PRIu64 " %" PRIu64 " %ld"
sheepdog_co_rw_vector_new(uint64_t oid) "new oid 0x%" PRIx64
sheepdog_snapshot_create_info(const char *sn_name, const char *id, const char *name, int64_t size, int is_snapshot) "sn_info: name %s id_str %s s: name %s vm_state_size %" PRId64 " " "is_snapshot %d"
sheepdog_snapshot_create(const char *sn_name, const char *id) "%s %s"
sheepdog_snapshot_create_inode(const char *name, uint32_t snap, uint32_t vdi) "s->inode: name %s snap_id 0x%" PRIx32 " vdi 0x%" PRIx32
# ssh.c
sftp_error(const char *op, const char *ssh_err, int ssh_err_code, int sftp_err_code) "%s failed: %s (libssh error code: %d, sftp error code: %d)"
Vendored
+3 -14
View File
@@ -447,7 +447,6 @@ vdi=${default_feature:-yes}
vvfat=${default_feature:-yes}
qed=${default_feature:-yes}
parallels=${default_feature:-yes}
sheepdog="no"
libxml2="$default_feature"
debug_mutex="no"
libpmem="$default_feature"
@@ -1478,10 +1477,6 @@ for opt do
;;
--enable-parallels) parallels="yes"
;;
--disable-sheepdog) sheepdog="no"
;;
--enable-sheepdog) sheepdog="yes"
;;
--disable-vhost-user) vhost_user="no"
;;
--enable-vhost-user) vhost_user="yes"
@@ -1668,7 +1663,7 @@ if [ "$ARCH" = "unknown" ]; then
fi
default_target_list=""
deprecated_targets_list=ppc64abi32-linux-user,lm32-softmmu,unicore32-softmmu
deprecated_targets_list=ppc64abi32-linux-user
deprecated_features=""
mak_wilds=""
@@ -1916,7 +1911,6 @@ disabled with --disable-FEATURE, default is enabled if available
vvfat vvfat image format support
qed qed image format support
parallels parallels image format support
sheepdog sheepdog block driver support (deprecated)
crypto-afalg Linux AF_ALG crypto backend driver
capstone capstone disassembler support
debug-mutex mutex debugging support
@@ -3623,7 +3617,7 @@ case "$fdt" in
esac
##########################################
# opengl probe (for sdl2, gtk, milkymist-tmu2)
# opengl probe (for sdl2, gtk)
gbm="no"
if $pkg_config gbm; then
@@ -6108,10 +6102,6 @@ fi
if test "$parallels" = "yes" ; then
echo "CONFIG_PARALLELS=y" >> $config_host_mak
fi
if test "$sheepdog" = "yes" ; then
add_to deprecated_features "sheepdog"
echo "CONFIG_SHEEPDOG=y" >> $config_host_mak
fi
if test "$have_mlockall" = "yes" ; then
echo "HAVE_MLOCKALL=y" >> $config_host_mak
fi
@@ -6286,14 +6276,13 @@ fi
# UNLINK is used to remove symlinks from older development versions
# that might get into the way when doing "git update" without doing
# a "make distclean" in between.
DIRS="tests tests/tcg tests/tcg/lm32 tests/qapi-schema tests/qtest/libqos"
DIRS="tests tests/tcg tests/qapi-schema tests/qtest/libqos"
DIRS="$DIRS tests/qtest tests/qemu-iotests tests/vm tests/fp tests/qgraph"
DIRS="$DIRS docs docs/interop fsdev scsi"
DIRS="$DIRS pc-bios/optionrom pc-bios/s390-ccw"
DIRS="$DIRS roms/seabios"
DIRS="$DIRS contrib/plugins/"
LINKS="Makefile"
LINKS="$LINKS tests/tcg/lm32/Makefile"
LINKS="$LINKS tests/tcg/Makefile.target"
LINKS="$LINKS pc-bios/optionrom/Makefile"
LINKS="$LINKS pc-bios/s390-ccw/Makefile"
-12
View File
@@ -1,12 +0,0 @@
# Default configuration for lm32-softmmu
# Uncomment the following lines to disable these optional devices:
#
#CONFIG_MILKYMIST_TMU2=n # disabling it actually causes compile-time failures
CONFIG_SEMIHOSTING=y
# Boards:
#
CONFIG_LM32_EVR=y
CONFIG_MILKYMIST=y
@@ -1,5 +0,0 @@
# Default configuration for moxie-softmmu
# Boards:
#
CONFIG_MOXIESIM=y
@@ -1,6 +0,0 @@
# Default configuration for unicore32-softmmu
# Boards:
#
CONFIG_PUV3=y
CONFIG_SEMIHOSTING=y
-2
View File
@@ -1,2 +0,0 @@
TARGET_ARCH=lm32
TARGET_WORDS_BIGENDIAN=y
@@ -1,2 +0,0 @@
TARGET_ARCH=moxie
TARGET_WORDS_BIGENDIAN=y
@@ -1 +0,0 @@
TARGET_ARCH=unicore32
-361
View File
@@ -1,361 +0,0 @@
/*
* Simple LatticeMico32 disassembler.
*
* Copyright (c) 2012 Michael Walle <michael@walle.cc>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*
*/
#include "qemu/osdep.h"
#include "disas/dis-asm.h"
typedef enum {
LM32_OP_SRUI = 0, LM32_OP_NORI, LM32_OP_MULI, LM32_OP_SH, LM32_OP_LB,
LM32_OP_SRI, LM32_OP_XORI, LM32_OP_LH, LM32_OP_ANDI, LM32_OP_XNORI,
LM32_OP_LW, LM32_OP_LHU, LM32_OP_SB, LM32_OP_ADDI, LM32_OP_ORI,
LM32_OP_SLI, LM32_OP_LBU, LM32_OP_BE, LM32_OP_BG, LM32_OP_BGE,
LM32_OP_BGEU, LM32_OP_BGU, LM32_OP_SW, LM32_OP_BNE, LM32_OP_ANDHI,
LM32_OP_CMPEI, LM32_OP_CMPGI, LM32_OP_CMPGEI, LM32_OP_CMPGEUI,
LM32_OP_CMPGUI, LM32_OP_ORHI, LM32_OP_CMPNEI, LM32_OP_SRU, LM32_OP_NOR,
LM32_OP_MUL, LM32_OP_DIVU, LM32_OP_RCSR, LM32_OP_SR, LM32_OP_XOR,
LM32_OP_ILL0, LM32_OP_AND, LM32_OP_XNOR, LM32_OP_ILL1, LM32_OP_SCALL,
LM32_OP_SEXTB, LM32_OP_ADD, LM32_OP_OR, LM32_OP_SL, LM32_OP_B,
LM32_OP_MODU, LM32_OP_SUB, LM32_OP_ILL2, LM32_OP_WCSR, LM32_OP_ILL3,
LM32_OP_CALL, LM32_OP_SEXTH, LM32_OP_BI, LM32_OP_CMPE, LM32_OP_CMPG,
LM32_OP_CMPGE, LM32_OP_CMPGEU, LM32_OP_CMPGU, LM32_OP_CALLI, LM32_OP_CMPNE,
} Lm32Opcode;
typedef enum {
FMT_INVALID = 0, FMT_RRI5, FMT_RRI16, FMT_IMM26, FMT_LOAD, FMT_STORE,
FMT_RRR, FMT_R, FMT_RNR, FMT_CRN, FMT_CNR, FMT_BREAK,
} Lm32OpcodeFmt;
typedef enum {
LM32_CSR_IE = 0, LM32_CSR_IM, LM32_CSR_IP, LM32_CSR_ICC, LM32_CSR_DCC,
LM32_CSR_CC, LM32_CSR_CFG, LM32_CSR_EBA, LM32_CSR_DC, LM32_CSR_DEBA,
LM32_CSR_CFG2, LM32_CSR_JTX = 0xe, LM32_CSR_JRX, LM32_CSR_BP0,
LM32_CSR_BP1, LM32_CSR_BP2, LM32_CSR_BP3, LM32_CSR_WP0 = 0x18,
LM32_CSR_WP1, LM32_CSR_WP2, LM32_CSR_WP3,
} Lm32CsrNum;
typedef struct {
int csr;
const char *name;
} Lm32CsrInfo;
static const Lm32CsrInfo lm32_csr_info[] = {
{LM32_CSR_IE, "ie", },
{LM32_CSR_IM, "im", },
{LM32_CSR_IP, "ip", },
{LM32_CSR_ICC, "icc", },
{LM32_CSR_DCC, "dcc", },
{LM32_CSR_CC, "cc", },
{LM32_CSR_CFG, "cfg", },
{LM32_CSR_EBA, "eba", },
{LM32_CSR_DC, "dc", },
{LM32_CSR_DEBA, "deba", },
{LM32_CSR_CFG2, "cfg2", },
{LM32_CSR_JTX, "jtx", },
{LM32_CSR_JRX, "jrx", },
{LM32_CSR_BP0, "bp0", },
{LM32_CSR_BP1, "bp1", },
{LM32_CSR_BP2, "bp2", },
{LM32_CSR_BP3, "bp3", },
{LM32_CSR_WP0, "wp0", },
{LM32_CSR_WP1, "wp1", },
{LM32_CSR_WP2, "wp2", },
{LM32_CSR_WP3, "wp3", },
};
static const Lm32CsrInfo *find_csr_info(int csr)
{
const Lm32CsrInfo *info;
int i;
for (i = 0; i < ARRAY_SIZE(lm32_csr_info); i++) {
info = &lm32_csr_info[i];
if (csr == info->csr) {
return info;
}
}
return NULL;
}
typedef struct {
int reg;
const char *name;
} Lm32RegInfo;
typedef enum {
LM32_REG_R0 = 0, LM32_REG_R1, LM32_REG_R2, LM32_REG_R3, LM32_REG_R4,
LM32_REG_R5, LM32_REG_R6, LM32_REG_R7, LM32_REG_R8, LM32_REG_R9,
LM32_REG_R10, LM32_REG_R11, LM32_REG_R12, LM32_REG_R13, LM32_REG_R14,
LM32_REG_R15, LM32_REG_R16, LM32_REG_R17, LM32_REG_R18, LM32_REG_R19,
LM32_REG_R20, LM32_REG_R21, LM32_REG_R22, LM32_REG_R23, LM32_REG_R24,
LM32_REG_R25, LM32_REG_GP, LM32_REG_FP, LM32_REG_SP, LM32_REG_RA,
LM32_REG_EA, LM32_REG_BA,
} Lm32RegNum;
static const Lm32RegInfo lm32_reg_info[] = {
{LM32_REG_R0, "r0", },
{LM32_REG_R1, "r1", },
{LM32_REG_R2, "r2", },
{LM32_REG_R3, "r3", },
{LM32_REG_R4, "r4", },
{LM32_REG_R5, "r5", },
{LM32_REG_R6, "r6", },
{LM32_REG_R7, "r7", },
{LM32_REG_R8, "r8", },
{LM32_REG_R9, "r9", },
{LM32_REG_R10, "r10", },
{LM32_REG_R11, "r11", },
{LM32_REG_R12, "r12", },
{LM32_REG_R13, "r13", },
{LM32_REG_R14, "r14", },
{LM32_REG_R15, "r15", },
{LM32_REG_R16, "r16", },
{LM32_REG_R17, "r17", },
{LM32_REG_R18, "r18", },
{LM32_REG_R19, "r19", },
{LM32_REG_R20, "r20", },
{LM32_REG_R21, "r21", },
{LM32_REG_R22, "r22", },
{LM32_REG_R23, "r23", },
{LM32_REG_R24, "r24", },
{LM32_REG_R25, "r25", },
{LM32_REG_GP, "gp", },
{LM32_REG_FP, "fp", },
{LM32_REG_SP, "sp", },
{LM32_REG_RA, "ra", },
{LM32_REG_EA, "ea", },
{LM32_REG_BA, "ba", },
};
static const Lm32RegInfo *find_reg_info(int reg)
{
assert(ARRAY_SIZE(lm32_reg_info) == 32);
return &lm32_reg_info[reg & 0x1f];
}
typedef struct {
struct {
uint32_t code;
uint32_t mask;
} op;
const char *name;
const char *args_fmt;
} Lm32OpcodeInfo;
static const Lm32OpcodeInfo lm32_opcode_info[] = {
/* pseudo instructions */
{{0x34000000, 0xffffffff}, "nop", NULL},
{{0xac000002, 0xffffffff}, "break", NULL},
{{0xac000003, 0xffffffff}, "scall", NULL},
{{0xc3e00000, 0xffffffff}, "bret", NULL},
{{0xc3c00000, 0xffffffff}, "eret", NULL},
{{0xc3a00000, 0xffffffff}, "ret", NULL},
{{0xa4000000, 0xfc1f07ff}, "not", "%2, %0"},
{{0xb8000000, 0xfc1f07ff}, "mv", "%2, %0"},
{{0x71e00000, 0xffe00000}, "mvhi", "%1, %u"},
{{0x34000000, 0xffe00000}, "mvi", "%1, %s"},
#define _O(op) {op << 26, 0x3f << 26}
/* regular opcodes */
{_O(LM32_OP_ADD), "add", "%2, %0, %1" },
{_O(LM32_OP_ADDI), "addi", "%1, %0, %s" },
{_O(LM32_OP_AND), "and", "%2, %0, %1" },
{_O(LM32_OP_ANDHI), "andhi", "%1, %0, %u" },
{_O(LM32_OP_ANDI), "andi", "%1, %0, %u" },
{_O(LM32_OP_B), "b", "%0", },
{_O(LM32_OP_BE), "be", "%1, %0, %r" },
{_O(LM32_OP_BG), "bg", "%1, %0, %r" },
{_O(LM32_OP_BGE), "bge", "%1, %0, %r" },
{_O(LM32_OP_BGEU), "bgeu", "%1, %0, %r" },
{_O(LM32_OP_BGU), "bgu", "%1, %0, %r" },
{_O(LM32_OP_BI), "bi", "%R", },
{_O(LM32_OP_BNE), "bne", "%1, %0, %r" },
{_O(LM32_OP_CALL), "call", "%0", },
{_O(LM32_OP_CALLI), "calli", "%R", },
{_O(LM32_OP_CMPE), "cmpe", "%2, %0, %1" },
{_O(LM32_OP_CMPEI), "cmpei", "%1, %0, %s" },
{_O(LM32_OP_CMPG), "cmpg", "%2, %0, %1" },
{_O(LM32_OP_CMPGE), "cmpge", "%2, %0, %1" },
{_O(LM32_OP_CMPGEI), "cmpgei", "%1, %0, %s" },
{_O(LM32_OP_CMPGEU), "cmpgeu", "%2, %0, %1" },
{_O(LM32_OP_CMPGEUI), "cmpgeui", "%1, %0, %s" },
{_O(LM32_OP_CMPGI), "cmpgi", "%1, %0, %s" },
{_O(LM32_OP_CMPGU), "cmpgu", "%2, %0, %1" },
{_O(LM32_OP_CMPGUI), "cmpgui", "%1, %0, %s" },
{_O(LM32_OP_CMPNE), "cmpne", "%2, %0, %1" },
{_O(LM32_OP_CMPNEI), "cmpnei", "%1, %0, %s" },
{_O(LM32_OP_DIVU), "divu", "%2, %0, %1" },
{_O(LM32_OP_LB), "lb", "%1, (%0+%s)" },
{_O(LM32_OP_LBU), "lbu", "%1, (%0+%s)" },
{_O(LM32_OP_LH), "lh", "%1, (%0+%s)" },
{_O(LM32_OP_LHU), "lhu", "%1, (%0+%s)" },
{_O(LM32_OP_LW), "lw", "%1, (%0+%s)" },
{_O(LM32_OP_MODU), "modu", "%2, %0, %1" },
{_O(LM32_OP_MULI), "muli", "%1, %0, %s" },
{_O(LM32_OP_MUL), "mul", "%2, %0, %1" },
{_O(LM32_OP_NORI), "nori", "%1, %0, %u" },
{_O(LM32_OP_NOR), "nor", "%2, %0, %1" },
{_O(LM32_OP_ORHI), "orhi", "%1, %0, %u" },
{_O(LM32_OP_ORI), "ori", "%1, %0, %u" },
{_O(LM32_OP_OR), "or", "%2, %0, %1" },
{_O(LM32_OP_RCSR), "rcsr", "%2, %c", },
{_O(LM32_OP_SB), "sb", "(%0+%s), %1" },
{_O(LM32_OP_SEXTB), "sextb", "%2, %0", },
{_O(LM32_OP_SEXTH), "sexth", "%2, %0", },
{_O(LM32_OP_SH), "sh", "(%0+%s), %1" },
{_O(LM32_OP_SLI), "sli", "%1, %0, %h" },
{_O(LM32_OP_SL), "sl", "%2, %0, %1" },
{_O(LM32_OP_SRI), "sri", "%1, %0, %h" },
{_O(LM32_OP_SR), "sr", "%2, %0, %1" },
{_O(LM32_OP_SRUI), "srui", "%1, %0, %d" },
{_O(LM32_OP_SRU), "sru", "%2, %0, %s" },
{_O(LM32_OP_SUB), "sub", "%2, %0, %s" },
{_O(LM32_OP_SW), "sw", "(%0+%s), %1" },
{_O(LM32_OP_WCSR), "wcsr", "%c, %1", },
{_O(LM32_OP_XNORI), "xnori", "%1, %0, %u" },
{_O(LM32_OP_XNOR), "xnor", "%2, %0, %1" },
{_O(LM32_OP_XORI), "xori", "%1, %0, %u" },
{_O(LM32_OP_XOR), "xor", "%2, %0, %1" },
#undef _O
};
static const Lm32OpcodeInfo *find_opcode_info(uint32_t opcode)
{
const Lm32OpcodeInfo *info;
int i;
for (i = 0; i < ARRAY_SIZE(lm32_opcode_info); i++) {
info = &lm32_opcode_info[i];
if ((opcode & info->op.mask) == info->op.code) {
return info;
}
}
return NULL;
}
int print_insn_lm32(bfd_vma memaddr, struct disassemble_info *info)
{
fprintf_function fprintf_fn = info->fprintf_func;
void *stream = info->stream;
int rc;
uint8_t insn[4];
const Lm32OpcodeInfo *opc_info;
uint32_t op;
const char *args_fmt;
rc = info->read_memory_func(memaddr, insn, 4, info);
if (rc != 0) {
info->memory_error_func(rc, memaddr, info);
return -1;
}
fprintf_fn(stream, "%02x %02x %02x %02x ",
insn[0], insn[1], insn[2], insn[3]);
op = bfd_getb32(insn);
opc_info = find_opcode_info(op);
if (opc_info) {
fprintf_fn(stream, "%-8s ", opc_info->name);
args_fmt = opc_info->args_fmt;
while (args_fmt && *args_fmt) {
if (*args_fmt == '%') {
switch (*(++args_fmt)) {
case '0': {
uint8_t r0;
const char *r0_name;
r0 = (op >> 21) & 0x1f;
r0_name = find_reg_info(r0)->name;
fprintf_fn(stream, "%s", r0_name);
break;
}
case '1': {
uint8_t r1;
const char *r1_name;
r1 = (op >> 16) & 0x1f;
r1_name = find_reg_info(r1)->name;
fprintf_fn(stream, "%s", r1_name);
break;
}
case '2': {
uint8_t r2;
const char *r2_name;
r2 = (op >> 11) & 0x1f;
r2_name = find_reg_info(r2)->name;
fprintf_fn(stream, "%s", r2_name);
break;
}
case 'c': {
uint8_t csr;
const Lm32CsrInfo *info;
csr = (op >> 21) & 0x1f;
info = find_csr_info(csr);
if (info) {
fprintf_fn(stream, "%s", info->name);
} else {
fprintf_fn(stream, "0x%x", csr);
}
break;
}
case 'u': {
uint16_t u16;
u16 = op & 0xffff;
fprintf_fn(stream, "0x%x", u16);
break;
}
case 's': {
int16_t s16;
s16 = (int16_t)(op & 0xffff);
fprintf_fn(stream, "%d", s16);
break;
}
case 'r': {
uint32_t rela;
rela = memaddr + (((int16_t)(op & 0xffff)) << 2);
fprintf_fn(stream, "%x", rela);
break;
}
case 'R': {
uint32_t rela;
int32_t imm26;
imm26 = (int32_t)((op & 0x3ffffff) << 6) >> 4;
rela = memaddr + imm26;
fprintf_fn(stream, "%x", rela);
break;
}
case 'h': {
uint8_t u5;
u5 = (op & 0x1f);
fprintf_fn(stream, "%d", u5);
break;
}
default:
break;
}
} else {
fprintf_fn(stream, "%c", *args_fmt);
}
args_fmt++;
}
} else {
fprintf_fn(stream, ".word 0x%x", op);
}
return 4;
}
-2
View File
@@ -9,11 +9,9 @@ common_ss.add(when: 'CONFIG_CRIS_DIS', if_true: files('cris.c'))
common_ss.add(when: 'CONFIG_HEXAGON_DIS', if_true: files('hexagon.c'))
common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c'))
common_ss.add(when: 'CONFIG_I386_DIS', if_true: files('i386.c'))
common_ss.add(when: 'CONFIG_LM32_DIS', if_true: files('lm32.c'))
common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c'))
common_ss.add(when: 'CONFIG_MICROBLAZE_DIS', if_true: files('microblaze.c'))
common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c'))
common_ss.add(when: 'CONFIG_MOXIE_DIS', if_true: files('moxie.c'))
common_ss.add(when: 'CONFIG_NANOMIPS_DIS', if_true: files('nanomips.cpp'))
common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c'))
common_ss.add(when: 'CONFIG_PPC_DIS', if_true: files('ppc.c'))
-360
View File
@@ -1,360 +0,0 @@
/* Disassemble moxie instructions.
Copyright (c) 2009 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
#include "qemu/osdep.h"
#define STATIC_TABLE
#define DEFINE_TABLE
#include "disas/dis-asm.h"
static void *stream;
/* Form 1 instructions come in different flavors:
Some have no arguments (MOXIE_F1_NARG)
Some only use the A operand (MOXIE_F1_A)
Some use A and B registers (MOXIE_F1_AB)
Some use A and consume a 4 byte immediate value (MOXIE_F1_A4)
Some use just a 4 byte immediate value (MOXIE_F1_4)
Some use just a 4 byte memory address (MOXIE_F1_M)
Some use B and an indirect A (MOXIE_F1_AiB)
Some use A and an indirect B (MOXIE_F1_ABi)
Some consume a 4 byte immediate value and use X (MOXIE_F1_4A)
Some use B and an indirect A plus 4 bytes (MOXIE_F1_AiB4)
Some use A and an indirect B plus 4 bytes (MOXIE_F1_ABi4)
Form 2 instructions also come in different flavors:
Some have no arguments (MOXIE_F2_NARG)
Some use the A register and an 8-bit value (MOXIE_F2_A8V)
Form 3 instructions also come in different flavors:
Some have no arguments (MOXIE_F3_NARG)
Some have a 10-bit PC relative operand (MOXIE_F3_PCREL). */
#define MOXIE_F1_NARG 0x100
#define MOXIE_F1_A 0x101
#define MOXIE_F1_AB 0x102
/* #define MOXIE_F1_ABC 0x103 */
#define MOXIE_F1_A4 0x104
#define MOXIE_F1_4 0x105
#define MOXIE_F1_AiB 0x106
#define MOXIE_F1_ABi 0x107
#define MOXIE_F1_4A 0x108
#define MOXIE_F1_AiB4 0x109
#define MOXIE_F1_ABi4 0x10a
#define MOXIE_F1_M 0x10b
#define MOXIE_F2_NARG 0x200
#define MOXIE_F2_A8V 0x201
#define MOXIE_F3_NARG 0x300
#define MOXIE_F3_PCREL 0x301
typedef struct moxie_opc_info_t {
short opcode;
unsigned itype;
const char * name;
} moxie_opc_info_t;
extern const moxie_opc_info_t moxie_form1_opc_info[64];
extern const moxie_opc_info_t moxie_form2_opc_info[4];
extern const moxie_opc_info_t moxie_form3_opc_info[16];
/* The moxie processor's 16-bit instructions come in two forms:
FORM 1 instructions start with a 0 bit...
0oooooooaaaabbbb
0 F
ooooooo - form 1 opcode number
aaaa - operand A
bbbb - operand B
FORM 2 instructions start with bits "10"...
10ooaaaavvvvvvvv
0 F
oo - form 2 opcode number
aaaa - operand A
vvvvvvvv - 8-bit immediate value
FORM 3 instructions start with a bits "11"...
11oooovvvvvvvvvv
0 F
oooo - form 3 opcode number
vvvvvvvvvv - 10-bit immediate value. */
const moxie_opc_info_t moxie_form1_opc_info[64] =
{
{ 0x00, MOXIE_F1_NARG, "nop" },
{ 0x01, MOXIE_F1_A4, "ldi.l" },
{ 0x02, MOXIE_F1_AB, "mov" },
{ 0x03, MOXIE_F1_M, "jsra" },
{ 0x04, MOXIE_F1_NARG, "ret" },
{ 0x05, MOXIE_F1_AB, "add.l" },
{ 0x06, MOXIE_F1_AB, "push" },
{ 0x07, MOXIE_F1_AB, "pop" },
{ 0x08, MOXIE_F1_A4, "lda.l" },
{ 0x09, MOXIE_F1_4A, "sta.l" },
{ 0x0a, MOXIE_F1_ABi, "ld.l" },
{ 0x0b, MOXIE_F1_AiB, "st.l" },
{ 0x0c, MOXIE_F1_ABi4, "ldo.l" },
{ 0x0d, MOXIE_F1_AiB4, "sto.l" },
{ 0x0e, MOXIE_F1_AB, "cmp" },
{ 0x0f, MOXIE_F1_NARG, "bad" },
{ 0x10, MOXIE_F1_NARG, "bad" },
{ 0x11, MOXIE_F1_NARG, "bad" },
{ 0x12, MOXIE_F1_NARG, "bad" },
{ 0x13, MOXIE_F1_NARG, "bad" },
{ 0x14, MOXIE_F1_NARG, "bad" },
{ 0x15, MOXIE_F1_NARG, "bad" },
{ 0x16, MOXIE_F1_NARG, "bad" },
{ 0x17, MOXIE_F1_NARG, "bad" },
{ 0x18, MOXIE_F1_NARG, "bad" },
{ 0x19, MOXIE_F1_A, "jsr" },
{ 0x1a, MOXIE_F1_M, "jmpa" },
{ 0x1b, MOXIE_F1_A4, "ldi.b" },
{ 0x1c, MOXIE_F1_ABi, "ld.b" },
{ 0x1d, MOXIE_F1_A4, "lda.b" },
{ 0x1e, MOXIE_F1_AiB, "st.b" },
{ 0x1f, MOXIE_F1_4A, "sta.b" },
{ 0x20, MOXIE_F1_A4, "ldi.s" },
{ 0x21, MOXIE_F1_ABi, "ld.s" },
{ 0x22, MOXIE_F1_A4, "lda.s" },
{ 0x23, MOXIE_F1_AiB, "st.s" },
{ 0x24, MOXIE_F1_4A, "sta.s" },
{ 0x25, MOXIE_F1_A, "jmp" },
{ 0x26, MOXIE_F1_AB, "and" },
{ 0x27, MOXIE_F1_AB, "lshr" },
{ 0x28, MOXIE_F1_AB, "ashl" },
{ 0x29, MOXIE_F1_AB, "sub.l" },
{ 0x2a, MOXIE_F1_AB, "neg" },
{ 0x2b, MOXIE_F1_AB, "or" },
{ 0x2c, MOXIE_F1_AB, "not" },
{ 0x2d, MOXIE_F1_AB, "ashr" },
{ 0x2e, MOXIE_F1_AB, "xor" },
{ 0x2f, MOXIE_F1_AB, "mul.l" },
{ 0x30, MOXIE_F1_4, "swi" },
{ 0x31, MOXIE_F1_AB, "div.l" },
{ 0x32, MOXIE_F1_AB, "udiv.l" },
{ 0x33, MOXIE_F1_AB, "mod.l" },
{ 0x34, MOXIE_F1_AB, "umod.l" },
{ 0x35, MOXIE_F1_NARG, "brk" },
{ 0x36, MOXIE_F1_ABi4, "ldo.b" },
{ 0x37, MOXIE_F1_AiB4, "sto.b" },
{ 0x38, MOXIE_F1_ABi4, "ldo.s" },
{ 0x39, MOXIE_F1_AiB4, "sto.s" },
{ 0x3a, MOXIE_F1_NARG, "bad" },
{ 0x3b, MOXIE_F1_NARG, "bad" },
{ 0x3c, MOXIE_F1_NARG, "bad" },
{ 0x3d, MOXIE_F1_NARG, "bad" },
{ 0x3e, MOXIE_F1_NARG, "bad" },
{ 0x3f, MOXIE_F1_NARG, "bad" }
};
const moxie_opc_info_t moxie_form2_opc_info[4] =
{
{ 0x00, MOXIE_F2_A8V, "inc" },
{ 0x01, MOXIE_F2_A8V, "dec" },
{ 0x02, MOXIE_F2_A8V, "gsr" },
{ 0x03, MOXIE_F2_A8V, "ssr" }
};
const moxie_opc_info_t moxie_form3_opc_info[16] =
{
{ 0x00, MOXIE_F3_PCREL,"beq" },
{ 0x01, MOXIE_F3_PCREL,"bne" },
{ 0x02, MOXIE_F3_PCREL,"blt" },
{ 0x03, MOXIE_F3_PCREL,"bgt" },
{ 0x04, MOXIE_F3_PCREL,"bltu" },
{ 0x05, MOXIE_F3_PCREL,"bgtu" },
{ 0x06, MOXIE_F3_PCREL,"bge" },
{ 0x07, MOXIE_F3_PCREL,"ble" },
{ 0x08, MOXIE_F3_PCREL,"bgeu" },
{ 0x09, MOXIE_F3_PCREL,"bleu" },
{ 0x0a, MOXIE_F3_NARG, "bad" },
{ 0x0b, MOXIE_F3_NARG, "bad" },
{ 0x0c, MOXIE_F3_NARG, "bad" },
{ 0x0d, MOXIE_F3_NARG, "bad" },
{ 0x0e, MOXIE_F3_NARG, "bad" },
{ 0x0f, MOXIE_F3_NARG, "bad" }
};
/* Macros to extract operands from the instruction word. */
#define OP_A(i) ((i >> 4) & 0xf)
#define OP_B(i) (i & 0xf)
#define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1)
static const char * reg_names[16] =
{ "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
"$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
int
print_insn_moxie(bfd_vma addr, struct disassemble_info * info)
{
int length = 2;
int status;
stream = info->stream;
const moxie_opc_info_t * opcode;
bfd_byte buffer[4];
unsigned short iword;
fprintf_function fpr = info->fprintf_func;
if ((status = info->read_memory_func(addr, buffer, 2, info)))
goto fail;
iword = (bfd_getb16(buffer) >> 16);
/* Form 1 instructions have the high bit set to 0. */
if ((iword & (1<<15)) == 0) {
/* Extract the Form 1 opcode. */
opcode = &moxie_form1_opc_info[iword >> 8];
switch (opcode->itype) {
case MOXIE_F1_NARG:
fpr(stream, "%s", opcode->name);
break;
case MOXIE_F1_A:
fpr(stream, "%s\t%s", opcode->name,
reg_names[OP_A(iword)]);
break;
case MOXIE_F1_AB:
fpr(stream, "%s\t%s, %s", opcode->name,
reg_names[OP_A(iword)],
reg_names[OP_B(iword)]);
break;
case MOXIE_F1_A4:
{
unsigned imm;
if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t%s, 0x%x", opcode->name,
reg_names[OP_A(iword)], imm);
length = 6;
}
break;
case MOXIE_F1_4:
{
unsigned imm;
if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t0x%x", opcode->name, imm);
length = 6;
}
break;
case MOXIE_F1_M:
{
unsigned imm;
if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t", opcode->name);
info->print_address_func((bfd_vma) imm, info);
length = 6;
}
break;
case MOXIE_F1_AiB:
fpr (stream, "%s\t(%s), %s", opcode->name,
reg_names[OP_A(iword)], reg_names[OP_B(iword)]);
break;
case MOXIE_F1_ABi:
fpr(stream, "%s\t%s, (%s)", opcode->name,
reg_names[OP_A(iword)], reg_names[OP_B(iword)]);
break;
case MOXIE_F1_4A:
{
unsigned imm;
if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t0x%x, %s",
opcode->name, imm, reg_names[OP_A(iword)]);
length = 6;
}
break;
case MOXIE_F1_AiB4:
{
unsigned imm;
if ((status = info->read_memory_func(addr+2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t0x%x(%s), %s", opcode->name,
imm,
reg_names[OP_A(iword)],
reg_names[OP_B(iword)]);
length = 6;
}
break;
case MOXIE_F1_ABi4:
{
unsigned imm;
if ((status = info->read_memory_func(addr+2, buffer, 4, info)))
goto fail;
imm = bfd_getb32(buffer);
fpr(stream, "%s\t%s, 0x%x(%s)",
opcode->name,
reg_names[OP_A(iword)],
imm,
reg_names[OP_B(iword)]);
length = 6;
}
break;
default:
abort();
}
}
else if ((iword & (1<<14)) == 0) {
/* Extract the Form 2 opcode. */
opcode = &moxie_form2_opc_info[(iword >> 12) & 3];
switch (opcode->itype) {
case MOXIE_F2_A8V:
fpr(stream, "%s\t%s, 0x%x",
opcode->name,
reg_names[(iword >> 8) & 0xf],
iword & ((1 << 8) - 1));
break;
case MOXIE_F2_NARG:
fpr(stream, "%s", opcode->name);
break;
default:
abort();
}
} else {
/* Extract the Form 3 opcode. */
opcode = &moxie_form3_opc_info[(iword >> 10) & 15];
switch (opcode->itype) {
case MOXIE_F3_PCREL:
fpr(stream, "%s\t", opcode->name);
info->print_address_func((bfd_vma) (addr + INST2OFFSET(iword) + 2),
info);
break;
default:
abort();
}
}
return length;
fail:
info->memory_error_func(status, addr, info);
return -1;
}
-33
View File
@@ -198,30 +198,6 @@ from Linux upstream kernel, declare it deprecated.
System emulator CPUS
--------------------
``moxie`` CPU (since 5.2.0)
'''''''''''''''''''''''''''
The ``moxie`` guest CPU support is deprecated and will be removed in
a future version of QEMU. It's unclear whether anybody is still using
CPU emulation in QEMU, and there are no test images available to make
sure that the code is still working.
``lm32`` CPUs (since 5.2.0)
'''''''''''''''''''''''''''
The ``lm32`` guest CPU support is deprecated and will be removed in
a future version of QEMU. The only public user of this architecture
was the milkymist project, which has been dead for years; there was
never an upstream Linux port.
``unicore32`` CPUs (since 5.2.0)
''''''''''''''''''''''''''''''''
The ``unicore32`` guest CPU support is deprecated and will be removed in
a future version of QEMU. Support for this CPU was removed from the
upstream Linux kernel, and there is no available upstream toolchain
to build binaries for it.
``Icelake-Client`` CPU Model (since 5.2.0)
''''''''''''''''''''''''''''''''''''''''''
@@ -293,15 +269,6 @@ The above, converted to the current supported format::
json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
``sheepdog`` driver (since 5.2.0)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The ``sheepdog`` block device driver is deprecated. The corresponding upstream
server project is no longer actively maintained. Users are recommended to switch
to an alternative distributed block device driver such as RBD. The
``qemu-img convert`` command can be used to liberate existing data by moving
it out of sheepdog volumes into an alternative storage backend.
linux-user mode CPUs
--------------------
-18
View File
@@ -85,24 +85,6 @@ These are specified using a special URL syntax.
Currently authentication must be done using ssh-agent. Other
authentication methods may be supported in future.
``Sheepdog``
Sheepdog is a distributed storage system for QEMU. QEMU supports
using either local sheepdog devices or remote networked devices.
Syntax for specifying a sheepdog device
::
sheepdog[+tcp|+unix]://[host:port]/vdiname[?socket=path][#snapid|#tag]
Example
.. parsed-literal::
|qemu_system| --drive file=sheepdog://192.0.2.1:30000/MyVirtualMachine
See also https://sheepdog.github.io/sheepdog/.
``GlusterFS``
GlusterFS is a user space distributed file system. QEMU supports the
use of GlusterFS volumes for hosting VM disk images using TCP, Unix
-69
View File
@@ -547,75 +547,6 @@ also available. Here are some example of the older syntax:
|qemu_system| linux2.img -hdb nbd:unix:/tmp/my_socket
|qemu_system| -cdrom nbd:localhost:10809:exportname=debian-500-ppc-netinst
Sheepdog disk images
~~~~~~~~~~~~~~~~~~~~
Sheepdog is a distributed storage system for QEMU. It provides highly
available block level storage volumes that can be attached to
QEMU-based virtual machines.
You can create a Sheepdog disk image with the command:
.. parsed-literal::
qemu-img create sheepdog:///IMAGE SIZE
where *IMAGE* is the Sheepdog image name and *SIZE* is its
size.
To import the existing *FILENAME* to Sheepdog, you can use a
convert command.
.. parsed-literal::
qemu-img convert FILENAME sheepdog:///IMAGE
You can boot from the Sheepdog disk image with the command:
.. parsed-literal::
|qemu_system| sheepdog:///IMAGE
You can also create a snapshot of the Sheepdog image like qcow2.
.. parsed-literal::
qemu-img snapshot -c TAG sheepdog:///IMAGE
where *TAG* is a tag name of the newly created snapshot.
To boot from the Sheepdog snapshot, specify the tag name of the
snapshot.
.. parsed-literal::
|qemu_system| sheepdog:///IMAGE#TAG
You can create a cloned image from the existing snapshot.
.. parsed-literal::
qemu-img create -b sheepdog:///BASE#TAG sheepdog:///IMAGE
where *BASE* is an image name of the source snapshot and *TAG*
is its tag name.
You can use an unix socket instead of an inet socket:
.. parsed-literal::
|qemu_system| sheepdog+unix:///IMAGE?socket=PATH
If the Sheepdog daemon doesn't run on the local host, you need to
specify one of the Sheepdog servers to connect to.
.. parsed-literal::
qemu-img create sheepdog://HOSTNAME:PORT/IMAGE SIZE
|qemu_system| sheepdog://HOSTNAME:PORT/IMAGE
iSCSI LUNs
~~~~~~~~~~
+28
View File
@@ -291,6 +291,27 @@ via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
The ``max-cpu-compat`` property of the ``pseries`` machine type should be used
instead.
``moxie`` CPU (removed in 6.1)
''''''''''''''''''''''''''''''
Nobody was using this CPU emulation in QEMU, and there were no test images
available to make sure that the code is still working, so it has been removed
without replacement.
``lm32`` CPUs (removed in 6.1.0)
''''''''''''''''''''''''''''''''
The only public user of this architecture was the milkymist project,
which has been dead for years; there was never an upstream Linux
port. Removed without replacement.
``unicore32`` CPUs (since 6.1.0)
''''''''''''''''''''''''''''''''
Support for this CPU was removed from the upstream Linux kernel, and
there is no available upstream toolchain to build binaries for it.
Removed without replacement.
System emulator machines
------------------------
@@ -467,3 +488,10 @@ VXHS backend (removed in 5.1)
'''''''''''''''''''''''''''''
The VXHS code did not compile since v2.12.0. It was removed in 5.1.
``sheepdog`` driver (removed in 6.0)
''''''''''''''''''''''''''''''''''''
The corresponding upstream server project is no longer maintained.
Users are recommended to switch to an alternative distributed block
device driver such as RBD.
+5 -6
View File
@@ -103,7 +103,7 @@ static inline bool snan_bit_is_one(float_status *status)
{
#if defined(TARGET_MIPS)
return status->snan_bit_is_one;
#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4)
#elif defined(TARGET_HPPA) || defined(TARGET_SH4)
return 1;
#else
return 0;
@@ -149,11 +149,10 @@ static FloatParts parts_default_nan(float_status *status)
sign = 1;
frac = ~0ULL;
#else
/* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
* S390, SH4, TriCore, and Xtensa. I cannot find documentation
* for Unicore32; the choice from the original commit is unchanged.
* Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile,
* do not have floating-point.
/*
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
* S390, SH4, TriCore, and Xtensa. Our other supported targets,
* CRIS, Nios2, and Tile, do not have floating-point.
*/
if (snan_bit_is_one(status)) {
/* set all bits other than msb */

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