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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180316' into staging

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Queued TCG patches

# gpg: Signature made Thu 15 Mar 2018 17:17:31 GMT
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20180316:
  tcg: Add choose_vector_size
  tcg/i386: Support INDEX_op_dup2_vec for -m32
  tcg: Improve tcg_gen_muli_i32/i64

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2018-03-16 17:25:33 +00:00
parent 9cc7d0cf6a adb196cbd5
commit 2bb39a657a
3 changed files with 286 additions and 185 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tcg/i386/tcg-target.inc.c
+9
View File
@@ -2696,6 +2696,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_x86_packus_vec:
insn = packus_insn[vece];
goto gen_simd;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_dup2_vec:
/* Constraints have already placed both 32-bit inputs in xmm regs. */
insn = OPC_PUNPCKLDQ;
goto gen_simd;
#endif
gen_simd:
tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
@@ -3045,6 +3051,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_x86_vperm2i128_vec:
case INDEX_op_x86_punpckl_vec:
case INDEX_op_x86_punpckh_vec:
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_dup2_vec:
#endif
return &x_x_x;
case INDEX_op_dup_vec:
case INDEX_op_shli_vec:
tcg/tcg-op-gvec.c
+259 -179
View File
File diff suppressed because it is too large Load Diff
tcg/tcg-op.c
+18 -6
View File
@@ -277,9 +277,15 @@ void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
{
TCGv_i32 t0 = tcg_const_i32(arg2);
tcg_gen_mul_i32(ret, arg1, t0);
tcg_temp_free_i32(t0);
if (arg2 == 0) {
tcg_gen_movi_i32(ret, 0);
} else if (is_power_of_2(arg2)) {
tcg_gen_shli_i32(ret, arg1, ctz32(arg2));
} else {
TCGv_i32 t0 = tcg_const_i32(arg2);
tcg_gen_mul_i32(ret, arg1, t0);
tcg_temp_free_i32(t0);
}
}
void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
@@ -1430,9 +1436,15 @@ void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
{
TCGv_i64 t0 = tcg_const_i64(arg2);
tcg_gen_mul_i64(ret, arg1, t0);
tcg_temp_free_i64(t0);
if (arg2 == 0) {
tcg_gen_movi_i64(ret, 0);
} else if (is_power_of_2(arg2)) {
tcg_gen_shli_i64(ret, arg1, ctz64(arg2));
} else {
TCGv_i64 t0 = tcg_const_i64(arg2);
tcg_gen_mul_i64(ret, arg1, t0);
tcg_temp_free_i64(t0);
}
}
void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)