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Replace cpu_abort with hw_error

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Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
Paul Brook
2009-05-08 02:35:15 +01:00
parent e612a1f725
commit 2ac711791b
47 changed files with 180 additions and 262 deletions
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hw/an5206.c
+1 -1
View File
@@ -41,7 +41,7 @@ static void an5206_init(ram_addr_t ram_size, int vga_ram_size,
cpu_model = "m5206";
env = cpu_init(cpu_model);
if (!env) {
cpu_abort(env, "Unable to find m68k CPU definition\n");
hw_error("Unable to find m68k CPU definition\n");
}
/* Initialize CPU registers. */
hw/arm_gic.c
+4 -6
View File
@@ -343,7 +343,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
}
return res;
bad_reg:
cpu_abort(cpu_single_env, "gic_dist_readb: Bad offset %x\n", (int)offset);
hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
return 0;
}
@@ -505,7 +505,7 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
gic_update(s);
return;
bad_reg:
cpu_abort(cpu_single_env, "gic_dist_writeb: Bad offset %x\n", (int)offset);
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
@@ -587,8 +587,7 @@ static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
case 0x18: /* Highest Pending Interrupt */
return s->current_pending[cpu];
default:
cpu_abort(cpu_single_env, "gic_cpu_read: Bad offset %x\n",
(int)offset);
hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
return 0;
}
}
@@ -609,8 +608,7 @@ static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
case 0x10: /* End Of Interrupt */
return gic_complete_irq(s, cpu, value & 0x3ff);
default:
cpu_abort(cpu_single_env, "gic_cpu_write: Bad offset %x\n",
(int)offset);
hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
return;
}
gic_update(s);
hw/arm_pic.c
+1 -1
View File
@@ -39,7 +39,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);
break;
default:
cpu_abort(env, "arm_pic_cpu_handler: Bad interrput line %d\n", irq);
hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq);
}
}
hw/arm_timer.c
+8 -8
View File
@@ -62,8 +62,7 @@ static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
return 0;
return s->int_level;
default:
cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",
(int)offset);
hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
return 0;
}
}
@@ -130,8 +129,7 @@ static void arm_timer_write(void *opaque, target_phys_addr_t offset,
arm_timer_recalibrate(s, 0);
break;
default:
cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n",
(int)offset);
hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
}
arm_timer_update(s);
}
@@ -290,8 +288,9 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
/* ??? Don't know the PrimeCell ID for this device. */
n = offset >> 8;
if (n > 3)
cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
if (n > 3) {
hw_error("sp804_read: Bad timer %d\n", n);
}
return arm_timer_read(s->timer[n], offset & 0xff);
}
@@ -303,8 +302,9 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset,
int n;
n = offset >> 8;
if (n > 3)
cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
if (n > 3) {
hw_error("sp804_write: Bad timer %d\n", n);
}
arm_timer_write(s->timer[n], offset & 0xff, value);
}
hw/armv7m_nvic.c
+7 -8
View File
@@ -102,7 +102,7 @@ int armv7m_nvic_acknowledge_irq(void *opaque)
irq = gic_acknowledge_irq(s->gic, 0);
if (irq == 1023)
cpu_abort(cpu_single_env, "Interrupt but no vector\n");
hw_error("Interrupt but no vector\n");
if (irq >= 32)
irq -= 16;
return irq;
@@ -221,8 +221,7 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
return val;
case 0xd28: /* Configurable Fault Status. */
/* TODO: Implement Fault Status. */
cpu_abort(cpu_single_env,
"Not implemented: Configurable Fault Status.");
hw_error("Not implemented: Configurable Fault Status.");
return 0;
case 0xd2c: /* Hard Fault Status. */
case 0xd30: /* Debug Fault Status. */
@@ -260,7 +259,7 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
/* TODO: Implement debug registers. */
default:
bad_reg:
cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n", offset);
hw_error("NVIC: Bad read offset 0x%x\n", offset);
}
}
@@ -324,10 +323,10 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
case 0xd0c: /* Application Interrupt/Reset Control. */
if ((value >> 16) == 0x05fa) {
if (value & 2) {
cpu_abort(cpu_single_env, "VECTCLRACTIVE not implemented");
hw_error("VECTCLRACTIVE not implemented");
}
if (value & 5) {
cpu_abort(cpu_single_env, "System reset");
hw_error("System reset");
}
}
break;
@@ -362,7 +361,7 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
goto bad_reg;
default:
bad_reg:
cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n", offset);
hw_error("NVIC: Bad write offset 0x%x\n", offset);
}
}
@@ -402,7 +401,7 @@ qemu_irq *armv7m_nvic_init(CPUState *env)
s->gic->nvic = s;
s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s);
if (env->v7m.nvic)
cpu_abort(env, "CPU can only have one NVIC\n");
hw_error("CPU can only have one NVIC\n");
env->v7m.nvic = s;
register_savevm("armv7m_nvic", -1, 1, nvic_save, nvic_load, s);
return s->gic->in;
hw/cbus.c
+5 -10
View File
@@ -63,8 +63,7 @@ static void cbus_io(struct cbus_priv_s *s)
s->slave[s->addr]->io(s->slave[s->addr]->opaque,
s->rw, s->reg, &s->val);
else
cpu_abort(cpu_single_env, "%s: bad slave address %i\n",
__FUNCTION__, s->addr);
hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr);
}
static void cbus_cycle(struct cbus_priv_s *s)
@@ -301,8 +300,7 @@ static inline uint16_t retu_read(struct cbus_retu_s *s, int reg)
return 0x0000;
default:
cpu_abort(cpu_single_env, "%s: bad register %02x\n",
__FUNCTION__, reg);
hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
}
}
@@ -375,8 +373,7 @@ static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val)
break;
default:
cpu_abort(cpu_single_env, "%s: bad register %02x\n",
__FUNCTION__, reg);
hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
}
}
@@ -542,8 +539,7 @@ static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg)
return 0x0000;
default:
cpu_abort(cpu_single_env, "%s: bad register %02x\n",
__FUNCTION__, reg);
hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
}
}
@@ -593,8 +589,7 @@ static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val)
break;
default:
cpu_abort(cpu_single_env, "%s: bad register %02x\n",
__FUNCTION__, reg);
hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
}
}
hw/etraxfs_dma.c
+2 -8
View File
@@ -562,10 +562,7 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
{
struct fs_dma_ctrl *ctrl = opaque;
CPUState *env = ctrl->env;
cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
addr);
hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
@@ -600,10 +597,7 @@ dma_readl (void *opaque, target_phys_addr_t addr)
static void
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_dma_ctrl *ctrl = opaque;
CPUState *env = ctrl->env;
cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
addr);
hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr);
}
static void
hw/etraxfs_pic.c
+1 -2
View File
@@ -148,8 +148,7 @@ static void nmi_handler(void *opaque, int irq, int level)
static void guru_handler(void *opaque, int irq, int level)
{
struct fs_pic_state *fs = (void *)opaque;
cpu_abort(fs->env, "%s unsupported exception\n", __func__);
hw_error("%s unsupported exception\n", __func__);
}
struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
hw/integratorcp.c
+10 -12
View File
@@ -63,7 +63,7 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
}
case 6: /* CM_LMBUSCNT */
/* ??? High frequency timer. */
cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
hw_error("integratorcm_read: CM_LMBUSCNT");
case 7: /* CM_AUXOSC */
return s->cm_auxosc;
case 8: /* CM_SDRAM */
@@ -72,7 +72,7 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
return s->cm_init;
case 10: /* CM_REFCT */
/* ??? High frequency timer. */
cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
hw_error("integratorcm_read: CM_REFCT");
case 12: /* CM_FLAGS */
return s->cm_flags;
case 14: /* CM_NVFLAGS */
@@ -98,8 +98,8 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
/* ??? Voltage control unimplemented. */
return 0;
default:
cpu_abort (cpu_single_env,
"integratorcm_read: Unimplemented offset 0x%x\n", (int)offset);
hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
(int)offset);
return 0;
}
}
@@ -117,7 +117,7 @@ static void integratorcm_do_remap(integratorcm_state *s, int flash)
static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
{
if (value & 8) {
cpu_abort(cpu_single_env, "Board reset\n");
hw_error("Board reset\n");
}
if ((s->cm_init ^ value) & 4) {
integratorcm_do_remap(s, (value & 4) == 0);
@@ -133,7 +133,7 @@ static void integratorcm_update(integratorcm_state *s)
/* ??? The CPU irq/fiq is raised when either the core module or base PIC
are active. */
if (s->int_level & (s->irq_enabled | s->fiq_enabled))
cpu_abort(cpu_single_env, "Core module interrupt\n");
hw_error("Core module interrupt\n");
}
static void integratorcm_write(void *opaque, target_phys_addr_t offset,
@@ -205,8 +205,8 @@ static void integratorcm_write(void *opaque, target_phys_addr_t offset,
/* ??? Voltage control unimplemented. */
break;
default:
cpu_abort (cpu_single_env,
"integratorcm_write: Unimplemented offset 0x%x\n", (int)offset);
hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
(int)offset);
break;
}
}
@@ -401,8 +401,7 @@ static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
case 3: /* CP_DECODE */
return 0x11;
default:
cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n",
(int)offset);
hw_error("icp_control_read: Bad offset %x\n", (int)offset);
return 0;
}
}
@@ -417,8 +416,7 @@ static void icp_control_write(void *opaque, target_phys_addr_t offset,
/* Nothing interesting implemented yet. */
break;
default:
cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n",
(int)offset);
hw_error("icp_control_write: Bad offset %x\n", (int)offset);
}
}
static CPUReadMemoryFunc *icp_control_readfn[] = {
hw/mcf5206.c
+10 -12
View File
@@ -61,11 +61,9 @@ static void m5206_timer_recalibrate(m5206_timer_state *s)
prescale *= 16;
if (mode == 3 || mode == 0)
cpu_abort(cpu_single_env,
"m5206_timer: mode %d not implemented\n", mode);
hw_error("m5206_timer: mode %d not implemented\n", mode);
if ((s->tmr & TMR_FRR) == 0)
cpu_abort(cpu_single_env,
"m5206_timer: free running mode not implemented\n");
hw_error("m5206_timer: free running mode not implemented\n");
/* Assume 66MHz system clock. */
ptimer_set_freq(s->timer, 66000000 / prescale);
@@ -296,7 +294,7 @@ static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset)
case 0x170: return s->uivr[0];
case 0x1b0: return s->uivr[1];
}
cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
hw_error("Bad MBAR read offset 0x%x", (int)offset);
return 0;
}
@@ -350,7 +348,7 @@ static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
s->uivr[1] = value;
break;
default:
cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
hw_error("Bad MBAR write offset 0x%x", (int)offset);
break;
}
}
@@ -377,7 +375,7 @@ static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
offset &= 0x3ff;
if (offset > 0x200) {
cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
hw_error("Bad MBAR read offset 0x%x", (int)offset);
}
if (m5206_mbar_width[offset >> 2] > 1) {
uint16_t val;
@@ -396,7 +394,7 @@ static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
int width;
offset &= 0x3ff;
if (offset > 0x200) {
cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
hw_error("Bad MBAR read offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width > 2) {
@@ -420,7 +418,7 @@ static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
int width;
offset &= 0x3ff;
if (offset > 0x200) {
cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
hw_error("Bad MBAR read offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width < 4) {
@@ -444,7 +442,7 @@ static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
int width;
offset &= 0x3ff;
if (offset > 0x200) {
cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
hw_error("Bad MBAR write offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width > 1) {
@@ -468,7 +466,7 @@ static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
int width;
offset &= 0x3ff;
if (offset > 0x200) {
cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
hw_error("Bad MBAR write offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width > 2) {
@@ -496,7 +494,7 @@ static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
int width;
offset &= 0x3ff;
if (offset > 0x200) {
cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
hw_error("Bad MBAR write offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width < 4) {
hw/mcf5208.c
+4 -8
View File
@@ -89,8 +89,7 @@ static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
case 4:
break;
default:
cpu_abort(cpu_single_env, "m5208_timer_write: Bad offset 0x%x\n",
(int)offset);
hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
break;
}
m5208_timer_update(s);
@@ -114,8 +113,7 @@ static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
case 4:
return ptimer_get_count(s->timer);
default:
cpu_abort(cpu_single_env, "m5208_timer_read: Bad offset 0x%x\n",
(int)addr);
hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
return 0;
}
}
@@ -148,8 +146,7 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
return 0;
default:
cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
(int)addr);
hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
return 0;
}
}
@@ -157,8 +154,7 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
(int)addr);
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
}
static CPUReadMemoryFunc *m5208_sys_readfn[] = {
hw/mcf_fec.c
+2 -4
View File
@@ -246,8 +246,7 @@ static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
case 0x184: return s->etdsr;
case 0x188: return s->emrbr;
default:
cpu_abort(cpu_single_env, "mcf_fec_read: Bad address 0x%x\n",
(int)addr);
hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
return 0;
}
}
@@ -343,8 +342,7 @@ static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
s->emrbr = value & 0x7f0;
break;
default:
cpu_abort(cpu_single_env, "mcf_fec_write Bad address 0x%x\n",
(int)addr);
hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
}
mcf_fec_update(s);
}
hw/mcf_intc.c
+2 -3
View File
@@ -67,7 +67,7 @@ static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
case 0xe1: case 0xe2: case 0xe3: case 0xe4:
case 0xe5: case 0xe6: case 0xe7:
/* LnIACK */
cpu_abort(cpu_single_env, "mcf_intc_read: LnIACK not implemented\n");
hw_error("mcf_intc_read: LnIACK not implemented\n");
default:
return 0;
}
@@ -99,8 +99,7 @@ static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val)
s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
break;
default:
cpu_abort(cpu_single_env, "mcf_intc_write: Bad write offset %d\n",
offset);
hw_error("mcf_intc_write: Bad write offset %d\n", offset);
break;
}
mcf_intc_update(s);
hw/mpcore.c
+2 -4
View File
@@ -195,8 +195,7 @@ static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
return mpcore_timer_read(&s->timer[id], offset & 0xf);
}
bad_reg:
cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
(int)offset);
hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
return 0;
}
@@ -241,8 +240,7 @@ static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
}
return;
bad_reg:
cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
(int)offset);
hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
}
static CPUReadMemoryFunc *mpcore_priv_readfn[] = {
hw/musicpal.c
+1 -1
View File
@@ -875,7 +875,7 @@ static void lcd_refresh(void *opaque)
LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
rgb_to_pixel32bgr : rgb_to_pixel32))
default:
cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
hw_error("unsupported colour depth %i\n",
ds_get_bits_per_pixel(s->ds));
}
hw/nand.c
+2 -4
View File
@@ -445,8 +445,7 @@ struct nand_flash_s *nand_init(int manf_id, int chip_id)
int index;
if (nand_flash_ids[chip_id].size == 0) {
cpu_abort(cpu_single_env, "%s: Unsupported NAND chip ID.\n",
__FUNCTION__);
hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
}
s = (struct nand_flash_s *) qemu_mallocz(sizeof(struct nand_flash_s));
@@ -475,8 +474,7 @@ struct nand_flash_s *nand_init(int manf_id, int chip_id)
nand_init_2048(s);
break;
default:
cpu_abort(cpu_single_env, "%s: Unsupported NAND block size.\n",
__FUNCTION__);
hw_error("%s: Unsupported NAND block size.\n", __FUNCTION__);
}
pagesize = 1 << s->oob_shift;
hw/nseries.c
+1 -2
View File
@@ -428,8 +428,7 @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
uint8_t ret;
if (len > 9)
cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
__FUNCTION__, len);
hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
if (s->p >= ARRAY_SIZE(s->resp))
ret = 0;
hw/omap1.c
+5 -6
View File
@@ -1531,7 +1531,7 @@ static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
case omap1510:
return 0x03310115;
default:
cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
hw_error("%s: bad mpu model\n", __FUNCTION__);
}
break;
@@ -1542,7 +1542,7 @@ static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
case omap1510:
return 0xfb47002f;
default:
cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
hw_error("%s: bad mpu model\n", __FUNCTION__);
}
break;
}
@@ -2775,15 +2775,14 @@ qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
{
if (line >= 16 || line < 0)
cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
s->handler[line] = handler;
}
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
{
if (row >= 5 || row < 0)
cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
__FUNCTION__, col, row);
hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
if (down)
s->buttons[row] |= 1 << col;
@@ -2970,7 +2969,7 @@ qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
{
if (line >= 16 || line < 0)
cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
s->handler[line] = handler;
}
hw/omap2.c
+6 -8
View File
@@ -1070,15 +1070,14 @@ struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
{
if (start >= s->modules * 32 || start < 0)
cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
__FUNCTION__, start);
hw_error("%s: No GPIO line %i\n", __FUNCTION__, start);
return s->module[start >> 5].in + (start & 31);
}
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
{
if (line >= s->modules * 32 || line < 0)
cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
s->module[line >> 5].handler[line & 31] = handler;
}
@@ -1399,8 +1398,7 @@ void omap_mcspi_attach(struct omap_mcspi_s *s,
int chipselect)
{
if (chipselect < 0 || chipselect >= s->chnum)
cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n",
__FUNCTION__, chipselect);
hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
s->ch[chipselect].txrx = txrx;
s->ch[chipselect].opaque = opaque;
@@ -2642,7 +2640,7 @@ static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
case omap3430:
return 0x1b7ae02f; /* ES 2 */
default:
cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
hw_error("%s: Bad mpu model\n", __FUNCTION__);
}
case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
@@ -2659,7 +2657,7 @@ static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
case omap3430:
return 0x000000f0;
default:
cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
hw_error("%s: Bad mpu model\n", __FUNCTION__);
}
case 0x20c:
@@ -2673,7 +2671,7 @@ static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
case omap3430:
return 0xcafeb7ae; /* ES 2 */
default:
cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
hw_error("%s: Bad mpu model\n", __FUNCTION__);
}
case 0x218: /* DIE_ID_reg */
hw/omap_clk.c
+2 -3
View File
@@ -1105,7 +1105,7 @@ struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name)
for (i = mpu->clks; i->name; i ++)
if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
return i;
cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
hw_error("%s: %s not found\n", __FUNCTION__, name);
}
void omap_clk_get(struct clk *clk)
@@ -1116,8 +1116,7 @@ void omap_clk_get(struct clk *clk)
void omap_clk_put(struct clk *clk)
{
if (!(clk->usecount --))
cpu_abort(cpu_single_env, "%s: %s is not in use\n",
__FUNCTION__, clk->name);
hw_error("%s: %s is not in use\n", __FUNCTION__, clk->name);
}
static void omap_clk_update(struct clk *clk)

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