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hw/arm/allwinner-h3: add EMAC ethernet device
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC) which provides 10M/100M/1000M Ethernet connectivity. This commit adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc), including emulation for the following functionality: * DMA transfers * MII interface * Transmit CRC calculation Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-10-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Niek Linnenbank
committed by
Peter Maydell
Peter Maydell
parent
82e4838249
commit
29d08975d1
@@ -300,6 +300,7 @@ config ALLWINNER_A10
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config ALLWINNER_H3
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bool
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select ALLWINNER_A10_PIT
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select ALLWINNER_SUN8I_EMAC
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select SERIAL
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select ARM_TIMER
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select ARM_GIC
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+15
-1
@@ -54,6 +54,7 @@ const hwaddr allwinner_h3_memmap[] = {
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[AW_H3_UART1] = 0x01c28400,
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[AW_H3_UART2] = 0x01c28800,
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[AW_H3_UART3] = 0x01c28c00,
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[AW_H3_EMAC] = 0x01c30000,
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[AW_H3_GIC_DIST] = 0x01c81000,
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[AW_H3_GIC_CPU] = 0x01c82000,
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[AW_H3_GIC_HYP] = 0x01c84000,
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@@ -106,7 +107,6 @@ struct AwH3Unimplemented {
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{ "twi1", 0x01c2b000, 1 * KiB },
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{ "twi2", 0x01c2b400, 1 * KiB },
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{ "scr", 0x01c2c400, 1 * KiB },
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{ "emac", 0x01c30000, 64 * KiB },
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{ "gpu", 0x01c40000, 64 * KiB },
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{ "hstmr", 0x01c60000, 4 * KiB },
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{ "dramcom", 0x01c62000, 4 * KiB },
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@@ -162,6 +162,7 @@ enum {
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AW_H3_GIC_SPI_OHCI2 = 77,
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AW_H3_GIC_SPI_EHCI3 = 78,
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AW_H3_GIC_SPI_OHCI3 = 79,
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AW_H3_GIC_SPI_EMAC = 82
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};
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/* Allwinner H3 general constants */
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@@ -207,6 +208,9 @@ static void allwinner_h3_init(Object *obj)
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sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
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TYPE_AW_SDHOST_SUN5I);
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sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
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TYPE_AW_SUN8I_EMAC);
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}
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static void allwinner_h3_realize(DeviceState *dev, Error **errp)
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@@ -337,6 +341,16 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
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object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
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"sd-bus", &error_abort);
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/* EMAC */
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if (nd_table[0].used) {
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qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
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qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
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}
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qdev_init_nofail(DEVICE(&s->emac));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
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qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
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/* Universal Serial Bus */
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sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
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qdev_get_gpio_in(DEVICE(&s->gic),
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@@ -77,6 +77,9 @@ static void orangepi_init(MachineState *machine)
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warn_report("Security Identifier value does not include H3 prefix");
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}
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/* Setup EMAC properties */
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object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
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/* Mark H3 object realized */
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object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
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@@ -79,6 +79,9 @@ config MIPSNET
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config ALLWINNER_EMAC
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bool
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config ALLWINNER_SUN8I_EMAC
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bool
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config IMX_FEC
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bool
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@@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) += xgmac.o
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common-obj-$(CONFIG_MIPSNET) += mipsnet.o
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common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
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common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o
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common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o
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common-obj-$(CONFIG_IMX_FEC) += imx_fec.o
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common-obj-$(CONFIG_CADENCE) += cadence_gem.o
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File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,15 @@
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# See docs/devel/tracing.txt for syntax documentation.
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# allwinner-sun8i-emac.c
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allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32
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allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32
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allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
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allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
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allwinner_sun8i_emac_reset(void) "HW reset"
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allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
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allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
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allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
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# etraxfs_eth.c
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mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x"
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mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x"
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@@ -44,6 +44,7 @@
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#include "hw/misc/allwinner-h3-sysctrl.h"
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#include "hw/misc/allwinner-sid.h"
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#include "hw/sd/allwinner-sdhost.h"
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#include "hw/net/allwinner-sun8i-emac.h"
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#include "target/arm/cpu.h"
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/**
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@@ -77,6 +78,7 @@ enum {
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AW_H3_UART1,
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AW_H3_UART2,
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AW_H3_UART3,
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AW_H3_EMAC,
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AW_H3_GIC_DIST,
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AW_H3_GIC_CPU,
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AW_H3_GIC_HYP,
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@@ -120,6 +122,7 @@ typedef struct AwH3State {
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AwH3SysCtrlState sysctrl;
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AwSidState sid;
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AwSdHostState mmc0;
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AwSun8iEmacState emac;
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GICState gic;
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MemoryRegion sram_a1;
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MemoryRegion sram_a2;
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@@ -0,0 +1,99 @@
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/*
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* Allwinner Sun8i Ethernet MAC emulation
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*
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* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
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#define HW_NET_ALLWINNER_SUN8I_EMAC_H
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#include "qom/object.h"
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#include "net/net.h"
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#include "hw/sysbus.h"
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/**
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* Object model
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* @{
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*/
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#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
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#define AW_SUN8I_EMAC(obj) \
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OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC)
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/** @} */
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/**
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* Allwinner Sun8i EMAC object instance state
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*/
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typedef struct AwSun8iEmacState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/** Maps I/O registers in physical memory */
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MemoryRegion iomem;
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/** Interrupt output signal to notify CPU */
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qemu_irq irq;
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/** Generic Network Interface Controller (NIC) for networking API */
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NICState *nic;
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/** Generic Network Interface Controller (NIC) configuration */
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NICConf conf;
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/**
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* @name Media Independent Interface (MII)
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* @{
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*/
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uint8_t mii_phy_addr; /**< PHY address */
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uint32_t mii_cr; /**< Control */
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uint32_t mii_st; /**< Status */
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uint32_t mii_adv; /**< Advertised Abilities */
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/** @} */
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/**
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* @name Hardware Registers
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* @{
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*/
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uint32_t basic_ctl0; /**< Basic Control 0 */
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uint32_t basic_ctl1; /**< Basic Control 1 */
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uint32_t int_en; /**< Interrupt Enable */
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uint32_t int_sta; /**< Interrupt Status */
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uint32_t frm_flt; /**< Receive Frame Filter */
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uint32_t rx_ctl0; /**< Receive Control 0 */
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uint32_t rx_ctl1; /**< Receive Control 1 */
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uint32_t rx_desc_head; /**< Receive Descriptor List Address */
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uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
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uint32_t tx_ctl0; /**< Transmit Control 0 */
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uint32_t tx_ctl1; /**< Transmit Control 1 */
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uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
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uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
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uint32_t tx_flowctl; /**< Transmit Flow Control */
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uint32_t mii_cmd; /**< Management Interface Command */
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uint32_t mii_data; /**< Management Interface Data */
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/** @} */
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} AwSun8iEmacState;
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#endif /* HW_NET_ALLWINNER_SUN8I_H */
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