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Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging

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target/xtensa: SR reorganization and options for modern cores

Reorganize special register handling to support configurations with
conflicting SR definitions.

Implement options used by the modern xtensa cores:
- memory protection unit;
- block prefetch;
- exclusive access

Add special register definitions and IRQ types for ECC/parity,
gather/scatter and IDMA.

# gpg: Signature made Mon 20 May 2019 18:53:05 BST
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190520-xtensa:
  target/xtensa: implement exclusive access option
  target/xtensa: update list of exception causes
  target/xtensa: implement block prefetch option opcodes
  target/xtensa: implement DIWBUI.P opcode
  target/xtensa: implement MPU option
  target/xtensa: add parity/ECC option SRs
  target/xtensa: define IDMA and gather/scatter IRQ types
  target/xtensa: make internal MMU functions static
  target/xtensa: get rid of centralized SR properties

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2019-05-21 10:44:21 +01:00
parent 2259637b95 b345e14053
commit 293c76cb48
9 changed files with 2592 additions and 1127 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/xtensa/cpu.c
+1 -1
View File
@@ -78,11 +78,11 @@ static void xtensa_cpu_reset(CPUState *s)
env->sregs[VECBASE] = env->config->vecbase;
env->sregs[IBREAKENABLE] = 0;
env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
env->sregs[CACHEATTR] = 0x22222222;
env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
env->sregs[CONFIGID0] = env->config->configid[0];
env->sregs[CONFIGID1] = env->config->configid[1];
env->exclusive_addr = -1;
#ifndef CONFIG_USER_ONLY
reset_mmu(env);
target/xtensa/cpu.h
+35 -23
View File
@@ -99,6 +99,7 @@ enum {
/* Memory protection and translation */
XTENSA_OPTION_REGION_PROTECTION,
XTENSA_OPTION_REGION_TRANSLATION,
XTENSA_OPTION_MPU,
XTENSA_OPTION_MMU,
XTENSA_OPTION_CACHEATTR,
@@ -137,13 +138,23 @@ enum {
PTEVADDR = 83,
MMID = 89,
RASID = 90,
MPUENB = 90,
ITLBCFG = 91,
DTLBCFG = 92,
MPUCFG = 92,
ERACCESS = 95,
IBREAKENABLE = 96,
MEMCTL = 97,
CACHEATTR = 98,
CACHEADRDIS = 98,
ATOMCTL = 99,
DDR = 104,
MEPC = 106,
MEPS = 107,
MESAVE = 108,
MESR = 109,
MECR = 110,
MEVADDR = 111,
IBREAKA = 128,
DBREAKA = 144,
DBREAKC = 160,
@@ -228,6 +239,7 @@ enum {
#define MAX_TLB_WAY_SIZE 8
#define MAX_NDBREAK 2
#define MAX_NMEMORY 4
#define MAX_MPU_FOREGROUND_SEGMENTS 32
#define REGION_PAGE_MASK 0xe0000000
@@ -268,14 +280,15 @@ enum {
LEVEL1_INTERRUPT_CAUSE,
ALLOCA_CAUSE,
INTEGER_DIVIDE_BY_ZERO_CAUSE,
PRIVILEGED_CAUSE = 8,
PC_VALUE_ERROR_CAUSE,
PRIVILEGED_CAUSE,
LOAD_STORE_ALIGNMENT_CAUSE,
INSTR_PIF_DATA_ERROR_CAUSE = 12,
EXTERNAL_REG_PRIVILEGE_CAUSE,
EXCLUSIVE_ERROR_CAUSE,
INSTR_PIF_DATA_ERROR_CAUSE,
LOAD_STORE_PIF_DATA_ERROR_CAUSE,
INSTR_PIF_ADDR_ERROR_CAUSE,
LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
INST_TLB_MISS_CAUSE,
INST_TLB_MULTI_HIT_CAUSE,
INST_FETCH_PRIVILEGE_CAUSE,
@@ -298,6 +311,9 @@ typedef enum {
INTTYPE_DEBUG,
INTTYPE_WRITE_ERR,
INTTYPE_PROFILING,
INTTYPE_IDMA_DONE,
INTTYPE_IDMA_ERR,
INTTYPE_GS_ERR,
INTTYPE_MAX
} interrupt_type;
@@ -318,6 +334,11 @@ typedef struct xtensa_tlb {
unsigned nrefillentries;
} xtensa_tlb;
typedef struct xtensa_mpu_entry {
uint32_t vaddr;
uint32_t attr;
} xtensa_mpu_entry;
typedef struct XtensaGdbReg {
int targno;
unsigned flags;
@@ -446,6 +467,7 @@ struct XtensaConfig {
unsigned icache_ways;
unsigned dcache_ways;
unsigned dcache_line_bytes;
uint32_t memctl_mask;
XtensaMemory instrom;
@@ -468,6 +490,11 @@ struct XtensaConfig {
xtensa_tlb itlb;
xtensa_tlb dtlb;
uint32_t mpu_align;
unsigned n_mpu_fg_segments;
unsigned n_mpu_bg_segments;
const xtensa_mpu_entry *mpu_bg;
};
typedef struct XtensaConfigList {
@@ -500,10 +527,13 @@ typedef struct CPUXtensaState {
} fregs[16];
float_status fp_status;
uint32_t windowbase_next;
uint32_t exclusive_addr;
uint32_t exclusive_val;
#ifndef CONFIG_USER_ONLY
xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS];
unsigned autorefill_idx;
bool runstall;
AddressSpace *address_space_er;
@@ -590,6 +620,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
#define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
void xtensa_collect_sr_names(const XtensaConfig *config);
void xtensa_translate_init(void);
void **xtensa_get_regfile_by_name(const char *name);
void xtensa_breakpoint_handler(CPUState *cs);
@@ -658,17 +689,6 @@ static inline int xtensa_get_cring(const CPUXtensaState *env)
}
#ifndef CONFIG_USER_ONLY
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env,
bool dtlb, uint32_t way);
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring);
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
xtensa_tlb_entry *entry, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access);
@@ -679,14 +699,6 @@ static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
{
return env->system_er;
}
static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
bool dtlb, unsigned wi, unsigned ei)
{
return dtlb ?
env->dtlb[wi] + ei :
env->itlb[wi] + ei;
}
#endif
static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
target/xtensa/helper.c
+1
View File
@@ -141,6 +141,7 @@ static void init_libisa(XtensaConfig *config)
}
#endif
}
xtensa_collect_sr_names(config);
}
static void xtensa_finalize_config(XtensaConfig *config)
target/xtensa/helper.h
+6
View File
@@ -24,6 +24,7 @@ DEF_HELPER_1(check_interrupts, void, env)
DEF_HELPER_2(intset, void, env, i32)
DEF_HELPER_2(intclear, void, env, i32)
DEF_HELPER_3(check_atomctl, void, env, i32, i32)
DEF_HELPER_4(check_exclusive, void, env, i32, i32, i32)
DEF_HELPER_2(wsr_memctl, void, env, i32)
DEF_HELPER_2(itlb_hit_test, void, env, i32)
@@ -33,6 +34,11 @@ DEF_HELPER_FLAGS_3(rtlb1, TCG_CALL_NO_RWG_SE, i32, env, i32, i32)
DEF_HELPER_3(itlb, void, env, i32, i32)
DEF_HELPER_3(ptlb, i32, env, i32, i32)
DEF_HELPER_4(wtlb, void, env, i32, i32, i32)
DEF_HELPER_2(wsr_mpuenb, void, env, i32)
DEF_HELPER_3(wptlb, void, env, i32, i32)
DEF_HELPER_FLAGS_2(rptlb0, TCG_CALL_NO_RWG_SE, i32, env, i32)
DEF_HELPER_FLAGS_2(rptlb1, TCG_CALL_NO_RWG_SE, i32, env, i32)
DEF_HELPER_2(pptlb, i32, env, i32)
DEF_HELPER_2(wsr_ibreakenable, void, env, i32)
DEF_HELPER_3(wsr_ibreaka, void, env, i32, i32)
target/xtensa/mmu_helper.c
+456 -76
View File
File diff suppressed because it is too large Load Diff
target/xtensa/op_helper.c
+42
View File
@@ -130,6 +130,48 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
}
}
void HELPER(check_exclusive)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr,
uint32_t is_write)
{
uint32_t paddr, page_size, access;
uint32_t atomctl = env->sregs[ATOMCTL];
int rc = xtensa_get_physical_addr(env, true, vaddr, is_write,
xtensa_get_cring(env), &paddr,
&page_size, &access);
if (rc) {
HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
}
/* When data cache is not configured use ATOMCTL bypass field. */
if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
access = PAGE_CACHE_BYPASS;
}
switch (access & PAGE_CACHE_MASK) {
case PAGE_CACHE_WB:
atomctl >>= 2;
/* fall through */
case PAGE_CACHE_WT:
atomctl >>= 2;
/* fall through */
case PAGE_CACHE_BYPASS:
if ((atomctl & 0x3) == 0) {
HELPER(exception_cause_vaddr)(env, pc,
EXCLUSIVE_ERROR_CAUSE, vaddr);
}
break;
case PAGE_CACHE_ISOLATE:
HELPER(exception_cause_vaddr)(env, pc,
LOAD_STORE_ERROR_CAUSE, vaddr);
break;
default:
break;
}
}
void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t v)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_ICACHE)) {
target/xtensa/overlay_tool.h
+41 -2
View File
@@ -72,6 +72,14 @@
#define XCHAL_HAVE_EXTERN_REGS 0
#endif
#ifndef XCHAL_HAVE_MPU
#define XCHAL_HAVE_MPU 0
#endif
#ifndef XCHAL_HAVE_EXCLUSIVE
#define XCHAL_HAVE_EXCLUSIVE 0
#endif
#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
#define XTENSA_OPTIONS ( \
@@ -92,8 +100,8 @@
XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
XTENSA_OPTION_ATOMCTL) | \
XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000) || \
XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \
XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
/* Interrupts and exceptions */ \
XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
@@ -112,11 +120,14 @@
XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \
XTENSA_OPTION_MEMORY_ECC_PARITY) | \
/* Memory protection and translation */ \
XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
XTENSA_OPTION_REGION_PROTECTION) | \
XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
XTENSA_OPTION_REGION_TRANSLATION) | \
XCHAL_OPTION(XCHAL_HAVE_MPU, XTENSA_OPTION_MPU) | \
XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
/* Other, TODO */ \
@@ -200,6 +211,9 @@
#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
#define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
#define XTHAL_INTTYPE_IDMA_DONE INTTYPE_IDMA_DONE
#define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR
#define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR
#define INTERRUPT(i) { \
@@ -356,6 +370,30 @@
#define XCHAL_SYSRAM0_SIZE 0x04000000
#endif
#elif XCHAL_HAVE_MPU
#ifndef XTENSA_MPU_BG_MAP
#define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\
{ .vaddr = 0, .attr = 0x00006700, }, \
}
#endif
#define TLB_SECTION \
.mpu_align = XCHAL_MPU_ALIGN, \
.n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \
.n_mpu_bg_segments = 1, \
.mpu_bg = XTENSA_MPU_BG_MAP
#ifndef XCHAL_SYSROM0_PADDR
#define XCHAL_SYSROM0_PADDR 0x50000000
#define XCHAL_SYSROM0_SIZE 0x04000000
#endif
#ifndef XCHAL_SYSRAM0_PADDR
#define XCHAL_SYSRAM0_PADDR 0x60000000
#define XCHAL_SYSRAM0_SIZE 0x04000000
#endif
#else
#ifndef XCHAL_SYSROM0_PADDR
@@ -391,6 +429,7 @@
#define CACHE_SECTION \
.icache_ways = XCHAL_ICACHE_WAYS, \
.dcache_ways = XCHAL_DCACHE_WAYS, \
.dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
.memctl_mask = \
(XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
(XCHAL_DCACHE_SIZE ? \
target/xtensa/translate.c
+1962 -1025
View File
File diff suppressed because it is too large Load Diff
tests/tcg/xtensa/test_exclusive.S
+48
View File
@@ -0,0 +1,48 @@
#include "macros.inc"
test_suite exclusive
#if XCHAL_HAVE_EXCLUSIVE
test exclusive_nowrite
movi a2, 0x29
wsr a2, atomctl
clrex
movi a2, 1f
movi a3, 1
s32ex a3, a2
getex a3
assert eqi, a3, 0
l32i a3, a2, 0
assert eqi, a3, 3
.data
.align 4
1:
.word 3
.text
test_end
test exclusive_write
movi a2, 0x29
wsr a2, atomctl
movi a2, 1f
l32ex a3, a2
assert eqi, a3, 3
movi a3, 2
s32ex a3, a2
getex a3
assert eqi, a3, 1
l32i a3, a2, 0
assert eqi, a3, 2
.data
.align 4
1:
.word 3
.text
test_end
#endif
test_suite_end