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Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging

Browse Source 
X86 queue, 2016-05-23

# gpg: Signature made Mon 23 May 2016 23:48:27 BST using RSA key ID 984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"

* remotes/ehabkost/tags/x86-pull-request:
  target-i386: kvm: Eliminate kvm_msr_entry_set()
  target-i386: kvm: Simplify MSR setting functions
  target-i386: kvm: Simplify MSR array construction
  target-i386: kvm: Increase MSR_BUF_SIZE
  target-i386: kvm: Allocate kvm_msrs struct once per VCPU
  target-i386: Call cpu_exec_init() on realize
  target-i386: Move TCG initialization to realize time
  target-i386: Move TCG initialization check to tcg_x86_init()
  cpu: Eliminate cpudef_init(), cpudef_setup()
  target-i386: Set constant model_id for qemu64/qemu32/athlon
  pc: Set CPU model-id on compat_props for pc <= 2.4
  osdep: Move default qemu_hw_version() value to a macro
  target-i386: kvm: Use X86XSaveArea struct for xsave save/load
  target-i386: Use xsave structs for ext_save_area
  target-i386: Define structs for layout of xsave area

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2016-05-24 13:06:33 +01:00
parent 99694362ee 1abc2cae46
commit 287db79df8
13 changed files with 400 additions and 299 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch_init.c
-7
View File
@@ -274,13 +274,6 @@ void do_smbios_option(QemuOpts *opts)
#endif
}
void cpudef_init(void)
{
#if defined(cpudef_setup)
cpudef_setup(); /* parse cpu definitions in target config file */
#endif
}
int kvm_available(void)
{
#ifdef CONFIG_KVM
bsd-user/main.c
-3
View File
@@ -753,9 +753,6 @@ int main(int argc, char **argv)
}
cpu_model = NULL;
#if defined(cpudef_setup)
cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
#endif
optind = 1;
for(;;) {
hw/i386/pc_piix.c
+13
View File
@@ -582,6 +582,7 @@ DEFINE_I440FX_MACHINE(v1_4, "pc-i440fx-1.4", pc_compat_1_4,
#define PC_COMPAT_1_3 \
PC_CPU_MODEL_IDS("1.3.0") \
{\
.driver = "usb-tablet",\
.property = "usb_version",\
@@ -613,6 +614,7 @@ DEFINE_I440FX_MACHINE(v1_3, "pc-1.3", pc_compat_1_3,
#define PC_COMPAT_1_2 \
PC_CPU_MODEL_IDS("1.2.0") \
{\
.driver = "nec-usb-xhci",\
.property = "msi",\
@@ -651,6 +653,7 @@ DEFINE_I440FX_MACHINE(v1_2, "pc-1.2", pc_compat_1_2,
#define PC_COMPAT_1_1 \
PC_CPU_MODEL_IDS("1.1.0") \
{\
.driver = "virtio-scsi-pci",\
.property = "hotplug",\
@@ -693,6 +696,7 @@ DEFINE_I440FX_MACHINE(v1_1, "pc-1.1", pc_compat_1_2,
#define PC_COMPAT_1_0 \
PC_CPU_MODEL_IDS("1.0") \
{\
.driver = TYPE_ISA_FDC,\
.property = "check_media_rate",\
@@ -722,10 +726,14 @@ DEFINE_I440FX_MACHINE(v1_0, "pc-1.0", pc_compat_1_2,
pc_i440fx_1_0_machine_options);
#define PC_COMPAT_0_15 \
PC_CPU_MODEL_IDS("0.15")
static void pc_i440fx_0_15_machine_options(MachineClass *m)
{
pc_i440fx_1_0_machine_options(m);
m->hw_version = "0.15";
SET_MACHINE_COMPAT(m, PC_COMPAT_0_15);
}
DEFINE_I440FX_MACHINE(v0_15, "pc-0.15", pc_compat_1_2,
@@ -733,6 +741,7 @@ DEFINE_I440FX_MACHINE(v0_15, "pc-0.15", pc_compat_1_2,
#define PC_COMPAT_0_14 \
PC_CPU_MODEL_IDS("0.14") \
{\
.driver = "virtio-blk-pci",\
.property = "event_idx",\
@@ -771,6 +780,7 @@ DEFINE_I440FX_MACHINE(v0_14, "pc-0.14", pc_compat_1_2,
#define PC_COMPAT_0_13 \
PC_CPU_MODEL_IDS("0.13") \
{\
.driver = TYPE_PCI_DEVICE,\
.property = "command_serr_enable",\
@@ -807,6 +817,7 @@ DEFINE_I440FX_MACHINE(v0_13, "pc-0.13", pc_compat_0_13,
#define PC_COMPAT_0_12 \
PC_CPU_MODEL_IDS("0.12") \
{\
.driver = "virtio-serial-pci",\
.property = "max_ports",\
@@ -841,6 +852,7 @@ DEFINE_I440FX_MACHINE(v0_12, "pc-0.12", pc_compat_0_13,
#define PC_COMPAT_0_11 \
PC_CPU_MODEL_IDS("0.11") \
{\
.driver = "virtio-blk-pci",\
.property = "vectors",\
@@ -871,6 +883,7 @@ DEFINE_I440FX_MACHINE(v0_11, "pc-0.11", pc_compat_0_13,
#define PC_COMPAT_0_10 \
PC_CPU_MODEL_IDS("0.10") \
{\
.driver = "virtio-blk-pci",\
.property = "class",\
include/hw/i386/pc.h
+29
View File
@@ -359,8 +359,29 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
#define PC_COMPAT_2_5 \
HW_COMPAT_2_5
/* Helper for setting model-id for CPU models that changed model-id
* depending on QEMU versions up to QEMU 2.4.
*/
#define PC_CPU_MODEL_IDS(v) \
{\
.driver = "qemu32-" TYPE_X86_CPU,\
.property = "model-id",\
.value = "QEMU Virtual CPU version " v,\
},\
{\
.driver = "qemu64-" TYPE_X86_CPU,\
.property = "model-id",\
.value = "QEMU Virtual CPU version " v,\
},\
{\
.driver = "athlon-" TYPE_X86_CPU,\
.property = "model-id",\
.value = "QEMU Virtual CPU version " v,\
},
#define PC_COMPAT_2_4 \
HW_COMPAT_2_4 \
PC_CPU_MODEL_IDS("2.4.0") \
{\
.driver = "Haswell-" TYPE_X86_CPU,\
.property = "abm",\
@@ -431,6 +452,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
#define PC_COMPAT_2_3 \
HW_COMPAT_2_3 \
PC_CPU_MODEL_IDS("2.3.0") \
{\
.driver = TYPE_X86_CPU,\
.property = "arat",\
@@ -511,6 +533,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
#define PC_COMPAT_2_2 \
HW_COMPAT_2_2 \
PC_CPU_MODEL_IDS("2.3.0") \
{\
.driver = "kvm64" "-" TYPE_X86_CPU,\
.property = "vme",\
@@ -604,6 +627,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
#define PC_COMPAT_2_1 \
HW_COMPAT_2_1 \
PC_CPU_MODEL_IDS("2.1.0") \
{\
.driver = "coreduo" "-" TYPE_X86_CPU,\
.property = "vmx",\
@@ -616,6 +640,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
},
#define PC_COMPAT_2_0 \
PC_CPU_MODEL_IDS("2.0.0") \
{\
.driver = "virtio-scsi-pci",\
.property = "any_layout",\
@@ -675,6 +700,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
},
#define PC_COMPAT_1_7 \
PC_CPU_MODEL_IDS("1.7.0") \
{\
.driver = TYPE_USB_DEVICE,\
.property = "msos-desc",\
@@ -692,6 +718,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
},
#define PC_COMPAT_1_6 \
PC_CPU_MODEL_IDS("1.6.0") \
{\
.driver = "e1000",\
.property = "mitigation",\
@@ -715,6 +742,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
},
#define PC_COMPAT_1_5 \
PC_CPU_MODEL_IDS("1.5.0") \
{\
.driver = "Conroe-" TYPE_X86_CPU,\
.property = "model",\
@@ -758,6 +786,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
},
#define PC_COMPAT_1_4 \
PC_CPU_MODEL_IDS("1.4.0") \
{\
.driver = "scsi-hd",\
.property = "discard_granularity",\
include/qemu/osdep.h
+9
View File
@@ -327,6 +327,15 @@ static inline void qemu_timersub(const struct timeval *val1,
void qemu_set_cloexec(int fd);
/* Starting on QEMU 2.5, qemu_hw_version() returns "2.5+" by default
* instead of QEMU_VERSION, so setting hw_version on MachineClass
* is no longer mandatory.
*
* Do NOT change this string, or it will break compatibility on all
* machine classes that don't set hw_version.
*/
#define QEMU_HW_VERSION "2.5+"
/* QEMU "hardware version" setting. Used to replace code that exposed
* QEMU_VERSION to guests in the past and need to keep compatibility.
* Do not use qemu_hw_version() in new code.
include/sysemu/arch_init.h
-1
View File
@@ -30,7 +30,6 @@ extern const uint32_t arch_type;
void select_soundhw(const char *optarg);
void do_acpitable_option(const QemuOpts *opts);
void do_smbios_option(QemuOpts *opts);
void cpudef_init(void);
void audio_init(void);
int kvm_available(void);
int xen_available(void);
linux-user/main.c
-3
View File
@@ -4154,9 +4154,6 @@ int main(int argc, char **argv, char **envp)
}
cpu_model = NULL;
#if defined(cpudef_setup)
cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
#endif
srand(time(NULL));
target-i386/cpu.c
+23 -39
View File
@@ -474,25 +474,32 @@ static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
const ExtSaveArea x86_ext_save_areas[] = {
[XSTATE_YMM_BIT] =
{ .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
.offset = 0x240, .size = 0x100 },
.offset = offsetof(X86XSaveArea, avx_state),
.size = sizeof(XSaveAVX) },
[XSTATE_BNDREGS_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
.offset = 0x3c0, .size = 0x40 },
.offset = offsetof(X86XSaveArea, bndreg_state),
.size = sizeof(XSaveBNDREG) },
[XSTATE_BNDCSR_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
.offset = 0x400, .size = 0x40 },
.offset = offsetof(X86XSaveArea, bndcsr_state),
.size = sizeof(XSaveBNDCSR) },
[XSTATE_OPMASK_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
.offset = 0x440, .size = 0x40 },
.offset = offsetof(X86XSaveArea, opmask_state),
.size = sizeof(XSaveOpmask) },
[XSTATE_ZMM_Hi256_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
.offset = 0x480, .size = 0x200 },
.offset = offsetof(X86XSaveArea, zmm_hi256_state),
.size = sizeof(XSaveZMM_Hi256) },
[XSTATE_Hi16_ZMM_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
.offset = 0x680, .size = 0x400 },
.offset = offsetof(X86XSaveArea, hi16_zmm_state),
.size = sizeof(XSaveHi16_ZMM) },
[XSTATE_PKRU_BIT] =
{ .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
.offset = 0xA80, .size = 0x8 },
.offset = offsetof(X86XSaveArea, pkru_state),
.size = sizeof(XSavePKRU) },
};
const char *get_register_name_32(unsigned int reg)
@@ -703,6 +710,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
.xlevel = 0x8000000A,
.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
},
{
.name = "phenom",
@@ -799,6 +807,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3,
.xlevel = 0x80000004,
.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
},
{
.name = "kvm32",
@@ -895,6 +904,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
.xlevel = 0x80000008,
.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
},
{
.name = "n270",
@@ -2264,30 +2274,6 @@ void cpu_clear_apic_feature(CPUX86State *env)
#endif /* !CONFIG_USER_ONLY */
/* Initialize list of CPU models, filling some non-static fields if necessary
*/
void x86_cpudef_setup(void)
{
int i, j;
static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
X86CPUDefinition *def = &builtin_x86_defs[i];
/* Look for specific "cpudef" models that */
/* have the QEMU version in .model_id */
for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
if (strcmp(model_with_versions[j], def->name) == 0) {
pstrcpy(def->model_id, sizeof(def->model_id),
"QEMU Virtual CPU version ");
pstrcat(def->model_id, sizeof(def->model_id),
qemu_hw_version());
break;
}
}
}
}
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
@@ -2916,6 +2902,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_exec_init(cs, &error_abort);
if (tcg_enabled()) {
tcg_x86_init();
}
#ifndef CONFIG_USER_ONLY
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
@@ -3102,10 +3094,8 @@ static void x86_cpu_initfn(Object *obj)
X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
CPUX86State *env = &cpu->env;
FeatureWord w;
static int inited;
cs->env_ptr = env;
cpu_exec_init(cs, &error_abort);
object_property_add(obj, "family", "int",
x86_cpuid_version_get_family,
@@ -3151,12 +3141,6 @@ static void x86_cpu_initfn(Object *obj)
}
x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
/* init various static tables used in TCG mode */
if (tcg_enabled() && !inited) {
inited = 1;
tcg_x86_init();
}
}
static int64_t x86_cpu_get_arch_id(CPUState *cs)
target-i386/cpu.h
+99 -2
View File
@@ -830,6 +830,101 @@ typedef struct {
#define NB_OPMASK_REGS 8
typedef union X86LegacyXSaveArea {
struct {
uint16_t fcw;
uint16_t fsw;
uint8_t ftw;
uint8_t reserved;
uint16_t fpop;
uint64_t fpip;
uint64_t fpdp;
uint32_t mxcsr;
uint32_t mxcsr_mask;
FPReg fpregs[8];
uint8_t xmm_regs[16][16];
};
uint8_t data[512];
} X86LegacyXSaveArea;
typedef struct X86XSaveHeader {
uint64_t xstate_bv;
uint64_t xcomp_bv;
uint8_t reserved[48];
} X86XSaveHeader;
/* Ext. save area 2: AVX State */
typedef struct XSaveAVX {
uint8_t ymmh[16][16];
} XSaveAVX;
/* Ext. save area 3: BNDREG */
typedef struct XSaveBNDREG {
BNDReg bnd_regs[4];
} XSaveBNDREG;
/* Ext. save area 4: BNDCSR */
typedef union XSaveBNDCSR {
BNDCSReg bndcsr;
uint8_t data[64];
} XSaveBNDCSR;
/* Ext. save area 5: Opmask */
typedef struct XSaveOpmask {
uint64_t opmask_regs[NB_OPMASK_REGS];
} XSaveOpmask;
/* Ext. save area 6: ZMM_Hi256 */
typedef struct XSaveZMM_Hi256 {
uint8_t zmm_hi256[16][32];
} XSaveZMM_Hi256;
/* Ext. save area 7: Hi16_ZMM */
typedef struct XSaveHi16_ZMM {
uint8_t hi16_zmm[16][64];
} XSaveHi16_ZMM;
/* Ext. save area 9: PKRU state */
typedef struct XSavePKRU {
uint32_t pkru;
uint32_t padding;
} XSavePKRU;
typedef struct X86XSaveArea {
X86LegacyXSaveArea legacy;
X86XSaveHeader header;
/* Extended save areas: */
/* AVX State: */
XSaveAVX avx_state;
uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
/* MPX State: */
XSaveBNDREG bndreg_state;
XSaveBNDCSR bndcsr_state;
/* AVX-512 State: */
XSaveOpmask opmask_state;
XSaveZMM_Hi256 zmm_hi256_state;
XSaveHi16_ZMM hi16_zmm_state;
/* PKRU State: */
XSavePKRU pkru_state;
} X86XSaveArea;
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
typedef enum TPRAccess {
TPR_ACCESS_READ,
TPR_ACCESS_WRITE,
@@ -1029,6 +1124,8 @@ typedef struct CPUX86State {
TPRAccess tpr_access_type;
} CPUX86State;
struct kvm_msrs;
/**
* X86CPU:
* @env: #CPUX86State
@@ -1081,6 +1178,8 @@ struct X86CPU {
struct DeviceState *apic_state;
struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
Notifier machine_done;
struct kvm_msrs *kvm_msr_buf;
};
static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
@@ -1130,7 +1229,6 @@ X86CPU *cpu_x86_init(const char *cpu_model);
X86CPU *cpu_x86_create(const char *cpu_model, Error **errp);
int cpu_x86_exec(CPUState *cpu);
void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void x86_cpudef_setup(void);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
int cpu_get_pic_interrupt(CPUX86State *s);
@@ -1308,7 +1406,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define cpu_exec cpu_x86_exec
#define cpu_signal_handler cpu_x86_signal_handler
#define cpu_list x86_cpu_list
#define cpudef_setup x86_cpudef_setup
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _ksmap
target-i386/kvm.c
+220 -229
View File
File diff suppressed because it is too large Load Diff
target-i386/translate.c
+6
View File
@@ -8144,6 +8144,12 @@ void tcg_x86_init(void)
"bnd0_ub", "bnd1_ub", "bnd2_ub", "bnd3_ub"
};
int i;
static bool initialized;
if (initialized) {
return;
}
initialized = true;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
util/osdep.c
+1 -8
View File
@@ -44,14 +44,7 @@ extern int madvise(caddr_t, size_t, int);
static bool fips_enabled = false;
/* Starting on QEMU 2.5, qemu_hw_version() returns "2.5+" by default
* instead of QEMU_VERSION, so setting hw_version on MachineClass
* is no longer mandatory.
*
* Do NOT change this string, or it will break compatibility on all
* machine classes that don't set hw_version.
*/
static const char *hw_version = "2.5+";
static const char *hw_version = QEMU_HW_VERSION;
int socket_set_cork(int fd, int v)
{
vl.c
-7
View File
@@ -4047,13 +4047,6 @@ int main(int argc, char **argv, char **envp)
qemu_set_hw_version(machine_class->hw_version);
}
/* Init CPU def lists, based on config
* - Must be called after all the qemu_read_config_file() calls
* - Must be called before list_cpus()
* - Must be called before machine_class->init()
*/
cpudef_init();
if (cpu_model && is_help_option(cpu_model)) {
list_cpus(stdout, &fprintf, cpu_model);
exit(0);