mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
SHIX board emulation (Samuel Tardieu)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1862 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
@@ -6,6 +6,7 @@ version 0.8.1:
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- IDE LBA48 support (Jens Axboe)
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- SSE3 support
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- Solaris port (Ben Taylor)
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- Preliminary SH4 target (Samuel Tardieu)
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version 0.8.0:
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+3
-3
@@ -476,10 +476,10 @@ ifeq ($(TARGET_ARCH), sh4)
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op.o: op.c op_mem.c cpu.h
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op_helper.o: op_helper.c exec.h cpu.h
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helper.o: helper.c exec.h cpu.h
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sh7750.o: sh7750.c sh7750.h sh7750_regs.h sh7750_regnames.h cpu.h
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shix.o: shix.c sh7750.h sh7750_regs.h sh7750_regnames.h tc58128.h
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sh7750.o: sh7750.c sh7750_regs.h sh7750_regnames.h cpu.h
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shix.o: shix.c sh7750_regs.h sh7750_regnames.h
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sh7750_regnames.o: sh7750_regnames.c sh7750_regnames.h sh7750_regs.h
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tc58128.o: tc58128.c tc58128.h sh7750.h
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tc58128.o: tc58128.c
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endif
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%.o: %.c
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+836
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,128 @@
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#include "vl.h"
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#include "sh7750_regs.h"
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#define REGNAME(r) {r, #r},
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typedef struct {
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uint32_t regaddr;
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const char *regname;
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} regname_t;
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static regname_t regnames[] = {
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REGNAME(SH7750_PTEH_A7)
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REGNAME(SH7750_PTEL_A7)
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REGNAME(SH7750_PTEA_A7)
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REGNAME(SH7750_TTB_A7)
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REGNAME(SH7750_TEA_A7)
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REGNAME(SH7750_MMUCR_A7)
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REGNAME(SH7750_CCR_A7)
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REGNAME(SH7750_QACR0_A7)
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REGNAME(SH7750_QACR1_A7)
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REGNAME(SH7750_TRA_A7)
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REGNAME(SH7750_EXPEVT_A7)
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REGNAME(SH7750_INTEVT_A7)
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REGNAME(SH7750_STBCR_A7)
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REGNAME(SH7750_STBCR2_A7)
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REGNAME(SH7750_FRQCR_A7)
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REGNAME(SH7750_WTCNT_A7)
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REGNAME(SH7750_WTCSR_A7)
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REGNAME(SH7750_R64CNT_A7)
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REGNAME(SH7750_RSECCNT_A7)
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REGNAME(SH7750_RMINCNT_A7)
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REGNAME(SH7750_RHRCNT_A7)
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REGNAME(SH7750_RWKCNT_A7)
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REGNAME(SH7750_RDAYCNT_A7)
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REGNAME(SH7750_RMONCNT_A7)
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REGNAME(SH7750_RYRCNT_A7)
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REGNAME(SH7750_RSECAR_A7)
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REGNAME(SH7750_RMINAR_A7)
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REGNAME(SH7750_RHRAR_A7)
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REGNAME(SH7750_RWKAR_A7)
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REGNAME(SH7750_RDAYAR_A7)
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REGNAME(SH7750_RMONAR_A7)
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REGNAME(SH7750_RCR1_A7)
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REGNAME(SH7750_RCR2_A7)
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REGNAME(SH7750_TOCR_A7)
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REGNAME(SH7750_TSTR_A7)
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REGNAME(SH7750_TCOR0_A7)
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REGNAME(SH7750_TCOR1_A7)
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REGNAME(SH7750_TCOR2_A7)
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REGNAME(SH7750_TCNT0_A7)
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REGNAME(SH7750_TCNT1_A7)
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REGNAME(SH7750_TCNT2_A7)
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REGNAME(SH7750_TCR0_A7)
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REGNAME(SH7750_TCR1_A7)
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REGNAME(SH7750_TCR2_A7)
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REGNAME(SH7750_TCPR2_A7)
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REGNAME(SH7750_BCR1_A7)
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REGNAME(SH7750_BCR2_A7)
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REGNAME(SH7750_WCR1_A7)
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REGNAME(SH7750_WCR2_A7)
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REGNAME(SH7750_WCR3_A7)
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REGNAME(SH7750_MCR_A7)
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REGNAME(SH7750_PCR_A7)
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REGNAME(SH7750_RTCSR_A7)
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REGNAME(SH7750_RTCNT_A7)
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REGNAME(SH7750_RTCOR_A7)
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REGNAME(SH7750_RFCR_A7)
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REGNAME(SH7750_SAR0_A7)
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REGNAME(SH7750_SAR1_A7)
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REGNAME(SH7750_SAR2_A7)
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REGNAME(SH7750_SAR3_A7)
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REGNAME(SH7750_DAR0_A7)
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REGNAME(SH7750_DAR1_A7)
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REGNAME(SH7750_DAR2_A7)
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REGNAME(SH7750_DAR3_A7)
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REGNAME(SH7750_DMATCR0_A7)
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REGNAME(SH7750_DMATCR1_A7)
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REGNAME(SH7750_DMATCR2_A7)
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REGNAME(SH7750_DMATCR3_A7)
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REGNAME(SH7750_CHCR0_A7)
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REGNAME(SH7750_CHCR1_A7)
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REGNAME(SH7750_CHCR2_A7)
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REGNAME(SH7750_CHCR3_A7)
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REGNAME(SH7750_DMAOR_A7)
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REGNAME(SH7750_SCRDR1_A7)
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REGNAME(SH7750_SCRDR2_A7)
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REGNAME(SH7750_SCTDR1_A7)
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REGNAME(SH7750_SCTDR2_A7)
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REGNAME(SH7750_SCSMR1_A7)
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REGNAME(SH7750_SCSMR2_A7)
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REGNAME(SH7750_SCSCR1_A7)
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REGNAME(SH7750_SCSCR2_A7)
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REGNAME(SH7750_SCSSR1_A7)
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REGNAME(SH7750_SCSFR2_A7)
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REGNAME(SH7750_SCSPTR1_A7)
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REGNAME(SH7750_SCSPTR2_A7)
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REGNAME(SH7750_SCBRR1_A7)
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REGNAME(SH7750_SCBRR2_A7)
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REGNAME(SH7750_SCFCR2_A7)
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REGNAME(SH7750_SCFDR2_A7)
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REGNAME(SH7750_SCLSR2_A7)
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REGNAME(SH7750_SCSCMR1_A7)
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REGNAME(SH7750_PCTRA_A7)
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REGNAME(SH7750_PDTRA_A7)
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REGNAME(SH7750_PCTRB_A7)
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REGNAME(SH7750_PDTRB_A7)
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REGNAME(SH7750_GPIOIC_A7)
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REGNAME(SH7750_ICR_A7)
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REGNAME(SH7750_IPRA_A7)
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REGNAME(SH7750_IPRB_A7)
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REGNAME(SH7750_IPRC_A7)
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REGNAME(SH7750_BCR3_A7)
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REGNAME(SH7750_BCR4_A7)
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REGNAME(SH7750_PRECHARGE0_A7)
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REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
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};
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const char *regname(uint32_t addr)
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{
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unsigned int i;
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for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) {
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if (regnames[i].regaddr == addr)
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return regnames[i].regname;
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}
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return "<unknown reg>";
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}
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@@ -0,0 +1,6 @@
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#ifndef _SH7750_REGNAMES_H
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#define _SH7750_REGNAMES_H
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const char *regname(uint32_t addr);
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#endif /* _SH7750_REGNAMES_H */
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+1623
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,111 @@
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/*
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* SHIX 2.0 board description
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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Shix 2.0 board by Alexis Polti, described at
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http://perso.enst.fr/~polti/realisations/shix20/
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More information in target-sh4/README.sh4
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*/
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#include "vl.h"
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#define BIOS_FILENAME "shix_bios.bin"
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#define BIOS_ADDRESS 0xA0000000
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void DMA_run(void)
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{
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/* XXXXX */
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}
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void irq_info(void)
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{
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/* XXXXX */
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}
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void pic_set_irq(int irq, int level)
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{
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/* XXXXX */
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}
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void pic_info()
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{
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/* XXXXX */
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}
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void vga_update_display()
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{
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/* XXXXX */
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}
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void vga_invalidate_display()
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{
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/* XXXXX */
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}
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void vga_screen_dump(const char *filename)
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{
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/* XXXXX */
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}
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void shix_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState * ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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int ret;
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CPUState *env;
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struct SH7750State *s;
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printf("Initializing CPU\n");
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env = cpu_init();
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/* Allocate memory space */
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printf("Allocating ROM\n");
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cpu_register_physical_memory(0x00000000, 0x00004000, IO_MEM_ROM);
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printf("Allocating SDRAM 1\n");
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cpu_register_physical_memory(0x08000000, 0x01000000, 0x00004000);
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printf("Allocating SDRAM 2\n");
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cpu_register_physical_memory(0x0c000000, 0x01000000, 0x01004000);
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/* Load BIOS in 0 (and access it through P2, 0xA0000000) */
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printf("%s: load BIOS '%s'\n", __func__, BIOS_FILENAME);
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ret = load_image(BIOS_FILENAME, phys_ram_base);
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if (ret < 0) { /* Check bios size */
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fprintf(stderr, "ret=%d\n", ret);
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fprintf(stderr, "qemu: could not load SHIX bios '%s'\n",
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BIOS_FILENAME);
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exit(1);
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}
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/* Register peripherals */
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s = sh7750_init(env);
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/* XXXXX Check success */
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tc58128_init(s, "shix_linux_nand.bin", NULL);
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fprintf(stderr, "initialization terminated\n");
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}
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QEMUMachine shix_machine = {
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"shix",
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"shix card",
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shix_init
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};
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+181
@@ -0,0 +1,181 @@
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#include <assert.h>
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#include "vl.h"
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#define CE1 0x0100
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#define CE2 0x0200
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#define RE 0x0400
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#define WE 0x0800
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#define ALE 0x1000
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#define CLE 0x2000
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#define RDY1 0x4000
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#define RDY2 0x8000
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#define RDY(n) ((n) == 0 ? RDY1 : RDY2)
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typedef enum { WAIT, READ1, READ2, READ3 } state_t;
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typedef struct {
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uint8_t *flash_contents;
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state_t state;
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uint32_t address;
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uint8_t address_cycle;
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} tc58128_dev;
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static tc58128_dev tc58128_devs[2];
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#define FLASH_SIZE (16*1024*1024)
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void init_dev(tc58128_dev * dev, char *filename)
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{
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int ret, blocks;
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dev->state = WAIT;
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dev->flash_contents = qemu_mallocz(FLASH_SIZE);
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memset(dev->flash_contents, 0xff, FLASH_SIZE);
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if (!dev->flash_contents) {
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fprintf(stderr, "could not alloc memory for flash\n");
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exit(1);
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}
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if (filename) {
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/* Load flash image skipping the first block */
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ret = load_image(filename, dev->flash_contents + 528 * 32);
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if (ret < 0) {
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fprintf(stderr, "ret=%d\n", ret);
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fprintf(stderr, "qemu: could not load flash image %s\n",
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filename);
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exit(1);
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} else {
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/* Build first block with number of blocks */
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blocks = (ret + 528 * 32 - 1) / (528 * 32);
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dev->flash_contents[0] = blocks & 0xff;
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dev->flash_contents[1] = (blocks >> 8) & 0xff;
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dev->flash_contents[2] = (blocks >> 16) & 0xff;
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dev->flash_contents[3] = (blocks >> 24) & 0xff;
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fprintf(stderr, "loaded %d bytes for %s into flash\n", ret,
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filename);
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}
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}
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}
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void handle_command(tc58128_dev * dev, uint8_t command)
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{
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switch (command) {
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case 0xff:
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fprintf(stderr, "reset flash device\n");
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dev->state = WAIT;
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break;
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case 0x00:
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fprintf(stderr, "read mode 1\n");
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dev->state = READ1;
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dev->address_cycle = 0;
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break;
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case 0x01:
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fprintf(stderr, "read mode 2\n");
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dev->state = READ2;
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dev->address_cycle = 0;
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break;
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case 0x50:
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fprintf(stderr, "read mode 3\n");
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dev->state = READ3;
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dev->address_cycle = 0;
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break;
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default:
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fprintf(stderr, "unknown flash command 0x%02x\n", command);
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assert(0);
|
||||
}
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}
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||||
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||||
void handle_address(tc58128_dev * dev, uint8_t data)
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||||
{
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||||
switch (dev->state) {
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case READ1:
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||||
case READ2:
|
||||
case READ3:
|
||||
switch (dev->address_cycle) {
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case 0:
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dev->address = data;
|
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if (dev->state == READ2)
|
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dev->address |= 0x100;
|
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else if (dev->state == READ3)
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dev->address |= 0x200;
|
||||
break;
|
||||
case 1:
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dev->address += data * 528 * 0x100;
|
||||
break;
|
||||
case 2:
|
||||
dev->address += data * 528;
|
||||
fprintf(stderr, "address pointer in flash: 0x%08x\n",
|
||||
dev->address);
|
||||
break;
|
||||
default:
|
||||
/* Invalid data */
|
||||
assert(0);
|
||||
}
|
||||
dev->address_cycle++;
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t handle_read(tc58128_dev * dev)
|
||||
{
|
||||
#if 0
|
||||
if (dev->address % 0x100000 == 0)
|
||||
fprintf(stderr, "reading flash at address 0x%08x\n", dev->address);
|
||||
#endif
|
||||
return dev->flash_contents[dev->address++];
|
||||
}
|
||||
|
||||
/* We never mark the device as busy, so interrupts cannot be triggered
|
||||
XXXXX */
|
||||
|
||||
int tc58128_cb(uint16_t porta, uint16_t portb,
|
||||
uint16_t * periph_pdtra, uint16_t * periph_portadir,
|
||||
uint16_t * periph_pdtrb, uint16_t * periph_portbdir)
|
||||
{
|
||||
int dev;
|
||||
|
||||
if ((porta & CE1) == 0)
|
||||
dev = 0;
|
||||
else if ((porta & CE2) == 0)
|
||||
dev = 1;
|
||||
else
|
||||
return 0; /* No device selected */
|
||||
|
||||
if ((porta & RE) && (porta & WE)) {
|
||||
/* Nothing to do, assert ready and return to input state */
|
||||
*periph_portadir &= 0xff00;
|
||||
*periph_portadir |= RDY(dev);
|
||||
*periph_pdtra |= RDY(dev);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (porta & CLE) {
|
||||
/* Command */
|
||||
assert((porta & WE) == 0);
|
||||
handle_command(&tc58128_devs[dev], porta & 0x00ff);
|
||||
} else if (porta & ALE) {
|
||||
assert((porta & WE) == 0);
|
||||
handle_address(&tc58128_devs[dev], porta & 0x00ff);
|
||||
} else if ((porta & RE) == 0) {
|
||||
*periph_portadir |= 0x00ff;
|
||||
*periph_pdtra &= 0xff00;
|
||||
*periph_pdtra |= handle_read(&tc58128_devs[dev]);
|
||||
} else {
|
||||
assert(0);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static sh7750_io_device tc58128 = {
|
||||
RE | WE, /* Port A triggers */
|
||||
0, /* Port B triggers */
|
||||
tc58128_cb /* Callback */
|
||||
};
|
||||
|
||||
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2)
|
||||
{
|
||||
init_dev(&tc58128_devs[0], zone1);
|
||||
init_dev(&tc58128_devs[1], zone2);
|
||||
return sh7750_register_io_device(s, &tc58128);
|
||||
}
|
||||
@@ -0,0 +1,150 @@
|
||||
qemu target: sh4
|
||||
author: Samuel Tardieu <sam@rfc1149.net>
|
||||
last modified: Tue Dec 6 07:22:44 CET 2005
|
||||
|
||||
The sh4 target is not ready at all yet for integration in qemu. This
|
||||
file describes the current state of implementation.
|
||||
|
||||
Most places requiring attention and/or modification can be detected by
|
||||
looking for "XXXXX" or "assert (0)".
|
||||
|
||||
The sh4 core is located in target-sh4/*, while the 7750 peripheral
|
||||
features (IO ports for example) are located in hw/sh7750.[ch]. The
|
||||
main board description is in hw/shix.c, and the NAND flash in
|
||||
hw/tc58128.[ch].
|
||||
|
||||
All the shortcomings indicated here will eventually be resolved. This
|
||||
is a work in progress. Features are added in a semi-random order: if a
|
||||
point is blocking to progress on booting the Linux kernel for the shix
|
||||
board, it is addressed first; if feedback is necessary and no progress
|
||||
can be made on blocking points until it is received, a random feature
|
||||
is worked on.
|
||||
|
||||
Goals
|
||||
-----
|
||||
|
||||
The primary model being worked on is the soft MMU target to be able to
|
||||
emulate the Shix 2.0 board by Alexis Polti, described at
|
||||
http://perso.enst.fr/~polti/realisations/shix20/
|
||||
|
||||
Ultimately, qemu will be coupled with a system C or a verilog
|
||||
simulator to simulate the whole board functionalities.
|
||||
|
||||
A sh4 user-mode has also somewhat started but will be worked on
|
||||
afterwards. The goal is to automate tests for GNAT (GNU Ada) compiler
|
||||
that I ported recently to the sh4-linux target.
|
||||
|
||||
Registers
|
||||
---------
|
||||
|
||||
16 general purpose registers are available at any time. The first 8
|
||||
registers are banked and the non-directly visible ones can be accessed
|
||||
by privileged instructions. In qemu, we define 24 general purpose
|
||||
registers and the code generation use either [0-7]+[8-15] or
|
||||
[16-23]+[8-15] depending on the MD and RB flags in the sr
|
||||
configuration register.
|
||||
|
||||
Instructions
|
||||
------------
|
||||
|
||||
Most sh4 instructions have been implemented. The missing ones at this
|
||||
time are:
|
||||
- FPU related instructions
|
||||
- LDTLB to load a new MMU entry
|
||||
- SLEEP to put the processor in sleep mode
|
||||
|
||||
Most instructions could be optimized a lot. This will be worked on
|
||||
after the current model is fully functional unless debugging
|
||||
convenience requires that it is done early.
|
||||
|
||||
Many instructions did not have a chance to be tested yet. The plan is
|
||||
to implement unit and regression testing of those in the future.
|
||||
|
||||
MMU
|
||||
---
|
||||
|
||||
The MMU is implemented in the sh4 core. MMU management has not been
|
||||
tested at all yet. In the sh7750, it can be manipulated through memory
|
||||
mapped registers and this part has not yet been implemented.
|
||||
|
||||
Exceptions
|
||||
----------
|
||||
|
||||
Exceptions are implemented as described in the sh4 reference manual
|
||||
but have not been tested yet. They do not use qemu EXCP_ features
|
||||
yet.
|
||||
|
||||
IRQ
|
||||
---
|
||||
|
||||
IRQ are not implemented yet.
|
||||
|
||||
Peripheral features
|
||||
-------------------
|
||||
|
||||
+ Serial ports
|
||||
|
||||
Configuration and use of the first serial port (SCI) without
|
||||
interrupts is supported. Input has not yet been tested.
|
||||
|
||||
Configuration of the second serial port (SCIF) is supported. FIFO
|
||||
handling infrastructure has been started but is not completed yet.
|
||||
|
||||
+ GPIO ports
|
||||
|
||||
GPIO ports have been implemented. A registration function allows
|
||||
external modules to register interest in some port changes (see
|
||||
hw/tc58128.[ch] for an example) and will be called back. Interrupt
|
||||
generation is not yet supported but some infrastructure is in place
|
||||
for this purpose. Note that in the current model a peripheral module
|
||||
cannot directly simulate a H->L->H input port transition and have an
|
||||
interrupt generated on the low level.
|
||||
|
||||
+ TC58128 NAND flash
|
||||
|
||||
TC58128 NAND flash is partially implemented through GPIO ports. It
|
||||
supports reading from flash.
|
||||
|
||||
GDB
|
||||
---
|
||||
|
||||
GDB remote target support has been implemented and lightly tested.
|
||||
|
||||
Files
|
||||
-----
|
||||
|
||||
File names are harcoded at this time. The bootloader must be stored in
|
||||
shix_bios.bin in the current directory. The initial Linux image must
|
||||
be stored in shix_linux_nand.bin in the current directory in NAND
|
||||
format. Test files can be obtained from
|
||||
http://perso.enst.fr/~polti/robot/ as well as the various datasheets I
|
||||
use.
|
||||
|
||||
qemu disk parameter on the command line is unused. You can supply any
|
||||
existing image and it will be ignored. As the goal is to simulate an
|
||||
embedded target, it is not clear how this parameter will be handled in
|
||||
the future.
|
||||
|
||||
To build an ELF kernel image from the NAND image, 16 bytes have to be
|
||||
stripped off the end of every 528 bytes, keeping only 512 of them. The
|
||||
following Python code snippet does it:
|
||||
|
||||
#! /usr/bin/python
|
||||
|
||||
def denand (infd, outfd):
|
||||
while True:
|
||||
d = infd.read (528)
|
||||
if not d: return
|
||||
outfd.write (d[:512])
|
||||
|
||||
if __name__ == '__main__':
|
||||
import sys
|
||||
denand (open (sys.argv[1], 'rb'),
|
||||
open (sys.argv[2], 'wb'))
|
||||
|
||||
Style isssues
|
||||
-------------
|
||||
|
||||
There is currently a mix between my style (space before opening
|
||||
parenthesis) and qemu style. This will be resolved before final
|
||||
integration is proposed.
|
||||
@@ -4863,6 +4863,8 @@ void register_machines(void)
|
||||
qemu_register_machine(&integratorcp926_machine);
|
||||
qemu_register_machine(&integratorcp1026_machine);
|
||||
qemu_register_machine(&versatilepb_machine);
|
||||
#elif defined(TARGET_SH4)
|
||||
qemu_register_machine(&shix_machine);
|
||||
#else
|
||||
#error unsupported CPU
|
||||
#endif
|
||||
|
||||
@@ -842,6 +842,9 @@ extern QEMUMachine heathrow_machine;
|
||||
/* mips_r4k.c */
|
||||
extern QEMUMachine mips_machine;
|
||||
|
||||
/* shix.c */
|
||||
extern QEMUMachine shix_machine;
|
||||
|
||||
#ifdef TARGET_PPC
|
||||
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
|
||||
#endif
|
||||
@@ -1016,6 +1019,28 @@ void *pl190_init(uint32_t base, void *parent, int irq, int fiq);
|
||||
void sp804_init(uint32_t base, void *pic, int irq);
|
||||
void icp_pit_init(uint32_t base, void *pic, int irq);
|
||||
|
||||
/* sh7750.c */
|
||||
struct SH7750State;
|
||||
|
||||
struct SH7750State *sh7750_init(CPUSH4State * cpu);
|
||||
|
||||
typedef struct {
|
||||
/* The callback will be triggered if any of the designated lines change */
|
||||
uint16_t portamask_trigger;
|
||||
uint16_t portbmask_trigger;
|
||||
/* Return 0 if no action was taken */
|
||||
int (*port_change_cb) (uint16_t porta, uint16_t portb,
|
||||
uint16_t * periph_pdtra,
|
||||
uint16_t * periph_portdira,
|
||||
uint16_t * periph_pdtrb,
|
||||
uint16_t * periph_portdirb);
|
||||
} sh7750_io_device;
|
||||
|
||||
int sh7750_register_io_device(struct SH7750State *s,
|
||||
sh7750_io_device * device);
|
||||
/* tc58128.c */
|
||||
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
|
||||
|
||||
#endif /* defined(QEMU_TOOL) */
|
||||
|
||||
/* monitor.c */
|
||||
|
||||
Reference in New Issue
Block a user