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Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging

Browse Source 
accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/ patchset which eliminates tcg_const

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* tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu: (91 commits)
  tcg: Drop tcg_const_*
  tcg: Drop tcg_const_*_vec
  target/tricore: Use min/max for saturate
  target/ppc: Avoid tcg_const_* in translate.c
  target/ppc: Fix gen_tlbsx_booke206
  target/ppc: Rewrite trans_ADDG6S
  target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
  target/ppc: Avoid tcg_const_* in fp-impl.c.inc
  target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
  target/ppc: Avoid tcg_const_* in xxeval
  target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
  target/ppc: Avoid tcg_const_i64 in do_vcntmb
  target/m68k: Use tcg_constant_i32 in gen_ea_mode
  target/arm: Avoid tcg_const_ptr in handle_rev
  target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
  target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
  target/arm: Avoid tcg_const_* in translate-mve.c
  target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
  target/arm: Improve trans_BFCI
  target/arm: Create gen_set_rmode, gen_restore_rmode
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2023-03-14 10:09:15 +00:00
parent 5cfda4ce79 0c8b6b9a63
commit 27a03171d0
67 changed files with 1166 additions and 2388 deletions
Download Patch File Download Diff File Expand all files Collapse all files
accel/tcg/plugin-gen.c
+1
View File
@@ -44,6 +44,7 @@
*/
#include "qemu/osdep.h"
#include "tcg/tcg.h"
#include "tcg/tcg-temp-internal.h"
#include "tcg/tcg-op.h"
#include "exec/exec-all.h"
#include "exec/plugin-gen.h"
include/exec/cpu-defs.h
+6 -3
View File
@@ -36,9 +36,6 @@
#ifndef TARGET_LONG_BITS
# error TARGET_LONG_BITS must be defined in cpu-param.h
#endif
#ifndef NB_MMU_MODES
# error NB_MMU_MODES must be defined in cpu-param.h
#endif
#ifndef TARGET_PHYS_ADDR_SPACE_BITS
# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
#endif
@@ -57,6 +54,12 @@
#include "exec/target_long.h"
/*
* Fix the number of mmu modes to 16, which is also the maximum
* supported by the softmmu tlb api.
*/
#define NB_MMU_MODES 16
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* use a fully associative victim tlb of 8 entries */
include/tcg/tcg-op.h
-4
View File
@@ -1089,9 +1089,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_extract_tl tcg_gen_extract_i64
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
#define tcg_gen_extract2_tl tcg_gen_extract2_i64
#define tcg_const_tl tcg_const_i64
#define tcg_constant_tl tcg_constant_i64
#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
#define tcg_gen_add2_tl tcg_gen_add2_i64
#define tcg_gen_sub2_tl tcg_gen_sub2_i64
@@ -1205,9 +1203,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_extract_tl tcg_gen_extract_i32
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
#define tcg_gen_extract2_tl tcg_gen_extract2_i32
#define tcg_const_tl tcg_const_i32
#define tcg_constant_tl tcg_constant_i32
#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
#define tcg_gen_add2_tl tcg_gen_add2_i32
#define tcg_gen_sub2_tl tcg_gen_sub2_i32
include/tcg/tcg-temp-internal.h
+83
View File
@@ -0,0 +1,83 @@
/*
* TCG internals related to TCG temp allocation
*
* Copyright (c) 2008 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef TCG_TEMP_INTERNAL_H
#define TCG_TEMP_INTERNAL_H
/*
* Allocation and freeing of EBB temps is reserved to TCG internals
*/
void tcg_temp_free_internal(TCGTemp *);
static inline void tcg_temp_free_i32(TCGv_i32 arg)
{
tcg_temp_free_internal(tcgv_i32_temp(arg));
}
static inline void tcg_temp_free_i64(TCGv_i64 arg)
{
tcg_temp_free_internal(tcgv_i64_temp(arg));
}
static inline void tcg_temp_free_i128(TCGv_i128 arg)
{
tcg_temp_free_internal(tcgv_i128_temp(arg));
}
static inline void tcg_temp_free_ptr(TCGv_ptr arg)
{
tcg_temp_free_internal(tcgv_ptr_temp(arg));
}
static inline void tcg_temp_free_vec(TCGv_vec arg)
{
tcg_temp_free_internal(tcgv_vec_temp(arg));
}
static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
return temp_tcgv_i32(t);
}
static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
return temp_tcgv_i64(t);
}
static inline TCGv_i128 tcg_temp_ebb_new_i128(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB);
return temp_tcgv_i128(t);
}
static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
return temp_tcgv_ptr(t);
}
#endif /* TCG_TEMP_FREE_H */
include/tcg/tcg.h
-64
View File
@@ -862,35 +862,9 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
intptr_t, const char *);
TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind);
void tcg_temp_free_internal(TCGTemp *);
TCGv_vec tcg_temp_new_vec(TCGType type);
TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
static inline void tcg_temp_free_i32(TCGv_i32 arg)
{
tcg_temp_free_internal(tcgv_i32_temp(arg));
}
static inline void tcg_temp_free_i64(TCGv_i64 arg)
{
tcg_temp_free_internal(tcgv_i64_temp(arg));
}
static inline void tcg_temp_free_i128(TCGv_i128 arg)
{
tcg_temp_free_internal(tcgv_i128_temp(arg));
}
static inline void tcg_temp_free_ptr(TCGv_ptr arg)
{
tcg_temp_free_internal(tcgv_ptr_temp(arg));
}
static inline void tcg_temp_free_vec(TCGv_vec arg)
{
tcg_temp_free_internal(tcgv_vec_temp(arg));
}
static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
const char *name)
{
@@ -898,13 +872,6 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_i32(t);
}
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
return temp_tcgv_i32(t);
}
static inline TCGv_i32 tcg_temp_new_i32(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB);
@@ -918,26 +885,12 @@ static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_i64(t);
}
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
return temp_tcgv_i64(t);
}
static inline TCGv_i64 tcg_temp_new_i64(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB);
return temp_tcgv_i64(t);
}
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_i128 tcg_temp_ebb_new_i128(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB);
return temp_tcgv_i128(t);
}
static inline TCGv_i128 tcg_temp_new_i128(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB);
@@ -951,13 +904,6 @@ static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_ptr(t);
}
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
return temp_tcgv_ptr(t);
}
static inline TCGv_ptr tcg_temp_new_ptr(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB);
@@ -1050,14 +996,6 @@ void tcg_remove_ops_after(TCGOp *op);
void tcg_optimize(TCGContext *s);
/* Allocate a new temporary and initialize it with a constant. */
TCGv_i32 tcg_const_i32(int32_t val);
TCGv_i64 tcg_const_i64(int64_t val);
TCGv_vec tcg_const_zeros_vec(TCGType);
TCGv_vec tcg_const_ones_vec(TCGType);
TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
/*
* Locate or create a read-only temporary that is a constant.
* This kind of temporary need not be freed, but for convenience
@@ -1079,10 +1017,8 @@ TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
#if UINTPTR_MAX == UINT32_MAX
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x)))
#else
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x)))
#endif
target/alpha/cpu-param.h
-2
View File
@@ -15,6 +15,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 44
#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
#define NB_MMU_MODES 3
#endif
target/arm/cpu-param.h
-2
View File
@@ -45,6 +45,4 @@
bool guarded;
#endif
#define NB_MMU_MODES 12
#endif
target/arm/internals.h
+9 -3
View File
@@ -193,16 +193,22 @@ void arm_restore_state_to_opc(CPUState *cs,
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
#endif /* CONFIG_TCG */
enum arm_fprounding {
typedef enum ARMFPRounding {
FPROUNDING_TIEEVEN,
FPROUNDING_POSINF,
FPROUNDING_NEGINF,
FPROUNDING_ZERO,
FPROUNDING_TIEAWAY,
FPROUNDING_ODD
};
} ARMFPRounding;
int arm_rmode_to_sf(int rmode);
extern const FloatRoundMode arm_rmode_to_sf_map[6];
static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
{
assert((unsigned)rmode < ARRAY_SIZE(arm_rmode_to_sf_map));
return arm_rmode_to_sf_map[rmode];
}
static inline void aarch64_save_sp(CPUARMState *env, int el)
{
target/arm/tcg/translate-a64.c
+73 -95
View File
@@ -6146,13 +6146,12 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
{
TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
TCGv_i32 tcg_rmode;
fpst = fpstatus_ptr(FPST_FPCR_F16);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(opcode & 7, fpst);
gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
break;
}
case 0xe: /* FRINTX */
@@ -6202,7 +6201,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
case 0xa: /* FRINTM */
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
rmode = arm_rmode_to_sf(opcode & 7);
rmode = opcode & 7;
gen_fpst = gen_helper_rints;
break;
case 0xe: /* FRINTX */
@@ -6212,14 +6211,14 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_rints;
break;
case 0x10: /* FRINT32Z */
rmode = float_round_to_zero;
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_s;
break;
case 0x11: /* FRINT32X */
gen_fpst = gen_helper_frint32_s;
break;
case 0x12: /* FRINT64Z */
rmode = float_round_to_zero;
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint64_s;
break;
case 0x13: /* FRINT64X */
@@ -6231,10 +6230,9 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@@ -6275,7 +6273,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
case 0xa: /* FRINTM */
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
rmode = arm_rmode_to_sf(opcode & 7);
rmode = opcode & 7;
gen_fpst = gen_helper_rintd;
break;
case 0xe: /* FRINTX */
@@ -6285,14 +6283,14 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_rintd;
break;
case 0x10: /* FRINT32Z */
rmode = float_round_to_zero;
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_d;
break;
case 0x11: /* FRINT32X */
gen_fpst = gen_helper_frint32_d;
break;
case 0x12: /* FRINT64Z */
rmode = float_round_to_zero;
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint64_d;
break;
case 0x13: /* FRINT64X */
@@ -6304,10 +6302,9 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@@ -6944,9 +6941,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
rmode = FPROUNDING_TIEAWAY;
}
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
switch (type) {
case 1: /* float64 */
@@ -7023,7 +7018,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
g_assert_not_reached();
}
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -7447,10 +7442,10 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
bool part = extract32(insn, 14, 1);
bool is_q = extract32(insn, 30, 1);
int esize = 8 << size;
int i, ofs;
int i;
int datasize = is_q ? 128 : 64;
int elements = datasize / esize;
TCGv_i64 tcg_res, tcg_resl, tcg_resh;
TCGv_i64 tcg_res[2], tcg_ele;
if (opcode == 0 || (size == 3 && !is_q)) {
unallocated_encoding(s);
@@ -7461,37 +7456,39 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
return;
}
tcg_resl = tcg_const_i64(0);
tcg_resh = is_q ? tcg_const_i64(0) : NULL;
tcg_res = tcg_temp_new_i64();
tcg_res[0] = tcg_temp_new_i64();
tcg_res[1] = is_q ? tcg_temp_new_i64() : NULL;
tcg_ele = tcg_temp_new_i64();
for (i = 0; i < elements; i++) {
int o, w;
switch (opcode) {
case 1: /* UZP1/2 */
{
int midpoint = elements / 2;
if (i < midpoint) {
read_vec_element(s, tcg_res, rn, 2 * i + part, size);
read_vec_element(s, tcg_ele, rn, 2 * i + part, size);
} else {
read_vec_element(s, tcg_res, rm,
read_vec_element(s, tcg_ele, rm,
2 * (i - midpoint) + part, size);
}
break;
}
case 2: /* TRN1/2 */
if (i & 1) {
read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
read_vec_element(s, tcg_ele, rm, (i & ~1) + part, size);
} else {
read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
read_vec_element(s, tcg_ele, rn, (i & ~1) + part, size);
}
break;
case 3: /* ZIP1/2 */
{
int base = part * elements / 2;
if (i & 1) {
read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
read_vec_element(s, tcg_ele, rm, base + (i >> 1), size);
} else {
read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
read_vec_element(s, tcg_ele, rn, base + (i >> 1), size);
}
break;
}
@@ -7499,19 +7496,18 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
g_assert_not_reached();
}
ofs = i * esize;
if (ofs < 64) {
tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
w = (i * esize) / 64;
o = (i * esize) % 64;
if (o == 0) {
tcg_gen_mov_i64(tcg_res[w], tcg_ele);
} else {
tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
tcg_gen_shli_i64(tcg_ele, tcg_ele, o);
tcg_gen_or_i64(tcg_res[w], tcg_res[w], tcg_ele);
}
}
write_vec_element(s, tcg_resl, rd, 0, MO_64);
if (is_q) {
write_vec_element(s, tcg_resh, rd, 1, MO_64);
for (i = 0; i <= is_q; ++i) {
write_vec_element(s, tcg_res[i], rd, i, MO_64);
}
clear_vec_high(s, is_q, rd);
}
@@ -8463,7 +8459,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
tcg_rn = tcg_temp_new_i64();
tcg_rd = tcg_temp_new_i64();
tcg_rd_narrowed = tcg_temp_new_i32();
tcg_final = tcg_const_i64(0);
tcg_final = tcg_temp_new_i64();
if (round) {
tcg_round = tcg_constant_i64(1ULL << (shift - 1));
@@ -8477,7 +8473,11 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
false, is_u_shift, size+1, shift);
narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
if (i == 0) {
tcg_gen_mov_i64(tcg_final, tcg_rd);
} else {
tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
}
}
if (!is_q) {
@@ -8771,9 +8771,8 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
assert(!(is_scalar && is_q));
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, tcg_fpstatus);
fracbits = (16 << size) - immhb;
tcg_shift = tcg_constant_i32(fracbits);
@@ -8831,7 +8830,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
}
}
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
/* AdvSIMD scalar shift by immediate
@@ -10219,12 +10218,11 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
tcg_rmode = NULL;
tcg_fpstatus = NULL;
tcg_rmode = NULL;
}
if (size == 3) {
@@ -10276,7 +10274,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -12005,22 +12003,26 @@ static void handle_rev(DisasContext *s, int opcode, bool u,
int esize = 8 << size;
int elements = dsize / esize;
TCGv_i64 tcg_rn = tcg_temp_new_i64();
TCGv_i64 tcg_rd = tcg_const_i64(0);
TCGv_i64 tcg_rd_hi = tcg_const_i64(0);
TCGv_i64 tcg_rd[2];
for (i = 0; i < 2; i++) {
tcg_rd[i] = tcg_temp_new_i64();
tcg_gen_movi_i64(tcg_rd[i], 0);
}
for (i = 0; i < elements; i++) {
int e_rev = (i & 0xf) ^ revmask;
int off = e_rev * esize;
int w = (e_rev * esize) / 64;
int o = (e_rev * esize) % 64;
read_vec_element(s, tcg_rn, rn, i, size);
if (off >= 64) {
tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi,
tcg_rn, off - 64, esize);
} else {
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
}
tcg_gen_deposit_i64(tcg_rd[w], tcg_rd[w], tcg_rn, o, esize);
}
write_vec_element(s, tcg_rd, rd, 0, MO_64);
write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);
for (i = 0; i < 2; i++) {
write_vec_element(s, tcg_rd[i], rd, i, MO_64);
}
clear_vec_high(s, true, rd);
}
}
@@ -12133,7 +12135,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
bool need_fpstatus = false;
bool need_rmode = false;
int rmode = -1;
TCGv_i32 tcg_rmode;
TCGv_ptr tcg_fpstatus;
@@ -12283,7 +12284,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
need_fpstatus = true;
need_rmode = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
if (size == 3 && !is_q) {
unallocated_encoding(s);
@@ -12293,7 +12293,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x5c: /* FCVTAU */
case 0x1c: /* FCVTAS */
need_fpstatus = true;
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
if (size == 3 && !is_q) {
unallocated_encoding(s);
@@ -12352,7 +12351,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
case 0x39: /* FRINTZ */
need_rmode = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
/* fall through */
case 0x59: /* FRINTX */
@@ -12364,7 +12362,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
break;
case 0x58: /* FRINTA */
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
need_fpstatus = true;
if (size == 3 && !is_q) {
@@ -12380,7 +12377,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
break;
case 0x1e: /* FRINT32Z */
case 0x1f: /* FRINT64Z */
need_rmode = true;
rmode = FPROUNDING_ZERO;
/* fall through */
case 0x5e: /* FRINT32X */
@@ -12406,14 +12402,13 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
return;
}
if (need_fpstatus || need_rmode) {
if (need_fpstatus || rmode >= 0) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
} else {
tcg_fpstatus = NULL;
}
if (need_rmode) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
tcg_rmode = NULL;
}
@@ -12595,8 +12590,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
clear_vec_high(s, is_q, rd);
if (need_rmode) {
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
if (tcg_rmode) {
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -12625,9 +12620,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
int pass;
TCGv_i32 tcg_rmode = NULL;
TCGv_ptr tcg_fpstatus = NULL;
bool need_rmode = false;
bool need_fpst = true;
int rmode;
int rmode = -1;
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
@@ -12676,27 +12670,22 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x3f: /* FRECPX */
break;
case 0x18: /* FRINTN */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x19: /* FRINTM */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x38: /* FRINTP */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_POSINF;
break;
case 0x39: /* FRINTZ */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_ZERO;
break;
case 0x58: /* FRINTA */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_TIEAWAY;
break;
@@ -12706,43 +12695,33 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
/* current rounding mode */
break;
case 0x1a: /* FCVTNS */
need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x1b: /* FCVTMS */
need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x1c: /* FCVTAS */
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x3a: /* FCVTPS */
need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x3b: /* FCVTZS */
need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
case 0x5a: /* FCVTNU */
need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x5b: /* FCVTMU */
need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x5c: /* FCVTAU */
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x7a: /* FCVTPU */
need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x7b: /* FCVTZU */
need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
case 0x2f: /* FABS */
@@ -12775,13 +12754,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
return;
}
if (need_rmode || need_fpst) {
if (rmode >= 0 || need_fpst) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR_F16);
}
if (need_rmode) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
}
if (is_scalar) {
@@ -12881,7 +12859,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
}
if (tcg_rmode) {
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
target/arm/tcg/translate-mve.c
+30 -26
View File
@@ -588,7 +588,7 @@ DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs)
DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu)
static bool do_vcvt_rmode(DisasContext *s, arg_1op *a,
enum arm_fprounding rmode, bool u)
ARMFPRounding rmode, bool u)
{
/*
* Handle VCVT fp to int with specified rounding mode.
@@ -1150,7 +1150,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
MVEGenLongDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
TCGv_i64 rda;
TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;
if (!dc_isar_feature(aa32_mve, s) ||
@@ -1177,21 +1177,22 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current rda value, not 0.
*/
rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
rda = tcg_temp_new_i64();
rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
rda = tcg_const_i64(0);
rda_i = tcg_constant_i64(0);
}
fn(rda, cpu_env, qn, qm, rda);
fn(rda_o, cpu_env, qn, qm, rda_i);
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda);
tcg_gen_extrl_i64_i32(rdalo, rda_o);
tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);
@@ -1258,7 +1259,7 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
TCGv_i32 rda;
TCGv_i32 rda_i, rda_o;
if (!dc_isar_feature(aa32_mve, s) ||
!mve_check_qreg_bank(s, a->qn) ||
@@ -1278,13 +1279,14 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
* beat must start with the current rda value, not 0.
*/
if (a->a || mve_skip_first_beat(s)) {
rda = load_reg(s, a->rda);
rda_o = rda_i = load_reg(s, a->rda);
} else {
rda = tcg_const_i32(0);
rda_i = tcg_constant_i32(0);
rda_o = tcg_temp_new_i32();
}
fn(rda, cpu_env, qn, qm, rda);
store_reg(s, a->rda, rda);
fn(rda_o, cpu_env, qn, qm, rda_i);
store_reg(s, a->rda, rda_o);
mve_update_eci(s);
return true;
@@ -1396,7 +1398,7 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
{ NULL, NULL }
};
TCGv_ptr qm;
TCGv_i32 rda;
TCGv_i32 rda_i, rda_o;
if (!dc_isar_feature(aa32_mve, s) ||
a->size == 3) {
@@ -1413,15 +1415,16 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
*/
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from Rda */
rda = load_reg(s, a->rda);
rda_o = rda_i = load_reg(s, a->rda);
} else {
/* Accumulate starting at zero */
rda = tcg_const_i32(0);
rda_i = tcg_constant_i32(0);
rda_o = tcg_temp_new_i32();
}
qm = mve_qreg_ptr(a->qm);
fns[a->size][a->u](rda, cpu_env, qm, rda);
store_reg(s, a->rda, rda);
fns[a->size][a->u](rda_o, cpu_env, qm, rda_i);
store_reg(s, a->rda, rda_o);
mve_update_eci(s);
return true;
@@ -1436,7 +1439,7 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* No need to check Qm's bank: it is only 3 bits in decode.
*/
TCGv_ptr qm;
TCGv_i64 rda;
TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;
if (!dc_isar_feature(aa32_mve, s)) {
@@ -1458,28 +1461,29 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current value of RdaHi:RdaLo, not zero.
*/
rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from RdaHi:RdaLo */
rda = tcg_temp_new_i64();
rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
/* Accumulate starting at zero */
rda = tcg_const_i64(0);
rda_i = tcg_constant_i64(0);
}
qm = mve_qreg_ptr(a->qm);
if (a->u) {
gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i);
} else {
gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i);
}
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda);
tcg_gen_extrl_i64_i32(rdalo, rda_o);
tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);
target/arm/tcg/translate-sve.c
+14 -14
View File
@@ -4082,7 +4082,7 @@ TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
int mode, gen_helper_gvec_3_ptr *fn)
ARMFPRounding mode, gen_helper_gvec_3_ptr *fn)
{
unsigned vsz;
TCGv_i32 tmode;
@@ -4096,30 +4096,28 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
vsz = vec_full_reg_size(s);
tmode = tcg_const_i32(mode);
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
gen_helper_set_rmode(tmode, tmode, status);
tmode = gen_set_rmode(mode, status);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
pred_full_reg_offset(s, a->pg),
status, vsz, vsz, 0, fn);
gen_helper_set_rmode(tmode, tmode, status);
gen_restore_rmode(tmode, status);
return true;
}
TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a,
float_round_nearest_even, frint_fns[a->esz])
FPROUNDING_TIEEVEN, frint_fns[a->esz])
TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a,
float_round_up, frint_fns[a->esz])
FPROUNDING_POSINF, frint_fns[a->esz])
TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a,
float_round_down, frint_fns[a->esz])
FPROUNDING_NEGINF, frint_fns[a->esz])
TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a,
float_round_to_zero, frint_fns[a->esz])
FPROUNDING_ZERO, frint_fns[a->esz])
TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a,
float_round_ties_away, frint_fns[a->esz])
FPROUNDING_TIEAWAY, frint_fns[a->esz])
static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
NULL, gen_helper_sve_frecpx_h,
@@ -4208,8 +4206,9 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
TCGv_ptr tp, i = tcg_const_ptr(0);
TCGv_ptr tp, i = tcg_temp_new_ptr();
tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);
t0 = tcg_temp_new_i64();
@@ -4286,8 +4285,9 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
TCGv_ptr tp, i = tcg_const_ptr(0);
TCGv_ptr tp, i = tcg_temp_new_ptr();
tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);
t0 = tcg_temp_new_i64();
@@ -7145,9 +7145,9 @@ TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
float_round_to_odd, gen_helper_sve_fcvt_ds)
FPROUNDING_ODD, gen_helper_sve_fcvt_ds)
TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds)
static gen_helper_gvec_3_ptr * const flogb_fns[] = {
NULL, gen_helper_flogb_h,
target/arm/tcg/translate-vfp.c
+10 -16
View File
@@ -464,8 +464,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
fpst = fpstatus_ptr(FPST_FPCR);
}
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_op;
@@ -489,7 +488,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
vfp_store_reg32(tcg_res, rd);
}
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@@ -533,9 +532,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
}
tcg_shift = tcg_constant_i32(0);
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_double, tcg_res;
@@ -572,7 +569,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
vfp_store_reg32(tcg_res, rd);
}
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@@ -2783,10 +2780,9 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR_F16);
tcg_rmode = tcg_const_i32(float_round_to_zero);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rinth(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@@ -2808,10 +2804,9 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
tcg_rmode = tcg_const_i32(float_round_to_zero);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rints(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@@ -2842,10 +2837,9 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
tcg_rmode = tcg_const_i32(float_round_to_zero);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rintd(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
}
target/arm/tcg/translate.c
+6 -8
View File
@@ -7261,8 +7261,8 @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
{
TCGv_i32 tmp;
int msb = a->msb, lsb = a->lsb;
TCGv_i32 t_in, t_rd;
int width;
if (!ENABLE_ARCH_6T2) {
@@ -7277,16 +7277,14 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
width = msb + 1 - lsb;
if (a->rn == 15) {
/* BFC */
tmp = tcg_const_i32(0);
t_in = tcg_constant_i32(0);
} else {
/* BFI */
tmp = load_reg(s, a->rn);
t_in = load_reg(s, a->rn);
}
if (width != 32) {
TCGv_i32 tmp2 = load_reg(s, a->rd);
tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
}
store_reg(s, a->rd, tmp);
t_rd = load_reg(s, a->rd);
tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
store_reg(s, a->rd, t_rd);
return true;
}
target/arm/tcg/translate.h
+17
View File
@@ -616,6 +616,23 @@ static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
return ret;
}
/*
* Set and reset rounding mode around another operation.
*/
static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst)
{
TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode));
TCGv_i32 old = tcg_temp_new_i32();
gen_helper_set_rmode(old, new, fpst);
return old;
}
static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
{
gen_helper_set_rmode(old, old, fpst);
}
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
target/arm/vfp_helper.c
+8 -27
View File
@@ -1104,33 +1104,14 @@ float64 HELPER(rintd)(float64 x, void *fp_status)
}
/* Convert ARM rounding mode to softfloat */
int arm_rmode_to_sf(int rmode)
{
switch (rmode) {
case FPROUNDING_TIEAWAY:
rmode = float_round_ties_away;
break;
case FPROUNDING_ODD:
/* FIXME: add support for TIEAWAY and ODD */
qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
rmode);
/* fall through for now */
case FPROUNDING_TIEEVEN:
default:
rmode = float_round_nearest_even;
break;
case FPROUNDING_POSINF:
rmode = float_round_up;
break;
case FPROUNDING_NEGINF:
rmode = float_round_down;
break;
case FPROUNDING_ZERO:
rmode = float_round_to_zero;
break;
}
return rmode;
}
const FloatRoundMode arm_rmode_to_sf_map[] = {
[FPROUNDING_TIEEVEN] = float_round_nearest_even,
[FPROUNDING_POSINF] = float_round_up,
[FPROUNDING_NEGINF] = float_round_down,
[FPROUNDING_ZERO] = float_round_to_zero,
[FPROUNDING_TIEAWAY] = float_round_ties_away,
[FPROUNDING_ODD] = float_round_to_odd,
};
/*
* Implement float64 to int32_t conversion without saturation;
target/avr/cpu-param.h
-1
View File
@@ -31,6 +31,5 @@
#define TARGET_PAGE_BITS 8
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
#define NB_MMU_MODES 2
#endif
target/avr/translate.c
+25 -23
View File
@@ -400,7 +400,7 @@ static bool trans_SUB(DisasContext *ctx, arg_SUB *a)
static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv Rr = tcg_const_i32(a->imm);
TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */
@@ -425,7 +425,7 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@@ -453,9 +453,9 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv Rr = tcg_const_i32(a->imm);
TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@@ -637,7 +637,7 @@ static bool trans_COM(DisasContext *ctx, arg_COM *a)
static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv t0 = tcg_const_i32(0);
TCGv t0 = tcg_constant_i32(0);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */
@@ -930,19 +930,19 @@ static void gen_jmp_z(DisasContext *ctx)
static void gen_push_ret(DisasContext *ctx, int ret)
{
if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
TCGv t0 = tcg_const_i32((ret & 0x0000ff));
TCGv t0 = tcg_constant_i32(ret & 0x0000ff);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
TCGv t0 = tcg_const_i32((ret & 0x00ffff));
TCGv t0 = tcg_constant_i32(ret & 0x00ffff);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
TCGv lo = tcg_const_i32((ret & 0x0000ff));
TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
TCGv lo = tcg_constant_i32(ret & 0x0000ff);
TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8);
tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
@@ -1211,7 +1211,7 @@ static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@@ -1238,7 +1238,7 @@ static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
{
TCGv Rd = cpu_r[a->rd];
int Imm = a->imm;
TCGv Rr = tcg_const_i32(Imm);
TCGv Rr = tcg_constant_i32(Imm);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
@@ -1288,12 +1288,13 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
*/
static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
{
TCGv temp = tcg_const_i32(a->reg);
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(temp, cpu_env, temp);
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = temp;
ctx->skip_var0 = data;
return true;
}
@@ -1305,12 +1306,13 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
*/
static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
{
TCGv temp = tcg_const_i32(a->reg);
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(temp, cpu_env, temp);
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = temp;
ctx->skip_var0 = data;
return true;
}
@@ -2122,7 +2124,7 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a)
static bool trans_IN(DisasContext *ctx, arg_IN *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_const_i32(a->imm);
TCGv port = tcg_constant_i32(a->imm);
gen_helper_inb(Rd, cpu_env, port);
return true;
@@ -2135,7 +2137,7 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a)
static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_const_i32(a->imm);
TCGv port = tcg_constant_i32(a->imm);
gen_helper_outb(cpu_env, port, Rd);
return true;
@@ -2403,7 +2405,7 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a)
static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
{
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_const_i32(a->reg);
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
tcg_gen_ori_tl(data, data, 1 << a->bit);
@@ -2418,7 +2420,7 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
{
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_const_i32(a->reg);
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, ~(1 << a->bit));
target/cris/cpu-param.h
-1
View File
@@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 13
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 2
#endif
target/cris/translate.c
+21 -25
View File
@@ -175,10 +175,7 @@ static const int preg_sizes[] = {
#define t_gen_mov_env_TN(member, tn) \
tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
#define t_gen_movi_env_TN(member, c) \
do { \
TCGv tc = tcg_const_tl(c); \
t_gen_mov_env_TN(member, tc); \
} while (0)
t_gen_mov_env_TN(member, tcg_constant_tl(c))
static inline void t_gen_mov_TN_preg(TCGv tn, int r)
{
@@ -268,8 +265,7 @@ static void cris_lock_irq(DisasContext *dc)
static inline void t_gen_raise_exception(uint32_t index)
{
TCGv_i32 tmp = tcg_const_i32(index);
gen_helper_raise_exception(cpu_env, tmp);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
}
static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
@@ -277,7 +273,7 @@ static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
TCGv t0, t_31;
t0 = tcg_temp_new();
t_31 = tcg_const_tl(31);
t_31 = tcg_constant_tl(31);
tcg_gen_shl_tl(d, a, b);
tcg_gen_sub_tl(t0, t_31, b);
@@ -1250,7 +1246,7 @@ static int dec_addq(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(dc->op1);
c = tcg_constant_tl(dc->op1);
cris_alu(dc, CC_OP_ADD,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1274,7 +1270,7 @@ static int dec_subq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(dc->op1);
c = tcg_constant_tl(dc->op1);
cris_alu(dc, CC_OP_SUB,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1289,7 +1285,7 @@ static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1304,7 +1300,7 @@ static int dec_andq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_AND,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1318,7 +1314,7 @@ static int dec_orq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_OR,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1330,7 +1326,7 @@ static int dec_btstq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_const_tl(dc->op1);
c = tcg_constant_tl(dc->op1);
cris_evaluate_flags(dc);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
c, cpu_PR[PR_CCS]);
@@ -1945,8 +1941,8 @@ static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
{
TCGv c2, c1;
LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
c1 = tcg_const_tl(dc->op1);
c2 = tcg_const_tl(dc->op2);
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_sreg_reg(cpu_env, c2, c1);
return 2;
@@ -1955,8 +1951,8 @@ static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
{
TCGv c2, c1;
LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
c1 = tcg_const_tl(dc->op1);
c2 = tcg_const_tl(dc->op2);
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_reg_sreg(cpu_env, c1, c2);
return 2;
@@ -2237,7 +2233,7 @@ static int dec_test_m(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZ);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
c = tcg_const_tl(0);
c = tcg_constant_tl(0);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], t[1], c, memsize_zz(dc));
do_postinc(dc, memsize);
@@ -2582,7 +2578,7 @@ static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
if (dc->op2 > 15) {
abort();
}
c = tcg_const_tl(dc->pc + 4);
c = tcg_constant_tl(dc->pc + 4);
t_gen_mov_preg_TN(dc, dc->op2, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
@@ -2598,7 +2594,7 @@ static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jas 0x%x\n", imm);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 8);
c = tcg_constant_tl(dc->pc + 8);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@@ -2616,7 +2612,7 @@ static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jasc 0x%x\n", imm);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 8 + 4);
c = tcg_constant_tl(dc->pc + 8 + 4);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@@ -2632,7 +2628,7 @@ static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
c = tcg_const_tl(dc->pc + 4 + 4);
c = tcg_constant_tl(dc->pc + 4 + 4);
t_gen_mov_preg_TN(dc, dc->op2, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
return 2;
@@ -2664,7 +2660,7 @@ static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 8);
c = tcg_constant_tl(dc->pc + 8);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@@ -2681,7 +2677,7 @@ static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 12);
c = tcg_constant_tl(dc->pc + 12);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@@ -2695,7 +2691,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0);
if (dc->op2 == 15) {
tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
-offsetof(CRISCPU, env) + offsetof(CPUState, halted));
tcg_gen_movi_tl(env_pc, dc->pc + 2);
t_gen_raise_exception(EXCP_HLT);
target/cris/translate_v10.c.inc
+13 -13
View File
@@ -251,7 +251,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -259,7 +259,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -267,7 +267,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -275,7 +275,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -285,7 +285,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZVC);
op = imm & (1 << 5);
imm &= 0x1f;
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
if (op) {
cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
@@ -305,7 +305,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
}
imm &= 0x1f;
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, op, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -313,7 +313,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -321,7 +321,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -1014,7 +1014,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
cris_alu_m_alloc_temps(t);
insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
c = tcg_const_tl(0);
c = tcg_constant_tl(0);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
t[0], c, size);
break;
@@ -1111,7 +1111,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
if (dc->mode == CRISV10_MODE_AUTOINC)
insn_len += size;
c = tcg_const_tl(dc->pc + insn_len);
c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
dc->jmp_pc = imm;
cris_prepare_jmp(dc, JMP_DIRECT);
@@ -1121,7 +1121,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("break %d\n", dc->src);
cris_evaluate_flags(dc);
tcg_gen_movi_tl(env_pc, dc->pc + 2);
c = tcg_const_tl(dc->src + 2);
c = tcg_constant_tl(dc->src + 2);
t_gen_mov_env_TN(trap_vector, c);
t_gen_raise_exception(EXCP_BREAK);
dc->base.is_jmp = DISAS_NORETURN;
@@ -1130,7 +1130,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
dc->opcode, dc->src, dc->dst);
t[0] = tcg_temp_new();
c = tcg_const_tl(dc->pc + insn_len);
c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
crisv10_prepare_memaddr(dc, t[0], size);
gen_load(dc, env_btarget, t[0], 4, 0);
@@ -1153,7 +1153,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
dc->pc, dc->opcode, dc->dst, dc->src);
tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
c = tcg_const_tl(dc->pc + insn_len);
c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
dc->delayed_branch--; /* v10 has no dslot here. */

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