mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/target_renesas_rx-20200320' into staging
Introduce the architectural part of the Renesas RX architecture emulation, developed by Yoshinori Sato. CI jobs results: https://gitlab.com/philmd/qemu/pipelines/127886344 https://travis-ci.org/github/philmd/qemu/builds/664579420 # gpg: Signature made Fri 20 Mar 2020 10:27:32 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/target_renesas_rx-20200320: Add rx-softmmu target/rx: Dump bytes for each insn during disassembly target/rx: Collect all bytes during disassembly target/rx: Emit all disassembly in one prt() target/rx: Use prt_ldmi for XCHG_mr disassembly target/rx: Replace operand with prt_ldmi in disassembler target/rx: Disassemble rx_index_addr into a string target/rx: RX disassembler target/rx: CPU definitions target/rx: TCG helpers target/rx: TCG translation MAINTAINERS: Add entry for the Renesas RX architecture hw/registerfields.h: Add 8bit and 16bit register macros Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
@@ -277,6 +277,11 @@ F: include/hw/riscv/
|
||||
F: linux-user/host/riscv32/
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||||
F: linux-user/host/riscv64/
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||||
|
||||
RENESAS RX CPUs
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M: Yoshinori Sato <ysato@users.sourceforge.jp>
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||||
S: Maintained
|
||||
F: target/rx/
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||||
|
||||
S390 TCG CPUs
|
||||
M: Richard Henderson <rth@twiddle.net>
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||||
M: David Hildenbrand <david@redhat.com>
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||||
|
||||
@@ -77,6 +77,8 @@ int graphic_depth = 32;
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||||
#define QEMU_ARCH QEMU_ARCH_PPC
|
||||
#elif defined(TARGET_RISCV)
|
||||
#define QEMU_ARCH QEMU_ARCH_RISCV
|
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#elif defined(TARGET_RX)
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#define QEMU_ARCH QEMU_ARCH_RX
|
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#elif defined(TARGET_S390X)
|
||||
#define QEMU_ARCH QEMU_ARCH_S390X
|
||||
#elif defined(TARGET_SH4)
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||||
|
||||
@@ -4227,7 +4227,7 @@ fi
|
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fdt_required=no
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for target in $target_list; do
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case $target in
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aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu|mips64el-softmmu|riscv*-softmmu)
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aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu|mips64el-softmmu|riscv*-softmmu|rx-softmmu)
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fdt_required=yes
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;;
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esac
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@@ -7912,6 +7912,12 @@ case "$target_name" in
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mttcg=yes
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gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
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;;
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rx)
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TARGET_ARCH=rx
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bflt="yes"
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target_compiler=$cross_cc_rx
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gdb_xml_files="rx-core.xml"
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;;
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sh4|sh4eb)
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TARGET_ARCH=sh4
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bflt="yes"
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@@ -8093,6 +8099,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
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riscv*)
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disas_config "RISCV"
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;;
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rx)
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disas_config "RX"
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;;
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s390*)
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disas_config "S390"
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;;
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@@ -0,0 +1,2 @@
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# Default configuration for rx-softmmu
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|
||||
@@ -0,0 +1,70 @@
|
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<?xml version="1.0"?>
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||||
<!-- Copyright (C) 2019 Free Software Foundation, Inc.
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||||
|
||||
Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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||||
notice and this notice are preserved. -->
|
||||
|
||||
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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||||
<feature name="org.gnu.gdb.rx.core">
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||||
<reg name="r0" bitsize="32" type="data_ptr"/>
|
||||
<reg name="r1" bitsize="32" type="uint32"/>
|
||||
<reg name="r2" bitsize="32" type="uint32"/>
|
||||
<reg name="r3" bitsize="32" type="uint32"/>
|
||||
<reg name="r4" bitsize="32" type="uint32"/>
|
||||
<reg name="r5" bitsize="32" type="uint32"/>
|
||||
<reg name="r6" bitsize="32" type="uint32"/>
|
||||
<reg name="r7" bitsize="32" type="uint32"/>
|
||||
<reg name="r8" bitsize="32" type="uint32"/>
|
||||
<reg name="r9" bitsize="32" type="uint32"/>
|
||||
<reg name="r10" bitsize="32" type="uint32"/>
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<reg name="r11" bitsize="32" type="uint32"/>
|
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<reg name="r12" bitsize="32" type="uint32"/>
|
||||
<reg name="r13" bitsize="32" type="uint32"/>
|
||||
<reg name="r14" bitsize="32" type="uint32"/>
|
||||
<reg name="r15" bitsize="32" type="uint32"/>
|
||||
|
||||
<flags id="psw_flags" size="4">
|
||||
<field name="C" start="0" end="0"/>
|
||||
<field name="Z" start="1" end="1"/>
|
||||
<field name="S" start="2" end="2"/>
|
||||
<field name="O" start="3" end="3"/>
|
||||
<field name="I" start="16" end="16"/>
|
||||
<field name="U" start="17" end="17"/>
|
||||
<field name="PM" start="20" end="20"/>
|
||||
<field name="IPL" start="24" end="27"/>
|
||||
</flags>
|
||||
|
||||
<flags id="fpsw_flags" size="4">
|
||||
<field name="RM" start="0" end="1"/>
|
||||
<field name="CV" start="2" end="2"/>
|
||||
<field name="CO" start="3" end="3"/>
|
||||
<field name="CZ" start="4" end="4"/>
|
||||
<field name="CU" start="5" end="5"/>
|
||||
<field name="CX" start="6" end="6"/>
|
||||
<field name="CE" start="7" end="7"/>
|
||||
<field name="DN" start="8" end="8"/>
|
||||
<field name="EV" start="10" end="10"/>
|
||||
<field name="EO" start="11" end="11"/>
|
||||
<field name="EZ" start="12" end="12"/>
|
||||
<field name="EU" start="13" end="13"/>
|
||||
<field name="EX" start="14" end="14"/>
|
||||
<field name="FV" start="26" end="26"/>
|
||||
<field name="FO" start="27" end="27"/>
|
||||
<field name="FZ" start="28" end="28"/>
|
||||
<field name="FU" start="29" end="29"/>
|
||||
<field name="FX" start="30" end="30"/>
|
||||
<field name="FS" start="31" end="31"/>
|
||||
</flags>
|
||||
|
||||
<reg name="usp" bitsize="32" type="data_ptr"/>
|
||||
<reg name="isp" bitsize="32" type="data_ptr"/>
|
||||
<reg name="psw" bitsize="32" type="psw_flags"/>
|
||||
<reg name="pc" bitsize="32" type="code_ptr"/>
|
||||
<reg name="intb" bitsize="32" type="data_ptr"/>
|
||||
<reg name="bpsw" bitsize="32" type="psw_flags"/>
|
||||
<reg name="bpc" bitsize="32" type="code_ptr"/>
|
||||
<reg name="fintv" bitsize="32" type="code_ptr"/>
|
||||
<reg name="fpsw" bitsize="32" type="fpsw_flags"/>
|
||||
<reg name="acc" bitsize="64" type="uint64"/>
|
||||
</feature>
|
||||
@@ -226,6 +226,10 @@ enum bfd_architecture
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#define bfd_mach_nios2r2 2
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||||
bfd_arch_lm32, /* Lattice Mico32 */
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||||
#define bfd_mach_lm32 1
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||||
bfd_arch_rx, /* Renesas RX */
|
||||
#define bfd_mach_rx 0x75
|
||||
#define bfd_mach_rx_v2 0x76
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||||
#define bfd_mach_rx_v3 0x77
|
||||
bfd_arch_last
|
||||
};
|
||||
#define bfd_mach_s390_31 31
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||||
@@ -436,6 +440,7 @@ int print_insn_little_nios2 (bfd_vma, disassemble_info*);
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||||
int print_insn_xtensa (bfd_vma, disassemble_info*);
|
||||
int print_insn_riscv32 (bfd_vma, disassemble_info*);
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||||
int print_insn_riscv64 (bfd_vma, disassemble_info*);
|
||||
int print_insn_rx(bfd_vma, disassemble_info *);
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||||
|
||||
#if 0
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||||
/* Fetch the disassembler for a given BFD, if that support is available. */
|
||||
|
||||
@@ -26,6 +26,7 @@
|
||||
#pragma GCC poison TARGET_PPC
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||||
#pragma GCC poison TARGET_PPC64
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||||
#pragma GCC poison TARGET_ABI32
|
||||
#pragma GCC poison TARGET_RX
|
||||
#pragma GCC poison TARGET_S390X
|
||||
#pragma GCC poison TARGET_SH4
|
||||
#pragma GCC poison TARGET_SPARC
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||||
|
||||
@@ -22,6 +22,14 @@
|
||||
enum { A_ ## reg = (addr) }; \
|
||||
enum { R_ ## reg = (addr) / 4 };
|
||||
|
||||
#define REG8(reg, addr) \
|
||||
enum { A_ ## reg = (addr) }; \
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||||
enum { R_ ## reg = (addr) };
|
||||
|
||||
#define REG16(reg, addr) \
|
||||
enum { A_ ## reg = (addr) }; \
|
||||
enum { R_ ## reg = (addr) / 2 };
|
||||
|
||||
/* Define SHIFT, LENGTH and MASK constants for a field within a register */
|
||||
|
||||
/* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
|
||||
@@ -34,6 +42,12 @@
|
||||
MAKE_64BIT_MASK(shift, length)};
|
||||
|
||||
/* Extract a field from a register */
|
||||
#define FIELD_EX8(storage, reg, field) \
|
||||
extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
|
||||
R_ ## reg ## _ ## field ## _LENGTH)
|
||||
#define FIELD_EX16(storage, reg, field) \
|
||||
extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
|
||||
R_ ## reg ## _ ## field ## _LENGTH)
|
||||
#define FIELD_EX32(storage, reg, field) \
|
||||
extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
|
||||
R_ ## reg ## _ ## field ## _LENGTH)
|
||||
@@ -49,6 +63,22 @@
|
||||
* Assigning values larger then the target field will result in
|
||||
* compilation warnings.
|
||||
*/
|
||||
#define FIELD_DP8(storage, reg, field, val) ({ \
|
||||
struct { \
|
||||
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
|
||||
} v = { .v = val }; \
|
||||
uint8_t d; \
|
||||
d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
|
||||
R_ ## reg ## _ ## field ## _LENGTH, v.v); \
|
||||
d; })
|
||||
#define FIELD_DP16(storage, reg, field, val) ({ \
|
||||
struct { \
|
||||
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
|
||||
} v = { .v = val }; \
|
||||
uint16_t d; \
|
||||
d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
|
||||
R_ ## reg ## _ ## field ## _LENGTH, v.v); \
|
||||
d; })
|
||||
#define FIELD_DP32(storage, reg, field, val) ({ \
|
||||
struct { \
|
||||
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
|
||||
|
||||
@@ -24,6 +24,7 @@ enum {
|
||||
QEMU_ARCH_NIOS2 = (1 << 17),
|
||||
QEMU_ARCH_HPPA = (1 << 18),
|
||||
QEMU_ARCH_RISCV = (1 << 19),
|
||||
QEMU_ARCH_RX = (1 << 20),
|
||||
|
||||
QEMU_ARCH_NONE = (1 << 31),
|
||||
};
|
||||
|
||||
+3
-1
@@ -16,6 +16,8 @@
|
||||
# individual target constants are not documented here, for the time
|
||||
# being.
|
||||
#
|
||||
# @rx: since 5.0
|
||||
#
|
||||
# Notes: The resulting QMP strings can be appended to the "qemu-system-"
|
||||
# prefix to produce the corresponding QEMU executable name. This
|
||||
# is true even for "qemu-system-x86_64".
|
||||
@@ -26,7 +28,7 @@
|
||||
'data' : [ 'aarch64', 'alpha', 'arm', 'cris', 'hppa', 'i386', 'lm32',
|
||||
'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
|
||||
'mips64el', 'mipsel', 'moxie', 'nios2', 'or1k', 'ppc',
|
||||
'ppc64', 'riscv32', 'riscv64', 's390x', 'sh4',
|
||||
'ppc64', 'riscv32', 'riscv64', 'rx', 's390x', 'sh4',
|
||||
'sh4eb', 'sparc', 'sparc64', 'tricore', 'unicore32',
|
||||
'x86_64', 'xtensa', 'xtensaeb' ] }
|
||||
|
||||
|
||||
@@ -0,0 +1,11 @@
|
||||
obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o
|
||||
|
||||
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
|
||||
|
||||
target/rx/decode.inc.c: \
|
||||
$(SRC_PATH)/target/rx/insns.decode $(DECODETREE)
|
||||
$(call quiet-command,\
|
||||
$(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", $(TARGET_DIR)$@)
|
||||
|
||||
target/rx/translate.o: target/rx/decode.inc.c
|
||||
target/rx/disas.o: target/rx/decode.inc.c
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* RX cpu parameters
|
||||
*
|
||||
* Copyright (c) 2019 Yoshinori Sato
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef RX_CPU_PARAM_H
|
||||
#define RX_CPU_PARAM_H
|
||||
|
||||
#define TARGET_LONG_BITS 32
|
||||
#define TARGET_PAGE_BITS 12
|
||||
|
||||
#define TARGET_PHYS_ADDR_SPACE_BITS 32
|
||||
#define TARGET_VIRT_ADDR_SPACE_BITS 32
|
||||
|
||||
#define NB_MMU_MODES 1
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* RX CPU
|
||||
*
|
||||
* Copyright (c) 2019 Yoshinori Sato
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef RX_CPU_QOM_H
|
||||
#define RX_CPU_QOM_H
|
||||
|
||||
#include "hw/core/cpu.h"
|
||||
|
||||
#define TYPE_RX_CPU "rx-cpu"
|
||||
|
||||
#define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")
|
||||
|
||||
#define RXCPU_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RX_CPU)
|
||||
#define RXCPU(obj) \
|
||||
OBJECT_CHECK(RXCPU, (obj), TYPE_RX_CPU)
|
||||
#define RXCPU_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RX_CPU)
|
||||
|
||||
/*
|
||||
* RXCPUClass:
|
||||
* @parent_realize: The parent class' realize handler.
|
||||
* @parent_reset: The parent class' reset handler.
|
||||
*
|
||||
* A RX CPU model.
|
||||
*/
|
||||
typedef struct RXCPUClass {
|
||||
/*< private >*/
|
||||
CPUClass parent_class;
|
||||
/*< public >*/
|
||||
|
||||
DeviceRealize parent_realize;
|
||||
DeviceReset parent_reset;
|
||||
} RXCPUClass;
|
||||
|
||||
#define CPUArchState struct CPURXState
|
||||
|
||||
#endif
|
||||
+225
@@ -0,0 +1,225 @@
|
||||
/*
|
||||
* QEMU RX CPU
|
||||
*
|
||||
* Copyright (c) 2019 Yoshinori Sato
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qemu/qemu-print.h"
|
||||
#include "qapi/error.h"
|
||||
#include "cpu.h"
|
||||
#include "qemu-common.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "hw/loader.h"
|
||||
#include "fpu/softfloat.h"
|
||||
|
||||
static void rx_cpu_set_pc(CPUState *cs, vaddr value)
|
||||
{
|
||||
RXCPU *cpu = RXCPU(cs);
|
||||
|
||||
cpu->env.pc = value;
|
||||
}
|
||||
|
||||
static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
|
||||
{
|
||||
RXCPU *cpu = RXCPU(cs);
|
||||
|
||||
cpu->env.pc = tb->pc;
|
||||
}
|
||||
|
||||
static bool rx_cpu_has_work(CPUState *cs)
|
||||
{
|
||||
return cs->interrupt_request &
|
||||
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
|
||||
}
|
||||
|
||||
static void rx_cpu_reset(DeviceState *dev)
|
||||
{
|
||||
RXCPU *cpu = RXCPU(dev);
|
||||
RXCPUClass *rcc = RXCPU_GET_CLASS(cpu);
|
||||
CPURXState *env = &cpu->env;
|
||||
uint32_t *resetvec;
|
||||
|
||||
rcc->parent_reset(dev);
|
||||
|
||||
memset(env, 0, offsetof(CPURXState, end_reset_fields));
|
||||
|
||||
resetvec = rom_ptr(0xfffffffc, 4);
|
||||
if (resetvec) {
|
||||
/* In the case of kernel, it is ignored because it is not set. */
|
||||
env->pc = ldl_p(resetvec);
|
||||
}
|
||||
rx_cpu_unpack_psw(env, 0, 1);
|
||||
env->regs[0] = env->isp = env->usp = 0;
|
||||
env->fpsw = 0;
|
||||
set_flush_to_zero(1, &env->fp_status);
|
||||
set_flush_inputs_to_zero(1, &env->fp_status);
|
||||
}
|
||||
|
||||
static void rx_cpu_list_entry(gpointer data, gpointer user_data)
|
||||
{
|
||||
ObjectClass *oc = data;
|
||||
|
||||
qemu_printf(" %s\n", object_class_get_name(oc));
|
||||
}
|
||||
|
||||
void rx_cpu_list(void)
|
||||
{
|
||||
GSList *list;
|
||||
list = object_class_get_list_sorted(TYPE_RX_CPU, false);
|
||||
qemu_printf("Available CPUs:\n");
|
||||
g_slist_foreach(list, rx_cpu_list_entry, NULL);
|
||||
g_slist_free(list);
|
||||
}
|
||||
|
||||
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
|
||||
{
|
||||
ObjectClass *oc;
|
||||
char *typename;
|
||||
|
||||
oc = object_class_by_name(cpu_model);
|
||||
if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
|
||||
!object_class_is_abstract(oc)) {
|
||||
return oc;
|
||||
}
|
||||
typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
|
||||
oc = object_class_by_name(typename);
|
||||
g_free(typename);
|
||||
if (oc != NULL && object_class_is_abstract(oc)) {
|
||||
oc = NULL;
|
||||
}
|
||||
|
||||
return oc;
|
||||
}
|
||||
|
||||
static void rx_cpu_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
CPUState *cs = CPU(dev);
|
||||
RXCPUClass *rcc = RXCPU_GET_CLASS(dev);
|
||||
Error *local_err = NULL;
|
||||
|
||||
cpu_exec_realizefn(cs, &local_err);
|
||||
if (local_err != NULL) {
|
||||
error_propagate(errp, local_err);
|
||||
return;
|
||||
}
|
||||
|
||||
qemu_init_vcpu(cs);
|
||||
cpu_reset(cs);
|
||||
|
||||
rcc->parent_realize(dev, errp);
|
||||
}
|
||||
|
||||
static void rx_cpu_set_irq(void *opaque, int no, int request)
|
||||
{
|
||||
RXCPU *cpu = opaque;
|
||||
CPUState *cs = CPU(cpu);
|
||||
int irq = request & 0xff;
|
||||
|
||||
static const int mask[] = {
|
||||
[RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
|
||||
[RX_CPU_FIR] = CPU_INTERRUPT_FIR,
|
||||
};
|
||||
if (irq) {
|
||||
cpu->env.req_irq = irq;
|
||||
cpu->env.req_ipl = (request >> 8) & 0x0f;
|
||||
cpu_interrupt(cs, mask[no]);
|
||||
} else {
|
||||
cpu_reset_interrupt(cs, mask[no]);
|
||||
}
|
||||
}
|
||||
|
||||
static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
|
||||
{
|
||||
info->mach = bfd_mach_rx;
|
||||
info->print_insn = print_insn_rx;
|
||||
}
|
||||
|
||||
static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
bool probe, uintptr_t retaddr)
|
||||
{
|
||||
uint32_t address, physical, prot;
|
||||
|
||||
/* Linear mapping */
|
||||
address = physical = addr & TARGET_PAGE_MASK;
|
||||
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
|
||||
return true;
|
||||
}
|
||||
|
||||
static void rx_cpu_init(Object *obj)
|
||||
{
|
||||
CPUState *cs = CPU(obj);
|
||||
RXCPU *cpu = RXCPU(obj);
|
||||
CPURXState *env = &cpu->env;
|
||||
|
||||
cpu_set_cpustate_pointers(cpu);
|
||||
cs->env_ptr = env;
|
||||
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
|
||||
}
|
||||
|
||||
static void rx_cpu_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
CPUClass *cc = CPU_CLASS(klass);
|
||||
RXCPUClass *rcc = RXCPU_CLASS(klass);
|
||||
|
||||
device_class_set_parent_realize(dc, rx_cpu_realize,
|
||||
&rcc->parent_realize);
|
||||
device_class_set_parent_reset(dc, rx_cpu_reset,
|
||||
&rcc->parent_reset);
|
||||
|
||||
cc->class_by_name = rx_cpu_class_by_name;
|
||||
cc->has_work = rx_cpu_has_work;
|
||||
cc->do_interrupt = rx_cpu_do_interrupt;
|
||||
cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
|
||||
cc->dump_state = rx_cpu_dump_state;
|
||||
cc->set_pc = rx_cpu_set_pc;
|
||||
cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;
|
||||
cc->gdb_read_register = rx_cpu_gdb_read_register;
|
||||
cc->gdb_write_register = rx_cpu_gdb_write_register;
|
||||
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
|
||||
cc->disas_set_info = rx_cpu_disas_set_info;
|
||||
cc->tcg_initialize = rx_translate_init;
|
||||
cc->tlb_fill = rx_cpu_tlb_fill;
|
||||
|
||||
cc->gdb_num_core_regs = 26;
|
||||
cc->gdb_core_xml_file = "rx-core.xml";
|
||||
}
|
||||
|
||||
static const TypeInfo rx_cpu_info = {
|
||||
.name = TYPE_RX_CPU,
|
||||
.parent = TYPE_CPU,
|
||||
.instance_size = sizeof(RXCPU),
|
||||
.instance_init = rx_cpu_init,
|
||||
.abstract = true,
|
||||
.class_size = sizeof(RXCPUClass),
|
||||
.class_init = rx_cpu_class_init,
|
||||
};
|
||||
|
||||
static const TypeInfo rx62n_rx_cpu_info = {
|
||||
.name = TYPE_RX62N_CPU,
|
||||
.parent = TYPE_RX_CPU,
|
||||
};
|
||||
|
||||
static void rx_cpu_register_types(void)
|
||||
{
|
||||
type_register_static(&rx_cpu_info);
|
||||
type_register_static(&rx62n_rx_cpu_info);
|
||||
}
|
||||
|
||||
type_init(rx_cpu_register_types)
|
||||
+180
@@ -0,0 +1,180 @@
|
||||
/*
|
||||
* RX emulation definition
|
||||
*
|
||||
* Copyright (c) 2019 Yoshinori Sato
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef RX_CPU_H
|
||||
#define RX_CPU_H
|
||||
|
||||
#include "qemu/bitops.h"
|
||||
#include "qemu-common.h"
|
||||
#include "hw/registerfields.h"
|
||||
#include "cpu-qom.h"
|
||||
|
||||
#include "exec/cpu-defs.h"
|
||||
|
||||
/* PSW define */
|
||||
REG32(PSW, 0)
|
||||
FIELD(PSW, C, 0, 1)
|
||||
FIELD(PSW, Z, 1, 1)
|
||||
FIELD(PSW, S, 2, 1)
|
||||
FIELD(PSW, O, 3, 1)
|
||||
FIELD(PSW, I, 16, 1)
|
||||
FIELD(PSW, U, 17, 1)
|
||||
FIELD(PSW, PM, 20, 1)
|
||||
FIELD(PSW, IPL, 24, 4)
|
||||
|
||||
/* FPSW define */
|
||||
REG32(FPSW, 0)
|
||||
FIELD(FPSW, RM, 0, 2)
|
||||
FIELD(FPSW, CV, 2, 1)
|
||||
FIELD(FPSW, CO, 3, 1)
|
||||
FIELD(FPSW, CZ, 4, 1)
|
||||
FIELD(FPSW, CU, 5, 1)
|
||||
FIELD(FPSW, CX, 6, 1)
|
||||
FIELD(FPSW, CE, 7, 1)
|
||||
FIELD(FPSW, CAUSE, 2, 6)
|
||||
FIELD(FPSW, DN, 8, 1)
|
||||
FIELD(FPSW, EV, 10, 1)
|
||||
FIELD(FPSW, EO, 11, 1)
|
||||
FIELD(FPSW, EZ, 12, 1)
|
||||
FIELD(FPSW, EU, 13, 1)
|
||||
FIELD(FPSW, EX, 14, 1)
|
||||
FIELD(FPSW, ENABLE, 10, 5)
|
||||
FIELD(FPSW, FV, 26, 1)
|
||||
FIELD(FPSW, FO, 27, 1)
|
||||
FIELD(FPSW, FZ, 28, 1)
|
||||
FIELD(FPSW, FU, 29, 1)
|
||||
FIELD(FPSW, FX, 30, 1)
|
||||
FIELD(FPSW, FLAGS, 26, 4)
|
||||
FIELD(FPSW, FS, 31, 1)
|
||||
|
||||
enum {
|
||||
NUM_REGS = 16,
|
||||
};
|
||||
|
||||
typedef struct CPURXState {
|
||||
/* CPU registers */
|
||||
uint32_t regs[NUM_REGS]; /* general registers */
|
||||
uint32_t psw_o; /* O bit of status register */
|
||||
uint32_t psw_s; /* S bit of status register */
|
||||
uint32_t psw_z; /* Z bit of status register */
|
||||
uint32_t psw_c; /* C bit of status register */
|
||||
uint32_t psw_u;
|
||||
uint32_t psw_i;
|
||||
uint32_t psw_pm;
|
||||
uint32_t psw_ipl;
|
||||
uint32_t bpsw; /* backup status */
|
||||
uint32_t bpc; /* backup pc */
|
||||
uint32_t isp; /* global base register */
|
||||
uint32_t usp; /* vector base register */
|
||||
uint32_t pc; /* program counter */
|
||||
uint32_t intb; /* interrupt vector */
|
||||
uint32_t fintv;
|
||||
uint32_t fpsw;
|
||||
uint64_t acc;
|
||||
|
||||
/* Fields up to this point are cleared by a CPU reset */
|
||||
struct {} end_reset_fields;
|
||||
|
||||
/* Internal use */
|
||||
uint32_t in_sleep;
|
||||
uint32_t req_irq; /* Requested interrupt no (hard) */
|
||||
uint32_t req_ipl; /* Requested interrupt level */
|
||||
uint32_t ack_irq; /* execute irq */
|
||||
uint32_t ack_ipl; /* execute ipl */
|
||||
float_status fp_status;
|
||||
qemu_irq ack; /* Interrupt acknowledge */
|
||||
} CPURXState;
|
||||
|
||||
/*
|
||||
* RXCPU:
|
||||
* @env: #CPURXState
|
||||
*
|
||||
* A RX CPU
|
||||
*/
|
||||
struct RXCPU {
|
||||
/*< private >*/
|
||||
CPUState parent_obj;
|
||||
/*< public >*/
|
||||
|
||||
CPUNegativeOffsetState neg;
|
||||
CPURXState env;
|
||||
};
|
||||
|
||||
typedef struct RXCPU RXCPU;
|
||||
typedef RXCPU ArchCPU;
|
||||
|
||||
#define ENV_OFFSET offsetof(RXCPU, env)
|
||||
|
||||
#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
|
||||
#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
|
||||
#define CPU_RESOLVING_TYPE TYPE_RX_CPU
|
||||
|
||||
const char *rx_crname(uint8_t cr);
|
||||
void rx_cpu_do_interrupt(CPUState *cpu);
|
||||
bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
|
||||
void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
|
||||
int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
|
||||
int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
||||
hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
||||
|
||||
void rx_translate_init(void);
|
||||
int cpu_rx_signal_handler(int host_signum, void *pinfo,
|
||||
void *puc);
|
||||
|
||||
void rx_cpu_list(void);
|
||||
void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
|
||||
|
||||
#define cpu_signal_handler cpu_rx_signal_handler
|
||||
#define cpu_list rx_cpu_list
|
||||
|
||||
#include "exec/cpu-all.h"
|
||||
|
||||
#define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0
|
||||
#define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1
|
||||
|
||||
#define RX_CPU_IRQ 0
|
||||
#define RX_CPU_FIR 1
|
||||
|
||||
static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc,
|
||||
target_ulong *cs_base, uint32_t *flags)
|
||||
{
|
||||
*pc = env->pc;
|
||||
*cs_base = 0;
|
||||
*flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
|
||||
}
|
||||
|
||||
static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
|
||||
{
|
||||
uint32_t psw = 0;
|
||||
psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl);
|
||||
psw = FIELD_DP32(psw, PSW, PM, env->psw_pm);
|
||||
psw = FIELD_DP32(psw, PSW, U, env->psw_u);
|
||||
psw = FIELD_DP32(psw, PSW, I, env->psw_i);
|
||||
psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31);
|
||||
psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31);
|
||||
psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0);
|
||||
psw = FIELD_DP32(psw, PSW, C, env->psw_c);
|
||||
return psw;
|
||||
}
|
||||
|
||||
#endif /* RX_CPU_H */
|
||||
+1446
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,112 @@
|
||||
/*
|
||||
* RX gdb server stub
|
||||
*
|
||||
* Copyright (c) 2019 Yoshinori Sato
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include "qemu/osdep.h"
|
||||
#include "qemu-common.h"
|
||||
#include "cpu.h"
|
||||
#include "exec/gdbstub.h"
|
||||
|
||||
int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
|
||||
{
|
||||
RXCPU *cpu = RXCPU(cs);
|
||||
CPURXState *env = &cpu->env;
|
||||
|
||||
switch (n) {
|
||||
case 0 ... 15:
|
||||
return gdb_get_regl(mem_buf, env->regs[n]);
|
||||
case 16:
|
||||
return gdb_get_regl(mem_buf, (env->psw_u) ? env->regs[0] : env->usp);
|
||||
case 17:
|
||||
return gdb_get_regl(mem_buf, (!env->psw_u) ? env->regs[0] : env->isp);
|
||||
case 18:
|
||||
return gdb_get_regl(mem_buf, rx_cpu_pack_psw(env));
|
||||
case 19:
|
||||
return gdb_get_regl(mem_buf, env->pc);
|
||||
case 20:
|
||||
return gdb_get_regl(mem_buf, env->intb);
|
||||
case 21:
|
||||
return gdb_get_regl(mem_buf, env->bpsw);
|
||||
case 22:
|
||||
return gdb_get_regl(mem_buf, env->bpc);
|
||||
case 23:
|
||||
return gdb_get_regl(mem_buf, env->fintv);
|
||||
case 24:
|
||||
return gdb_get_regl(mem_buf, env->fpsw);
|
||||
case 25:
|
||||
return 0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
|
||||
{
|
||||
RXCPU *cpu = RXCPU(cs);
|
||||
CPURXState *env = &cpu->env;
|
||||
uint32_t psw;
|
||||
switch (n) {
|
||||
case 0 ... 15:
|
||||
env->regs[n] = ldl_p(mem_buf);
|
||||
if (n == 0) {
|
||||
if (env->psw_u) {
|
||||
env->usp = env->regs[0];
|
||||
} else {
|
||||
env->isp = env->regs[0];
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 16:
|
||||
env->usp = ldl_p(mem_buf);
|
||||
if (env->psw_u) {
|
||||
env->regs[0] = ldl_p(mem_buf);
|
||||
}
|
||||
break;
|
||||
case 17:
|
||||
env->isp = ldl_p(mem_buf);
|
||||
if (!env->psw_u) {
|
||||
env->regs[0] = ldl_p(mem_buf);
|
||||
}
|
||||
break;
|
||||
case 18:
|
||||
psw = ldl_p(mem_buf);
|
||||
rx_cpu_unpack_psw(env, psw, 1);
|
||||
break;
|
||||
case 19:
|
||||
env->pc = ldl_p(mem_buf);
|
||||
break;
|
||||
case 20:
|
||||
env->intb = ldl_p(mem_buf);
|
||||
break;
|
||||
case 21:
|
||||
env->bpsw = ldl_p(mem_buf);
|
||||
break;
|
||||
case 22:
|
||||
env->bpc = ldl_p(mem_buf);
|
||||
break;
|
||||
case 23:
|
||||
env->fintv = ldl_p(mem_buf);
|
||||
break;
|
||||
case 24:
|
||||
env->fpsw = ldl_p(mem_buf);
|
||||
break;
|
||||
case 25:
|
||||
return 8;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 4;
|
||||
}
|
||||
@@ -0,0 +1,149 @@
|
||||
/*
|
||||
* RX emulation
|
||||
*
|
||||
* Copyright (c) 2019 Yoshinori Sato
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qemu/bitops.h"
|
||||
#include "cpu.h"
|
||||
#include "exec/log.h"
|
||||
#include "exec/cpu_ldst.h"
|
||||
#include "sysemu/sysemu.h"
|
||||
#include "hw/irq.h"
|
||||
|
||||
void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte)
|
||||
{
|
||||
if (env->psw_pm == 0) {
|
||||
env->psw_ipl = FIELD_EX32(psw, PSW, IPL);
|
||||
if (rte) {
|
||||
/* PSW.PM can write RTE and RTFI */
|
||||
env->psw_pm = FIELD_EX32(psw, PSW, PM);
|
||||
}
|
||||
env->psw_u = FIELD_EX32(psw, PSW, U);
|
||||
env->psw_i = FIELD_EX32(psw, PSW, I);
|
||||
}
|
||||
env->psw_o = FIELD_EX32(psw, PSW, O) << 31;
|
||||
env->psw_s = FIELD_EX32(psw, PSW, S) << 31;
|
||||
env->psw_z = 1 - FIELD_EX32(psw, PSW, Z);
|
||||
env->psw_c = FIELD_EX32(psw, PSW, C);
|
||||
}
|
||||
|
||||
#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR)
|
||||
void rx_cpu_do_interrupt(CPUState *cs)
|
||||
{
|
||||
RXCPU *cpu = RXCPU(cs);
|
||||
CPURXState *env = &cpu->env;
|
||||
int do_irq = cs->interrupt_request & INT_FLAGS;
|
||||
uint32_t save_psw;
|
||||
|
||||
env->in_sleep = 0;
|
||||
|
||||
if (env->psw_u) {
|
||||
env->usp = env->regs[0];
|
||||
} else {
|
||||
env->isp = env->regs[0];
|
||||
}
|
||||
save_psw = rx_cpu_pack_psw(env);
|
||||
env->psw_pm = env->psw_i = env->psw_u = 0;
|
||||
|
||||
if (do_irq) {
|
||||
if (do_irq & CPU_INTERRUPT_FIR) {
|
||||
env->bpc = env->pc;
|
||||
env->bpsw = save_psw;
|
||||
env->pc = env->fintv;
|
||||
env->psw_ipl = 15;
|
||||
cs->interrupt_request &= ~CPU_INTERRUPT_FIR;
|
||||
qemu_set_irq(env->ack, env->ack_irq);
|
||||
qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n");
|
||||
} else if (do_irq & CPU_INTERRUPT_HARD) {
|
||||
env->isp -= 4;
|
||||
cpu_stl_data(env, env->isp, save_psw);
|
||||
env->isp -= 4;
|
||||
cpu_stl_data(env, env->isp, env->pc);
|
||||
env->pc = cpu_ldl_data(env, env->intb + env->ack_irq * 4);
|
||||
env->psw_ipl = env->ack_ipl;
|
||||
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
||||
qemu_set_irq(env->ack, env->ack_irq);
|
||||
qemu_log_mask(CPU_LOG_INT,
|
||||
"interrupt 0x%02x raised\n", env->ack_irq);
|
||||
}
|
||||
} else {
|
||||
uint32_t vec = cs->exception_index;
|
||||
const char *expname = "unknown exception";
|
||||
|
||||
env->isp -= 4;
|
||||
cpu_stl_data(env, env->isp, save_psw);
|
||||
env->isp -= 4;
|
||||
cpu_stl_data(env, env->isp, env->pc);
|
||||
|
||||
if (vec < 0x100) {
|
||||
env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4);
|
||||
} else {
|
||||
env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4);
|
||||
}
|
||||
switch (vec) {
|
||||
case 20:
|
||||
expname = "privilege violation";
|
||||
break;
|
||||
case 21:
|
||||
expname = "access exception";
|
||||
break;
|
||||
case 23:
|
||||
expname = "illegal instruction";
|
||||
break;
|
||||
case 25:
|
||||
expname = "fpu exception";
|
||||
break;
|
||||
case 30:
|
||||
expname = "non-maskable interrupt";
|
||||
break;
|
||||
case 0x100 ... 0x1ff:
|
||||
expname = "unconditional trap";
|
||||
}
|
||||
qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n",
|
||||
(vec & 0xff), expname);
|
||||
}
|
||||
env->regs[0] = env->isp;
|
||||
}
|
||||
|
||||
bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||
{
|
||||
RXCPU *cpu = RXCPU(cs);
|
||||
CPURXState *env = &cpu->env;
|
||||
int accept = 0;
|
||||
/* hardware interrupt (Normal) */
|
||||
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
||||
env->psw_i && (env->psw_ipl < env->req_ipl)) {
|
||||
env->ack_irq = env->req_irq;
|
||||
env->ack_ipl = env->req_ipl;
|
||||
accept = 1;
|
||||
}
|
||||
/* hardware interrupt (FIR) */
|
||||
if ((interrupt_request & CPU_INTERRUPT_FIR) &&
|
||||
env->psw_i && (env->psw_ipl < 15)) {
|
||||
accept = 1;
|
||||
}
|
||||
if (accept) {
|
||||
rx_cpu_do_interrupt(cs);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
||||
{
|
||||
return addr;
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
|
||||
DEF_HELPER_1(raise_access_fault, noreturn, env)
|
||||
DEF_HELPER_1(raise_privilege_violation, noreturn, env)
|
||||
DEF_HELPER_1(wait, noreturn, env)
|
||||
DEF_HELPER_1(debug, noreturn, env)
|
||||
DEF_HELPER_2(rxint, noreturn, env, i32)
|
||||
DEF_HELPER_1(rxbrk, noreturn, env)
|
||||
DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
|
||||
DEF_HELPER_FLAGS_3(fsub, TCG_CALL_NO_WG, f32, env, f32, f32)
|
||||
DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, f32, env, f32, f32)
|
||||
DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, f32, env, f32, f32)
|
||||
DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_WG, void, env, f32, f32)
|
||||
DEF_HELPER_FLAGS_2(ftoi, TCG_CALL_NO_WG, i32, env, f32)
|
||||
DEF_HELPER_FLAGS_2(round, TCG_CALL_NO_WG, i32, env, f32)
|
||||
DEF_HELPER_FLAGS_2(itof, TCG_CALL_NO_WG, f32, env, i32)
|
||||
DEF_HELPER_2(set_fpsw, void, env, i32)
|
||||
DEF_HELPER_FLAGS_2(racw, TCG_CALL_NO_WG, void, env, i32)
|
||||
DEF_HELPER_FLAGS_2(set_psw_rte, TCG_CALL_NO_WG, void, env, i32)
|
||||
DEF_HELPER_FLAGS_2(set_psw, TCG_CALL_NO_WG, void, env, i32)
|
||||
DEF_HELPER_1(pack_psw, i32, env)
|
||||
DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_1(scmpu, TCG_CALL_NO_WG, void, env)
|
||||
DEF_HELPER_1(smovu, void, env)
|
||||
DEF_HELPER_1(smovf, void, env)
|
||||
DEF_HELPER_1(smovb, void, env)
|
||||
DEF_HELPER_2(sstr, void, env, i32)
|
||||
DEF_HELPER_FLAGS_2(swhile, TCG_CALL_NO_WG, void, env, i32)
|
||||
DEF_HELPER_FLAGS_2(suntil, TCG_CALL_NO_WG, void, env, i32)
|
||||
DEF_HELPER_FLAGS_2(rmpa, TCG_CALL_NO_WG, void, env, i32)
|
||||
DEF_HELPER_1(satr, void, env)
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user