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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

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* x86 updates for Intel errata (myself, Eduardo)
* the big ugly list of x86 VMX features, which was targeted for 5.0 but
caused a Libvirt regression (myself)

# gpg: Signature made Thu 21 Nov 2019 15:35:13 GMT
# gpg:                using RSA key BFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  i386: Add -noTSX aliases for hle=off, rtm=off CPU models
  i386: Add new versions of Skylake/Cascadelake/Icelake without TSX
  target/i386: add support for MSR_IA32_TSX_CTRL
  target/i386: add VMX features to named CPU models

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2019-11-21 17:18:40 +00:00
parent 996970236c 02fa60d101
commit 2061735ff0
4 changed files with 796 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/i386/cpu.c
+758 -1
View File
File diff suppressed because it is too large Load Diff
target/i386/cpu.h
+5
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@@ -349,7 +349,11 @@ typedef enum X86Seg {
#define MSR_VIRT_SSBD 0xc001011f
#define MSR_IA32_PRED_CMD 0x49
#define MSR_IA32_CORE_CAPABILITY 0xcf
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
#define MSR_IA32_TSX_CTRL 0x122
#define MSR_IA32_TSCDEADLINE 0x6e0
#define FEATURE_CONTROL_LOCKED (1<<0)
@@ -1449,6 +1453,7 @@ typedef struct CPUX86State {
uint64_t msr_smi_count;
uint32_t pkru;
uint32_t tsx_ctrl;
uint64_t spec_ctrl;
uint64_t virt_ssbd;
target/i386/kvm.c
+13
View File
@@ -97,6 +97,7 @@ static bool has_msr_hv_reenlightenment;
static bool has_msr_xss;
static bool has_msr_umwait;
static bool has_msr_spec_ctrl;
static bool has_msr_tsx_ctrl;
static bool has_msr_virt_ssbd;
static bool has_msr_smi_count;
static bool has_msr_arch_capabs;
@@ -2036,6 +2037,9 @@ static int kvm_get_supported_msrs(KVMState *s)
case MSR_IA32_SPEC_CTRL:
has_msr_spec_ctrl = true;
break;
case MSR_IA32_TSX_CTRL:
has_msr_tsx_ctrl = true;
break;
case MSR_VIRT_SSBD:
has_msr_virt_ssbd = true;
break;
@@ -2694,6 +2698,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
}
if (has_msr_tsx_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
}
if (has_msr_virt_ssbd) {
kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
}
@@ -3110,6 +3117,9 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
}
if (has_msr_tsx_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
}
if (has_msr_virt_ssbd) {
kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
}
@@ -3502,6 +3512,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_SPEC_CTRL:
env->spec_ctrl = msrs[i].data;
break;
case MSR_IA32_TSX_CTRL:
env->tsx_ctrl = msrs[i].data;
break;
case MSR_VIRT_SSBD:
env->virt_ssbd = msrs[i].data;
break;
target/i386/machine.c
+20
View File
@@ -1293,6 +1293,25 @@ static const VMStateDescription vmstate_efer32 = {
};
#endif
static bool msr_tsx_ctrl_needed(void *opaque)
{
X86CPU *cpu = opaque;
CPUX86State *env = &cpu->env;
return env->features[FEAT_ARCH_CAPABILITIES] & ARCH_CAP_TSX_CTRL_MSR;
}
static const VMStateDescription vmstate_msr_tsx_ctrl = {
.name = "cpu/msr_tsx_ctrl",
.version_id = 1,
.minimum_version_id = 1,
.needed = msr_tsx_ctrl_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.tsx_ctrl, X86CPU),
VMSTATE_END_OF_LIST()
}
};
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -1427,6 +1446,7 @@ VMStateDescription vmstate_x86_cpu = {
#ifdef CONFIG_KVM
&vmstate_nested_state,
#endif
&vmstate_msr_tsx_ctrl,
NULL
}
};